1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/stm32_i2c.h> 14 #include <io.h> 15 #include <kernel/delay.h> 16 #include <kernel/dt.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <libfdt.h> 20 #include <stdbool.h> 21 #include <stdlib.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 25 /* STM32 I2C registers offsets */ 26 #define I2C_CR1 0x00U 27 #define I2C_CR2 0x04U 28 #define I2C_OAR1 0x08U 29 #define I2C_OAR2 0x0CU 30 #define I2C_TIMINGR 0x10U 31 #define I2C_TIMEOUTR 0x14U 32 #define I2C_ISR 0x18U 33 #define I2C_ICR 0x1CU 34 #define I2C_PECR 0x20U 35 #define I2C_RXDR 0x24U 36 #define I2C_TXDR 0x28U 37 38 /* Bit definition for I2C_CR1 register */ 39 #define I2C_CR1_PE BIT(0) 40 #define I2C_CR1_TXIE BIT(1) 41 #define I2C_CR1_RXIE BIT(2) 42 #define I2C_CR1_ADDRIE BIT(3) 43 #define I2C_CR1_NACKIE BIT(4) 44 #define I2C_CR1_STOPIE BIT(5) 45 #define I2C_CR1_TCIE BIT(6) 46 #define I2C_CR1_ERRIE BIT(7) 47 #define I2C_CR1_DNF GENMASK_32(11, 8) 48 #define I2C_CR1_ANFOFF BIT(12) 49 #define I2C_CR1_SWRST BIT(13) 50 #define I2C_CR1_TXDMAEN BIT(14) 51 #define I2C_CR1_RXDMAEN BIT(15) 52 #define I2C_CR1_SBC BIT(16) 53 #define I2C_CR1_NOSTRETCH BIT(17) 54 #define I2C_CR1_WUPEN BIT(18) 55 #define I2C_CR1_GCEN BIT(19) 56 #define I2C_CR1_SMBHEN BIT(22) 57 #define I2C_CR1_SMBDEN BIT(21) 58 #define I2C_CR1_ALERTEN BIT(22) 59 #define I2C_CR1_PECEN BIT(23) 60 61 /* Bit definition for I2C_CR2 register */ 62 #define I2C_CR2_SADD GENMASK_32(9, 0) 63 #define I2C_CR2_RD_WRN BIT(10) 64 #define I2C_CR2_RD_WRN_OFFSET 10U 65 #define I2C_CR2_ADD10 BIT(11) 66 #define I2C_CR2_HEAD10R BIT(12) 67 #define I2C_CR2_START BIT(13) 68 #define I2C_CR2_STOP BIT(14) 69 #define I2C_CR2_NACK BIT(15) 70 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 71 #define I2C_CR2_NBYTES_OFFSET 16U 72 #define I2C_CR2_RELOAD BIT(24) 73 #define I2C_CR2_AUTOEND BIT(25) 74 #define I2C_CR2_PECBYTE BIT(26) 75 76 /* Bit definition for I2C_OAR1 register */ 77 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 78 #define I2C_OAR1_OA1MODE BIT(10) 79 #define I2C_OAR1_OA1EN BIT(15) 80 81 /* Bit definition for I2C_OAR2 register */ 82 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 83 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 84 #define I2C_OAR2_OA2NOMASK 0 85 #define I2C_OAR2_OA2MASK01 BIT(8) 86 #define I2C_OAR2_OA2MASK02 BIT(9) 87 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 88 #define I2C_OAR2_OA2MASK04 BIT(10) 89 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 90 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 91 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 92 #define I2C_OAR2_OA2EN BIT(15) 93 94 /* Bit definition for I2C_TIMINGR register */ 95 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 96 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 97 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 98 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 99 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 100 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 101 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 102 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 103 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 104 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 105 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 106 (I2C_TIMINGR_SCLL_MAX - 1)) 107 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 108 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 109 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 110 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 111 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 112 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 113 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 114 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 115 116 /* Bit definition for I2C_TIMEOUTR register */ 117 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 118 #define I2C_TIMEOUTR_TIDLE BIT(12) 119 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 120 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 121 #define I2C_TIMEOUTR_TEXTEN BIT(31) 122 123 /* Bit definition for I2C_ISR register */ 124 #define I2C_ISR_TXE BIT(0) 125 #define I2C_ISR_TXIS BIT(1) 126 #define I2C_ISR_RXNE BIT(2) 127 #define I2C_ISR_ADDR BIT(3) 128 #define I2C_ISR_NACKF BIT(4) 129 #define I2C_ISR_STOPF BIT(5) 130 #define I2C_ISR_TC BIT(6) 131 #define I2C_ISR_TCR BIT(7) 132 #define I2C_ISR_BERR BIT(8) 133 #define I2C_ISR_ARLO BIT(9) 134 #define I2C_ISR_OVR BIT(10) 135 #define I2C_ISR_PECERR BIT(11) 136 #define I2C_ISR_TIMEOUT BIT(12) 137 #define I2C_ISR_ALERT BIT(13) 138 #define I2C_ISR_BUSY BIT(15) 139 #define I2C_ISR_DIR BIT(16) 140 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 141 142 /* Bit definition for I2C_ICR register */ 143 #define I2C_ICR_ADDRCF BIT(3) 144 #define I2C_ICR_NACKCF BIT(4) 145 #define I2C_ICR_STOPCF BIT(5) 146 #define I2C_ICR_BERRCF BIT(8) 147 #define I2C_ICR_ARLOCF BIT(9) 148 #define I2C_ICR_OVRCF BIT(10) 149 #define I2C_ICR_PECCF BIT(11) 150 #define I2C_ICR_TIMOUTCF BIT(12) 151 #define I2C_ICR_ALERTCF BIT(13) 152 153 /* Max data size for a single I2C transfer */ 154 #define MAX_NBYTE_SIZE 255U 155 156 #define I2C_NSEC_PER_SEC 1000000000L 157 #define I2C_TIMEOUT_BUSY_MS 25 158 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000) 159 160 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 161 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 162 I2C_CR2_RD_WRN) 163 164 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 165 I2C_TIMINGR_SDADEL | \ 166 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 167 168 /* 169 * I2C transfer modes 170 * I2C_RELOAD: Enable Reload mode 171 * I2C_AUTOEND_MODE: Enable automatic end mode 172 * I2C_SOFTEND_MODE: Enable software end mode 173 */ 174 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 175 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 176 #define I2C_SOFTEND_MODE 0x0 177 178 /* 179 * Start/restart/stop I2C transfer requests. 180 * 181 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 182 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 183 * I2C_GENERATE_START_READ: Generate Restart for read request. 184 * I2C_GENERATE_START_WRITE: Generate Restart for write request 185 */ 186 #define I2C_NO_STARTSTOP 0x0 187 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 188 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 189 I2C_CR2_RD_WRN) 190 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 191 192 /* Memory address byte sizes */ 193 #define I2C_MEMADD_SIZE_8BIT 1 194 #define I2C_MEMADD_SIZE_16BIT 2 195 196 /* 197 * struct i2c_spec_s - Private I2C timing specifications. 198 * @rate: I2C bus speed (Hz) 199 * @rate_min: 80% of I2C bus speed (Hz) 200 * @rate_max: 120% of I2C bus speed (Hz) 201 * @fall_max: Max fall time of both SDA and SCL signals (ns) 202 * @rise_max: Max rise time of both SDA and SCL signals (ns) 203 * @hddat_min: Min data hold time (ns) 204 * @vddat_max: Max data valid time (ns) 205 * @sudat_min: Min data setup time (ns) 206 * @l_min: Min low period of the SCL clock (ns) 207 * @h_min: Min high period of the SCL clock (ns) 208 */ 209 struct i2c_spec_s { 210 uint32_t rate; 211 uint32_t rate_min; 212 uint32_t rate_max; 213 uint32_t fall_max; 214 uint32_t rise_max; 215 uint32_t hddat_min; 216 uint32_t vddat_max; 217 uint32_t sudat_min; 218 uint32_t l_min; 219 uint32_t h_min; 220 }; 221 222 /* 223 * struct i2c_timing_s - Private I2C output parameters. 224 * @scldel: Data setup time 225 * @sdadel: Data hold time 226 * @sclh: SCL high period (master mode) 227 * @sclh: SCL low period (master mode) 228 * @is_saved: True if relating to a configuration candidate 229 */ 230 struct i2c_timing_s { 231 uint8_t scldel; 232 uint8_t sdadel; 233 uint8_t sclh; 234 uint8_t scll; 235 bool is_saved; 236 }; 237 238 static const struct i2c_spec_s i2c_specs[] = { 239 [I2C_SPEED_STANDARD] = { 240 .rate = I2C_STANDARD_RATE, 241 .rate_min = (I2C_STANDARD_RATE * 80) / 100, 242 .rate_max = (I2C_STANDARD_RATE * 120) / 100, 243 .fall_max = 300, 244 .rise_max = 1000, 245 .hddat_min = 0, 246 .vddat_max = 3450, 247 .sudat_min = 250, 248 .l_min = 4700, 249 .h_min = 4000, 250 }, 251 [I2C_SPEED_FAST] = { 252 .rate = I2C_FAST_RATE, 253 .rate_min = (I2C_FAST_RATE * 80) / 100, 254 .rate_max = (I2C_FAST_RATE * 120) / 100, 255 .fall_max = 300, 256 .rise_max = 300, 257 .hddat_min = 0, 258 .vddat_max = 900, 259 .sudat_min = 100, 260 .l_min = 1300, 261 .h_min = 600, 262 }, 263 [I2C_SPEED_FAST_PLUS] = { 264 .rate = I2C_FAST_PLUS_RATE, 265 .rate_min = (I2C_FAST_PLUS_RATE * 80) / 100, 266 .rate_max = (I2C_FAST_PLUS_RATE * 120) / 100, 267 .fall_max = 100, 268 .rise_max = 120, 269 .hddat_min = 0, 270 .vddat_max = 450, 271 .sudat_min = 50, 272 .l_min = 500, 273 .h_min = 260, 274 }, 275 }; 276 277 /* 278 * I2C request parameters 279 * @dev_addr: I2C address of the target device 280 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 281 * @mem_addr: Target memory cell accessed in device (memory mode) 282 * @mem_addr_size: Byte size of the memory cell address (memory mode) 283 * @timeout_ms: Timeout in millisenconds for the request 284 */ 285 struct i2c_request { 286 uint32_t dev_addr; 287 enum i2c_mode_e mode; 288 uint32_t mem_addr; 289 uint32_t mem_addr_size; 290 unsigned int timeout_ms; 291 }; 292 293 static vaddr_t get_base(struct i2c_handle_s *hi2c) 294 { 295 return io_pa_or_va_secure(&hi2c->base); 296 } 297 298 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 299 { 300 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 301 hi2c->i2c_state = I2C_STATE_READY; 302 } 303 304 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 305 { 306 vaddr_t base = get_base(hi2c); 307 308 stm32_clock_enable(hi2c->clock); 309 310 cfg->cr1 = io_read32(base + I2C_CR1); 311 cfg->cr2 = io_read32(base + I2C_CR2); 312 cfg->oar1 = io_read32(base + I2C_OAR1); 313 cfg->oar2 = io_read32(base + I2C_OAR2); 314 cfg->timingr = io_read32(base + I2C_TIMINGR); 315 316 stm32_clock_disable(hi2c->clock); 317 } 318 319 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 320 { 321 vaddr_t base = get_base(hi2c); 322 323 stm32_clock_enable(hi2c->clock); 324 325 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 326 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 327 io_write32(base + I2C_OAR1, cfg->oar1); 328 io_write32(base + I2C_CR2, cfg->cr2); 329 io_write32(base + I2C_OAR2, cfg->oar2); 330 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 331 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 332 333 stm32_clock_disable(hi2c->clock); 334 } 335 336 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 337 { 338 DMSG("CR1: 0x%" PRIx32, cfg->cr1); 339 DMSG("CR2: 0x%" PRIx32, cfg->cr2); 340 DMSG("OAR1: 0x%" PRIx32, cfg->oar1); 341 DMSG("OAR2: 0x%" PRIx32, cfg->oar2); 342 DMSG("TIM: 0x%" PRIx32, cfg->timingr); 343 } 344 345 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 346 { 347 vaddr_t __maybe_unused base = get_base(hi2c); 348 349 stm32_clock_enable(hi2c->clock); 350 351 DMSG("CR1: 0x%" PRIx32, io_read32(base + I2C_CR1)); 352 DMSG("CR2: 0x%" PRIx32, io_read32(base + I2C_CR2)); 353 DMSG("OAR1: 0x%" PRIx32, io_read32(base + I2C_OAR1)); 354 DMSG("OAR2: 0x%" PRIx32, io_read32(base + I2C_OAR2)); 355 DMSG("TIM: 0x%" PRIx32, io_read32(base + I2C_TIMINGR)); 356 357 stm32_clock_disable(hi2c->clock); 358 } 359 360 /* 361 * Compute the I2C device timings 362 * 363 * @init: Ref to the initialization configuration structure 364 * @clock_src: I2C clock source frequency (Hz) 365 * @timing: Pointer to the final computed timing result 366 * Return 0 on success or a negative value 367 */ 368 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 369 uint32_t clock_src, uint32_t *timing) 370 { 371 enum i2c_speed_e mode = init->speed_mode; 372 uint32_t speed_freq = i2c_specs[mode].rate; 373 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 374 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 375 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 376 uint32_t af_delay_min = 0; 377 uint32_t af_delay_max = 0; 378 uint32_t dnf_delay = 0; 379 uint32_t tsync = 0; 380 uint32_t clk_min = 0; 381 uint32_t clk_max = 0; 382 int clk_error_prev = 0; 383 uint16_t p = 0; 384 uint16_t l = 0; 385 uint16_t a = 0; 386 uint16_t h = 0; 387 unsigned int sdadel_min = 0; 388 unsigned int sdadel_max = 0; 389 unsigned int scldel_min = 0; 390 unsigned int delay = 0; 391 int s = -1; 392 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 393 394 switch (mode) { 395 case I2C_SPEED_STANDARD: 396 case I2C_SPEED_FAST: 397 case I2C_SPEED_FAST_PLUS: 398 break; 399 default: 400 EMSG("I2C speed out of bound {%d/%d}", 401 mode, I2C_SPEED_FAST_PLUS); 402 return -1; 403 } 404 405 speed_freq = i2c_specs[mode].rate; 406 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 407 clk_error_prev = INT_MAX; 408 409 if ((init->rise_time > i2c_specs[mode].rise_max) || 410 (init->fall_time > i2c_specs[mode].fall_max)) { 411 EMSG(" I2C timings out of bound: Rise{%d > %d}/Fall{%d > %d}", 412 init->rise_time, i2c_specs[mode].rise_max, 413 init->fall_time, i2c_specs[mode].fall_max); 414 return -1; 415 } 416 417 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 418 EMSG("DNF out of bound %d/%d", 419 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 420 return -1; 421 } 422 423 /* Analog and Digital Filters */ 424 if (init->analog_filter) { 425 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 426 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 427 } 428 dnf_delay = init->digital_filter_coef * i2cclk; 429 430 sdadel_min = i2c_specs[mode].hddat_min + init->fall_time; 431 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 432 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 433 sdadel_min = 0; 434 435 sdadel_max = i2c_specs[mode].vddat_max - init->rise_time; 436 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 437 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 438 sdadel_max = 0; 439 440 scldel_min = init->rise_time + i2c_specs[mode].sudat_min; 441 442 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 443 sdadel_min, sdadel_max, scldel_min); 444 445 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 446 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 447 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 448 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 449 450 if (scldel < scldel_min) 451 continue; 452 453 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 454 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 455 456 if ((sdadel >= sdadel_min) && 457 (sdadel <= sdadel_max) && 458 (p != p_prev)) { 459 solutions[p].scldel = l; 460 solutions[p].sdadel = a; 461 solutions[p].is_saved = true; 462 p_prev = p; 463 break; 464 } 465 } 466 467 if (p_prev == p) 468 break; 469 } 470 } 471 472 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 473 EMSG(" I2C no Prescaler solution"); 474 return -1; 475 } 476 477 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 478 clk_max = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_min; 479 clk_min = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_max; 480 481 /* 482 * Among prescaler possibilities discovered above figures out SCL Low 483 * and High Period. Provided: 484 * - SCL Low Period has to be higher than Low Period of the SCL Clock 485 * defined by I2C Specification. I2C Clock has to be lower than 486 * (SCL Low Period - Analog/Digital filters) / 4. 487 * - SCL High Period has to be lower than High Period of the SCL Clock 488 * defined by I2C Specification. 489 * - I2C Clock has to be lower than SCL High Period. 490 */ 491 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 492 uint32_t prescaler = (p + 1) * i2cclk; 493 494 if (!solutions[p].is_saved) 495 continue; 496 497 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 498 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 499 500 if ((tscl_l < i2c_specs[mode].l_min) || 501 (i2cclk >= 502 ((tscl_l - af_delay_min - dnf_delay) / 4))) 503 continue; 504 505 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 506 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 507 uint32_t tscl = tscl_l + tscl_h + 508 init->rise_time + 509 init->fall_time; 510 511 if ((tscl >= clk_min) && (tscl <= clk_max) && 512 (tscl_h >= i2c_specs[mode].h_min) && 513 (i2cclk < tscl_h)) { 514 int clk_error = tscl - i2cbus; 515 516 if (clk_error < 0) 517 clk_error = -clk_error; 518 519 if (clk_error < clk_error_prev) { 520 clk_error_prev = clk_error; 521 solutions[p].scll = l; 522 solutions[p].sclh = h; 523 s = p; 524 } 525 } 526 } 527 } 528 } 529 530 if (s < 0) { 531 EMSG(" I2C no solution at all"); 532 return -1; 533 } 534 535 /* Finalize timing settings */ 536 *timing = I2C_SET_TIMINGR_PRESC(s) | 537 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 538 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 539 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 540 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 541 542 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%i/%i", 543 s, solutions[s].scldel, solutions[s].sdadel); 544 DMSG("I2C TIMINGR (SCLH/SCLL): %i/%i", 545 solutions[s].sclh, solutions[s].scll); 546 DMSG("I2C TIMINGR: 0x%x", *timing); 547 548 return 0; 549 } 550 551 /* 552 * Setup the I2C device timings 553 * 554 * @hi2c: I2C handle structure 555 * @init: Ref to the initialization configuration structure 556 * @timing: Output TIMINGR register configuration value 557 * @retval 0 if OK, negative value else 558 */ 559 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 560 struct stm32_i2c_init_s *init, 561 uint32_t *timing) 562 { 563 int rc = 0; 564 uint32_t clock_src = stm32_clock_get_rate(hi2c->clock); 565 566 if (!clock_src) { 567 EMSG("Null I2C clock rate"); 568 return -1; 569 } 570 571 /* 572 * If the timing has already been computed, and the frequency is the 573 * same as when it was computed, then use the saved timing. 574 */ 575 if (clock_src == hi2c->saved_frequency) { 576 *timing = hi2c->saved_timing; 577 return 0; 578 } 579 580 do { 581 rc = i2c_compute_timing(init, clock_src, timing); 582 if (rc) { 583 EMSG("Failed to compute I2C timings"); 584 if (init->speed_mode > I2C_SPEED_STANDARD) { 585 init->speed_mode--; 586 IMSG("Downgrade I2C speed to %uHz)", 587 i2c_specs[init->speed_mode].rate); 588 } else { 589 break; 590 } 591 } 592 } while (rc); 593 594 if (rc) { 595 EMSG("Impossible to compute I2C timings"); 596 return rc; 597 } 598 599 DMSG("I2C Speed Mode(%i), Freq(%i), Clk Source(%i)", 600 init->speed_mode, i2c_specs[init->speed_mode].rate, clock_src); 601 DMSG("I2C Rise(%i) and Fall(%i) Time", 602 init->rise_time, init->fall_time); 603 DMSG("I2C Analog Filter(%s), DNF(%i)", 604 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 605 606 hi2c->saved_timing = *timing; 607 hi2c->saved_frequency = clock_src; 608 609 return 0; 610 } 611 612 /* 613 * Configure I2C Analog noise filter. 614 * @hi2c: I2C handle structure 615 * @analog_filter_on: True if enabling analog filter, false otherwise 616 * Return 0 on success or a negative value 617 */ 618 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c, 619 bool analog_filter_on) 620 { 621 vaddr_t base = get_base(hi2c); 622 623 if (hi2c->i2c_state != I2C_STATE_READY) 624 return -1; 625 626 hi2c->i2c_state = I2C_STATE_BUSY; 627 628 /* Disable the selected I2C peripheral */ 629 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 630 631 /* Reset I2Cx ANOFF bit */ 632 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 633 634 /* Set analog filter bit if filter is disabled */ 635 if (!analog_filter_on) 636 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 637 638 /* Enable the selected I2C peripheral */ 639 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 640 641 hi2c->i2c_state = I2C_STATE_READY; 642 643 return 0; 644 } 645 646 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 647 struct stm32_i2c_init_s *init, 648 struct stm32_pinctrl **pinctrl, 649 size_t *pinctrl_count) 650 { 651 const fdt32_t *cuint = NULL; 652 struct dt_node_info info = { .status = 0 }; 653 int count = 0; 654 655 /* Default STM32 specific configs caller may need to overwrite */ 656 memset(init, 0, sizeof(*init)); 657 658 _fdt_fill_device_info(fdt, &info, node); 659 init->dt_status = info.status; 660 init->pbase = info.reg; 661 init->clock = info.clock; 662 assert(info.reg != DT_INFO_INVALID_REG && 663 info.clock != DT_INFO_INVALID_CLOCK); 664 665 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 666 if (cuint) 667 init->rise_time = fdt32_to_cpu(*cuint); 668 else 669 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 670 671 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 672 if (cuint) 673 init->fall_time = fdt32_to_cpu(*cuint); 674 else 675 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 676 677 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 678 if (cuint) { 679 switch (fdt32_to_cpu(*cuint)) { 680 case I2C_STANDARD_RATE: 681 init->speed_mode = I2C_SPEED_STANDARD; 682 break; 683 case I2C_FAST_RATE: 684 init->speed_mode = I2C_SPEED_FAST; 685 break; 686 case I2C_FAST_PLUS_RATE: 687 init->speed_mode = I2C_SPEED_FAST_PLUS; 688 break; 689 default: 690 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 691 break; 692 } 693 } else { 694 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 695 } 696 697 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 698 if (count <= 0) { 699 *pinctrl = NULL; 700 *pinctrl_count = 0; 701 return count; 702 } 703 704 if (count > 2) 705 panic("Too many PINCTRLs found"); 706 707 *pinctrl = calloc(count, sizeof(**pinctrl)); 708 if (!*pinctrl) 709 panic(); 710 711 *pinctrl_count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, 712 *pinctrl, count); 713 assert(*pinctrl_count == (unsigned int)count); 714 715 return 0; 716 } 717 718 int stm32_i2c_init(struct i2c_handle_s *hi2c, 719 struct stm32_i2c_init_s *init_data) 720 { 721 int rc = 0; 722 uint32_t timing = 0; 723 vaddr_t base = 0; 724 uint32_t val = 0; 725 726 hi2c->dt_status = init_data->dt_status; 727 hi2c->base.pa = init_data->pbase; 728 hi2c->clock = init_data->clock; 729 730 rc = i2c_setup_timing(hi2c, init_data, &timing); 731 if (rc) 732 return rc; 733 734 stm32_clock_enable(hi2c->clock); 735 base = get_base(hi2c); 736 hi2c->i2c_state = I2C_STATE_BUSY; 737 738 /* Disable the selected I2C peripheral */ 739 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 740 741 /* Configure I2Cx: Frequency range */ 742 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 743 744 /* Disable Own Address1 before set the Own Address1 configuration */ 745 io_write32(base + I2C_OAR1, 0); 746 747 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 748 if (init_data->addr_mode_10b_not_7b) 749 io_write32(base + I2C_OAR1, 750 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 751 init_data->own_address1); 752 else 753 io_write32(base + I2C_OAR1, 754 I2C_OAR1_OA1EN | init_data->own_address1); 755 756 /* Configure I2Cx: Addressing Master mode */ 757 io_write32(base + I2C_CR2, 0); 758 if (init_data->addr_mode_10b_not_7b) 759 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 760 761 /* 762 * Enable the AUTOEND by default, and enable NACK 763 * (should be disabled only during Slave process). 764 */ 765 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 766 767 /* Disable Own Address2 before set the Own Address2 configuration */ 768 io_write32(base + I2C_OAR2, 0); 769 770 /* Configure I2Cx: Dual mode and Own Address2 */ 771 if (init_data->dual_address_mode) 772 io_write32(base + I2C_OAR2, 773 I2C_OAR2_OA2EN | init_data->own_address2 | 774 (init_data->own_address2_masks << 8)); 775 776 /* Configure I2Cx: Generalcall and NoStretch mode */ 777 val = 0; 778 if (init_data->general_call_mode) 779 val |= I2C_CR1_GCEN; 780 if (init_data->no_stretch_mode) 781 val |= I2C_CR1_NOSTRETCH; 782 io_write32(base + I2C_CR1, val); 783 784 /* Enable the selected I2C peripheral */ 785 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 786 787 hi2c->i2c_err = I2C_ERROR_NONE; 788 hi2c->i2c_state = I2C_STATE_READY; 789 790 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter); 791 if (rc) 792 EMSG("I2C analog filter error %d", rc); 793 794 stm32_clock_disable(hi2c->clock); 795 796 return rc; 797 } 798 799 /* I2C transmit (TX) data register flush sequence */ 800 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 801 { 802 vaddr_t base = get_base(hi2c); 803 804 /* 805 * If a pending TXIS flag is set, 806 * write a dummy data in TXDR to clear it. 807 */ 808 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 809 io_write32(base + I2C_TXDR, 0); 810 811 /* Flush TX register if not empty */ 812 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 813 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 814 } 815 816 /* 817 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 818 * 819 * @hi2c: I2C handle structure 820 * @bit_mask: Bit mask for the target single bit position to consider 821 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 822 * @timeout_ref: Expriation timeout reference 823 * Return 0 on success and a non-zero value on timeout 824 */ 825 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 826 unsigned int awaited_value, uint64_t timeout_ref) 827 { 828 vaddr_t isr = get_base(hi2c) + I2C_ISR; 829 830 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 831 832 /* May timeout while TEE thread is suspended */ 833 while (!timeout_elapsed(timeout_ref)) 834 if (!!(io_read32(isr) & bit_mask) == awaited_value) 835 break; 836 837 if (!!(io_read32(isr) & bit_mask) == awaited_value) 838 return 0; 839 840 notif_i2c_timeout(hi2c); 841 return -1; 842 } 843 844 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 845 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 846 { 847 vaddr_t base = get_base(hi2c); 848 849 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 850 return 0; 851 852 /* 853 * Wait until STOP Flag is reset. Use polling method. 854 * AutoEnd should be initiate after AF. 855 * Timeout may elpased while TEE thread is suspended. 856 */ 857 while (!timeout_elapsed(timeout_ref)) 858 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 859 break; 860 861 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 862 notif_i2c_timeout(hi2c); 863 return -1; 864 } 865 866 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 867 868 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 869 870 i2c_flush_txdr(hi2c); 871 872 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 873 874 hi2c->i2c_err |= I2C_ERROR_ACKF; 875 hi2c->i2c_state = I2C_STATE_READY; 876 877 return -1; 878 } 879 880 /* Wait TXIS bit is 1 in I2C_ISR register */ 881 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 882 { 883 while (!timeout_elapsed(timeout_ref)) { 884 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 885 break; 886 if (i2c_ack_failed(hi2c, timeout_ref)) 887 return -1; 888 } 889 890 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 891 return 0; 892 893 if (i2c_ack_failed(hi2c, timeout_ref)) 894 return -1; 895 896 notif_i2c_timeout(hi2c); 897 return -1; 898 } 899 900 /* Wait STOPF bit is 1 in I2C_ISR register */ 901 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 902 { 903 while (!timeout_elapsed(timeout_ref)) { 904 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 905 break; 906 907 if (i2c_ack_failed(hi2c, timeout_ref)) 908 return -1; 909 } 910 911 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 912 return 0; 913 914 if (i2c_ack_failed(hi2c, timeout_ref)) 915 return -1; 916 917 notif_i2c_timeout(hi2c); 918 return -1; 919 } 920 921 /* 922 * Load I2C_CR2 register for a I2C transfer 923 * 924 * @hi2c: I2C handle structure 925 * @dev_addr: Slave address to be transferred 926 * @size: Number of bytes to be transferred 927 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 928 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 929 * I2C_GENERATE_START_{READ|WRITE} 930 */ 931 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 932 uint32_t size, uint32_t i2c_mode, 933 uint32_t startstop) 934 { 935 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 936 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 937 (I2C_CR2_RD_WRN & 938 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 939 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 940 ((size << I2C_CR2_NBYTES_OFFSET) & 941 I2C_CR2_NBYTES) | 942 i2c_mode | startstop; 943 944 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 945 } 946 947 /* 948 * Master sends target device address followed by internal memory 949 * address for a memory write request. 950 * Function returns 0 on success or a negative value. 951 */ 952 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 953 struct i2c_request *request, 954 uint64_t timeout_ref) 955 { 956 vaddr_t base = get_base(hi2c); 957 958 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 959 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 960 961 if (i2c_wait_txis(hi2c, timeout_ref)) 962 return -1; 963 964 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 965 /* Send memory address */ 966 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 967 } else { 968 /* Send MSB of memory address */ 969 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 970 971 if (i2c_wait_txis(hi2c, timeout_ref)) 972 return -1; 973 974 /* Send LSB of memory address */ 975 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 976 } 977 978 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 979 return -1; 980 981 return 0; 982 } 983 984 /* 985 * Master sends target device address followed by internal memory 986 * address to prepare a memory read request. 987 * Function returns 0 on success or a negative value. 988 */ 989 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 990 struct i2c_request *request, 991 uint64_t timeout_ref) 992 { 993 vaddr_t base = get_base(hi2c); 994 995 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 996 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 997 998 if (i2c_wait_txis(hi2c, timeout_ref)) 999 return -1; 1000 1001 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 1002 /* Send memory address */ 1003 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1004 } else { 1005 /* Send MSB of memory address */ 1006 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 1007 1008 if (i2c_wait_txis(hi2c, timeout_ref)) 1009 return -1; 1010 1011 /* Send LSB of memory address */ 1012 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1013 } 1014 1015 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 1016 return -1; 1017 1018 return 0; 1019 } 1020 1021 /* 1022 * Write an amount of data in blocking mode 1023 * 1024 * @hi2c: Reference to struct i2c_handle_s 1025 * @request: I2C request parameters 1026 * @p_data: Pointer to data buffer 1027 * @size: Amount of data to be sent 1028 * Return 0 on success or a negative value 1029 */ 1030 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1031 uint8_t *p_data, uint16_t size) 1032 { 1033 uint64_t timeout_ref = 0; 1034 vaddr_t base = get_base(hi2c); 1035 int rc = -1; 1036 uint8_t *p_buff = p_data; 1037 size_t xfer_size = 0; 1038 size_t xfer_count = size; 1039 1040 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1041 return -1; 1042 1043 if (hi2c->i2c_state != I2C_STATE_READY) 1044 return -1; 1045 1046 if (!p_data || !size) 1047 return -1; 1048 1049 stm32_clock_enable(hi2c->clock); 1050 1051 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1052 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1053 goto bail; 1054 1055 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1056 hi2c->i2c_err = I2C_ERROR_NONE; 1057 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1058 1059 if (request->mode == I2C_MODE_MEM) { 1060 /* In memory mode, send slave address and memory address */ 1061 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1062 goto bail; 1063 1064 if (xfer_count > MAX_NBYTE_SIZE) { 1065 xfer_size = MAX_NBYTE_SIZE; 1066 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1067 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1068 } else { 1069 xfer_size = xfer_count; 1070 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1071 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1072 } 1073 } else { 1074 /* In master mode, send slave address */ 1075 if (xfer_count > MAX_NBYTE_SIZE) { 1076 xfer_size = MAX_NBYTE_SIZE; 1077 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1078 I2C_RELOAD_MODE, 1079 I2C_GENERATE_START_WRITE); 1080 } else { 1081 xfer_size = xfer_count; 1082 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1083 I2C_AUTOEND_MODE, 1084 I2C_GENERATE_START_WRITE); 1085 } 1086 } 1087 1088 do { 1089 if (i2c_wait_txis(hi2c, timeout_ref)) 1090 goto bail; 1091 1092 io_write8(base + I2C_TXDR, *p_buff); 1093 p_buff++; 1094 xfer_count--; 1095 xfer_size--; 1096 1097 if (xfer_count && !xfer_size) { 1098 /* Wait until TCR flag is set */ 1099 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1100 goto bail; 1101 1102 if (xfer_count > MAX_NBYTE_SIZE) { 1103 xfer_size = MAX_NBYTE_SIZE; 1104 i2c_transfer_config(hi2c, request->dev_addr, 1105 xfer_size, 1106 I2C_RELOAD_MODE, 1107 I2C_NO_STARTSTOP); 1108 } else { 1109 xfer_size = xfer_count; 1110 i2c_transfer_config(hi2c, request->dev_addr, 1111 xfer_size, 1112 I2C_AUTOEND_MODE, 1113 I2C_NO_STARTSTOP); 1114 } 1115 } 1116 1117 } while (xfer_count > 0U); 1118 1119 /* 1120 * No need to Check TC flag, with AUTOEND mode the stop 1121 * is automatically generated. 1122 * Wait until STOPF flag is reset. 1123 */ 1124 if (i2c_wait_stop(hi2c, timeout_ref)) 1125 goto bail; 1126 1127 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1128 1129 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1130 1131 hi2c->i2c_state = I2C_STATE_READY; 1132 1133 rc = 0; 1134 1135 bail: 1136 stm32_clock_disable(hi2c->clock); 1137 1138 return rc; 1139 } 1140 1141 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1142 uint32_t mem_addr, uint32_t mem_addr_size, 1143 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1144 { 1145 struct i2c_request request = { 1146 .dev_addr = dev_addr, 1147 .mode = I2C_MODE_MEM, 1148 .mem_addr = mem_addr, 1149 .mem_addr_size = mem_addr_size, 1150 .timeout_ms = timeout_ms, 1151 }; 1152 1153 return i2c_write(hi2c, &request, p_data, size); 1154 } 1155 1156 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1157 uint8_t *p_data, size_t size, 1158 unsigned int timeout_ms) 1159 { 1160 struct i2c_request request = { 1161 .dev_addr = dev_addr, 1162 .mode = I2C_MODE_MASTER, 1163 .timeout_ms = timeout_ms, 1164 }; 1165 1166 return i2c_write(hi2c, &request, p_data, size); 1167 } 1168 1169 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 1170 unsigned int mem_addr, uint8_t *p_data, 1171 bool write) 1172 { 1173 uint64_t timeout_ref = 0; 1174 uintptr_t base = get_base(hi2c); 1175 int rc = -1; 1176 uint8_t *p_buff = p_data; 1177 uint32_t event_mask = 0; 1178 1179 if (hi2c->i2c_state != I2C_STATE_READY || !p_data) 1180 return -1; 1181 1182 stm32_clock_enable(hi2c->clock); 1183 1184 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1185 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1186 goto bail; 1187 1188 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX; 1189 hi2c->i2c_err = I2C_ERROR_NONE; 1190 1191 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1192 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE, 1193 I2C_GENERATE_START_WRITE); 1194 1195 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1196 if (i2c_wait_txis(hi2c, timeout_ref)) 1197 goto bail; 1198 1199 io_write8(base + I2C_TXDR, mem_addr); 1200 1201 if (write) 1202 event_mask = I2C_ISR_TCR; 1203 else 1204 event_mask = I2C_ISR_TC; 1205 1206 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1207 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref)) 1208 goto bail; 1209 1210 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1211 I2C_AUTOEND_MODE, 1212 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ); 1213 1214 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1215 if (write) { 1216 if (i2c_wait_txis(hi2c, timeout_ref)) 1217 goto bail; 1218 1219 io_write8(base + I2C_TXDR, *p_buff); 1220 } else { 1221 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1222 goto bail; 1223 1224 *p_buff = io_read8(base + I2C_RXDR); 1225 } 1226 1227 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1228 if (i2c_wait_stop(hi2c, timeout_ref)) 1229 goto bail; 1230 1231 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1232 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1233 1234 hi2c->i2c_state = I2C_STATE_READY; 1235 1236 rc = 0; 1237 1238 bail: 1239 stm32_clock_disable(hi2c->clock); 1240 1241 return rc; 1242 } 1243 1244 /* 1245 * Read an amount of data in blocking mode 1246 * 1247 * @hi2c: Reference to struct i2c_handle_s 1248 * @request: I2C request parameters 1249 * @p_data: Pointer to data buffer 1250 * @size: Amount of data to be sent 1251 * Return 0 on success or a negative value 1252 */ 1253 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1254 uint8_t *p_data, uint32_t size) 1255 { 1256 vaddr_t base = get_base(hi2c); 1257 uint64_t timeout_ref = 0; 1258 int rc = -1; 1259 uint8_t *p_buff = p_data; 1260 size_t xfer_count = size; 1261 size_t xfer_size = 0; 1262 1263 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1264 return -1; 1265 1266 if (hi2c->i2c_state != I2C_STATE_READY) 1267 return -1; 1268 1269 if (!p_data || !size) 1270 return -1; 1271 1272 stm32_clock_enable(hi2c->clock); 1273 1274 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1275 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1276 goto bail; 1277 1278 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1279 hi2c->i2c_err = I2C_ERROR_NONE; 1280 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1281 1282 if (request->mode == I2C_MODE_MEM) { 1283 /* Send memory address */ 1284 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1285 goto bail; 1286 } 1287 1288 /* 1289 * Send slave address. 1290 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1291 * and generate RESTART. 1292 */ 1293 if (xfer_count > MAX_NBYTE_SIZE) { 1294 xfer_size = MAX_NBYTE_SIZE; 1295 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1296 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1297 } else { 1298 xfer_size = xfer_count; 1299 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1300 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1301 } 1302 1303 do { 1304 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1305 goto bail; 1306 1307 *p_buff = io_read8(base + I2C_RXDR); 1308 p_buff++; 1309 xfer_size--; 1310 xfer_count--; 1311 1312 if (xfer_count && !xfer_size) { 1313 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1314 goto bail; 1315 1316 if (xfer_count > MAX_NBYTE_SIZE) { 1317 xfer_size = MAX_NBYTE_SIZE; 1318 i2c_transfer_config(hi2c, request->dev_addr, 1319 xfer_size, 1320 I2C_RELOAD_MODE, 1321 I2C_NO_STARTSTOP); 1322 } else { 1323 xfer_size = xfer_count; 1324 i2c_transfer_config(hi2c, request->dev_addr, 1325 xfer_size, 1326 I2C_AUTOEND_MODE, 1327 I2C_NO_STARTSTOP); 1328 } 1329 } 1330 } while (xfer_count > 0U); 1331 1332 /* 1333 * No need to Check TC flag, with AUTOEND mode the stop 1334 * is automatically generated. 1335 * Wait until STOPF flag is reset. 1336 */ 1337 if (i2c_wait_stop(hi2c, timeout_ref)) 1338 goto bail; 1339 1340 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1341 1342 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1343 1344 hi2c->i2c_state = I2C_STATE_READY; 1345 1346 rc = 0; 1347 1348 bail: 1349 stm32_clock_disable(hi2c->clock); 1350 1351 return rc; 1352 } 1353 1354 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1355 uint32_t mem_addr, uint32_t mem_addr_size, 1356 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1357 { 1358 struct i2c_request request = { 1359 .dev_addr = dev_addr, 1360 .mode = I2C_MODE_MEM, 1361 .mem_addr = mem_addr, 1362 .mem_addr_size = mem_addr_size, 1363 .timeout_ms = timeout_ms, 1364 }; 1365 1366 return i2c_read(hi2c, &request, p_data, size); 1367 } 1368 1369 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1370 uint8_t *p_data, size_t size, 1371 unsigned int timeout_ms) 1372 { 1373 struct i2c_request request = { 1374 .dev_addr = dev_addr, 1375 .mode = I2C_MODE_MASTER, 1376 .timeout_ms = timeout_ms, 1377 }; 1378 1379 return i2c_read(hi2c, &request, p_data, size); 1380 } 1381 1382 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1383 unsigned int trials, unsigned int timeout_ms) 1384 { 1385 vaddr_t base = get_base(hi2c); 1386 unsigned int i2c_trials = 0U; 1387 bool rc = false; 1388 1389 if (hi2c->i2c_state != I2C_STATE_READY) 1390 return rc; 1391 1392 stm32_clock_enable(hi2c->clock); 1393 1394 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1395 goto bail; 1396 1397 hi2c->i2c_state = I2C_STATE_BUSY; 1398 hi2c->i2c_err = I2C_ERROR_NONE; 1399 1400 do { 1401 uint64_t timeout_ref = 0; 1402 vaddr_t isr = base + I2C_ISR; 1403 1404 /* Generate Start */ 1405 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1406 io_write32(base + I2C_CR2, 1407 ((dev_addr & I2C_CR2_SADD) | 1408 I2C_CR2_START | I2C_CR2_AUTOEND) & 1409 ~I2C_CR2_RD_WRN); 1410 else 1411 io_write32(base + I2C_CR2, 1412 ((dev_addr & I2C_CR2_SADD) | 1413 I2C_CR2_START | I2C_CR2_ADD10) & 1414 ~I2C_CR2_RD_WRN); 1415 1416 /* 1417 * No need to Check TC flag, with AUTOEND mode the stop 1418 * is automatically generated. 1419 * Wait until STOPF flag is set or a NACK flag is set. 1420 */ 1421 timeout_ref = timeout_init_us(timeout_ms * 1000); 1422 while (!timeout_elapsed(timeout_ref)) 1423 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1424 break; 1425 1426 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1427 notif_i2c_timeout(hi2c); 1428 goto bail; 1429 } 1430 1431 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1432 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1433 goto bail; 1434 1435 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1436 1437 hi2c->i2c_state = I2C_STATE_READY; 1438 1439 rc = true; 1440 goto bail; 1441 } 1442 1443 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1444 goto bail; 1445 1446 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1447 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1448 1449 if (i2c_trials == trials) { 1450 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1451 1452 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1453 goto bail; 1454 1455 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1456 } 1457 1458 i2c_trials++; 1459 } while (i2c_trials < trials); 1460 1461 notif_i2c_timeout(hi2c); 1462 1463 bail: 1464 stm32_clock_disable(hi2c->clock); 1465 1466 return rc; 1467 } 1468 1469 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1470 { 1471 if (hi2c->i2c_state == I2C_STATE_READY) 1472 return; 1473 1474 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1475 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1476 panic(); 1477 1478 stm32_pinctrl_load_active_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1479 1480 if (hi2c->i2c_state == I2C_STATE_RESET) { 1481 /* There is no valid I2C configuration to be loaded yet */ 1482 return; 1483 } 1484 1485 restore_cfg(hi2c, &hi2c->sec_cfg); 1486 1487 hi2c->i2c_state = I2C_STATE_READY; 1488 } 1489 1490 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1491 { 1492 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1493 return; 1494 1495 if (hi2c->i2c_state != I2C_STATE_READY) 1496 panic(); 1497 1498 save_cfg(hi2c, &hi2c->sec_cfg); 1499 stm32_pinctrl_load_standby_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1500 1501 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1502 } 1503