1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2022-2024, STMicroelectronics 4 */ 5 6 #include <arm.h> 7 #include <config.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/stm32_gpio.h> 11 #include <drivers/stm32_rif.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/delay.h> 15 #include <kernel/dt.h> 16 #include <kernel/dt_driver.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 #include <stdbool.h> 22 #include <stdlib.h> 23 #include <stm32_util.h> 24 #include <trace.h> 25 26 #define _HPDMA_SECCFGR U(0x000) 27 #define _HPDMA_PRIVCFGR U(0x004) 28 #define _HPDMA_RCFGLOCKR U(0x008) 29 #define _HPDMA_CIDCFGR(x) (U(0x054) + U(0x080) * (x)) 30 #define _HPDMA_SEMCR(x) (U(0x058) + U(0x080) * (x)) 31 32 /* 33 * CFGR register bitfields 34 */ 35 #define _HPDMA_CFGR_ENABLE BIT(31) 36 37 /* 38 * CIDCFGR register bitfields 39 */ 40 #define _HPDMA_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 41 #define _HPDMA_CIDCFGR_SCID_MASK GENMASK_32(5, 4) 42 #define _HPDMA_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 43 _CIDCFGR_SEMEN | \ 44 _HPDMA_CIDCFGR_SCID_MASK |\ 45 _HPDMA_CIDCFGR_SEMWL_MASK) 46 47 /* 48 * PRIVCFGR register bitfields 49 */ 50 #define _HPDMA_PRIVCFGR_MASK GENMASK_32(15, 0) 51 52 /* 53 * RCFGLOCKR register bitfields 54 */ 55 #define _HPDMA_RCFGLOCKR_MASK GENMASK_32(15, 0) 56 57 /* 58 * SECCFGR register bitfields 59 */ 60 #define _HPDMA_SECCFGR_EN BIT(0) 61 #define _HPDMA_SECCFGR_MASK GENMASK_32(15, 0) 62 63 /* 64 * SEMCR register bitfields 65 */ 66 #define _HPDMA_SEMCR_SCID_MASK GENMASK_32(5, 4) 67 #define _HPDMA_SEMCR_SCID_SHIFT U(4) 68 69 /* 70 * Miscellaneous 71 */ 72 73 #define HPDMA_RIF_CHANNELS U(16) 74 75 #define HPDMA_NB_MAX_CID_SUPPORTED U(3) 76 77 struct hpdma_pdata { 78 struct clk *hpdma_clock; 79 struct rif_conf_data conf_data; 80 unsigned int nb_channels; 81 vaddr_t base; 82 83 SLIST_ENTRY(hpdma_pdata) link; 84 }; 85 86 static SLIST_HEAD(, hpdma_pdata) hpdma_list = 87 SLIST_HEAD_INITIALIZER(hpdma_list); 88 89 /* This function expects HPDMA bus clock is enabled */ 90 static TEE_Result apply_rif_config(struct hpdma_pdata *hpdma_d, bool is_tdcid) 91 { 92 TEE_Result res = TEE_ERROR_ACCESS_DENIED; 93 uint32_t cidcfgr = 0; 94 unsigned int i = 0; 95 96 for (i = 0; i < HPDMA_RIF_CHANNELS; i++) { 97 if (!(BIT(i) & hpdma_d->conf_data.access_mask[0])) 98 continue; 99 /* 100 * When TDCID, OP-TEE should be the one to set the CID filtering 101 * configuration. Clearing previous configuration prevents 102 * undesired events during the only legitimate configuration. 103 */ 104 if (is_tdcid) 105 io_clrbits32(hpdma_d->base + _HPDMA_CIDCFGR(i), 106 _HPDMA_CIDCFGR_CONF_MASK); 107 108 cidcfgr = io_read32(hpdma_d->base + _HPDMA_CIDCFGR(i)); 109 110 /* Check if the channel is in semaphore mode */ 111 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 112 continue; 113 114 /* If not TDCID, we want to acquire semaphores assigned to us */ 115 res = stm32_rif_acquire_semaphore(hpdma_d->base + 116 _HPDMA_SEMCR(i), 117 HPDMA_NB_MAX_CID_SUPPORTED); 118 if (res) { 119 EMSG("Couldn't acquire semaphore for channel %u", i); 120 return res; 121 } 122 } 123 124 /* Security and privilege RIF configuration */ 125 io_clrsetbits32(hpdma_d->base + _HPDMA_PRIVCFGR, _HPDMA_PRIVCFGR_MASK & 126 hpdma_d->conf_data.access_mask[0], 127 hpdma_d->conf_data.priv_conf[0]); 128 io_clrsetbits32(hpdma_d->base + _HPDMA_SECCFGR, _HPDMA_SECCFGR_MASK & 129 hpdma_d->conf_data.access_mask[0], 130 hpdma_d->conf_data.sec_conf[0]); 131 132 /* Skip CID/semaphore configuration if not in TDCID state. */ 133 if (!is_tdcid) 134 goto end; 135 136 for (i = 0; i < HPDMA_RIF_CHANNELS; i++) { 137 if (!(BIT(i) & hpdma_d->conf_data.access_mask[0])) 138 continue; 139 140 io_clrsetbits32(hpdma_d->base + _HPDMA_CIDCFGR(i), 141 _HPDMA_CIDCFGR_CONF_MASK, 142 hpdma_d->conf_data.cid_confs[i]); 143 144 cidcfgr = io_read32(hpdma_d->base + _HPDMA_CIDCFGR(i)); 145 146 /* 147 * Take semaphore if the resource is in semaphore 148 * mode and secured. 149 */ 150 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) || 151 !(io_read32(hpdma_d->base + _HPDMA_SECCFGR) & BIT(i))) { 152 res = 153 stm32_rif_release_semaphore(hpdma_d->base + 154 _HPDMA_SEMCR(i), 155 HPDMA_NB_MAX_CID_SUPPORTED); 156 if (res) { 157 EMSG("Couldn't release semaphore for res%u", i); 158 return TEE_ERROR_ACCESS_DENIED; 159 } 160 } else { 161 res = 162 stm32_rif_acquire_semaphore(hpdma_d->base + 163 _HPDMA_SEMCR(i), 164 HPDMA_NB_MAX_CID_SUPPORTED); 165 if (res) { 166 EMSG("Couldn't acquire semaphore for res%u", i); 167 return TEE_ERROR_ACCESS_DENIED; 168 } 169 } 170 } 171 172 /* 173 * Lock RIF configuration if configured. This cannot be undone until 174 * next reset. 175 */ 176 io_clrsetbits32(hpdma_d->base + _HPDMA_RCFGLOCKR, _HPDMA_RCFGLOCKR_MASK, 177 hpdma_d->conf_data.lock_conf[0]); 178 179 end: 180 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 181 /* Check that RIF config are applied, panic otherwise */ 182 if ((io_read32(hpdma_d->base + _HPDMA_PRIVCFGR) & 183 hpdma_d->conf_data.access_mask[0]) != 184 hpdma_d->conf_data.priv_conf[0]) 185 panic("HPDMA channel priv conf is incorrect"); 186 187 if ((io_read32(hpdma_d->base + _HPDMA_SECCFGR) & 188 hpdma_d->conf_data.access_mask[0]) != 189 hpdma_d->conf_data.sec_conf[0]) 190 panic("HPDMA channel sec conf is incorrect"); 191 } 192 193 return TEE_SUCCESS; 194 } 195 196 static TEE_Result parse_dt(const void *fdt, int node, 197 struct hpdma_pdata *hpdma_d) 198 { 199 TEE_Result res = TEE_ERROR_GENERIC; 200 unsigned int i = 0; 201 int lenp = 0; 202 const fdt32_t *cuint = NULL; 203 struct dt_node_info info = { }; 204 struct io_pa_va addr = { }; 205 206 fdt_fill_device_info(fdt, &info, node); 207 assert(info.reg != DT_INFO_INVALID_REG && 208 info.reg_size != DT_INFO_INVALID_REG_SIZE); 209 210 addr.pa = info.reg; 211 hpdma_d->base = io_pa_or_va_secure(&addr, info.reg_size); 212 213 /* Gate the IP */ 214 res = clk_dt_get_by_index(fdt, node, 0, &hpdma_d->hpdma_clock); 215 if (res) 216 return res; 217 218 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 219 if (!cuint) 220 panic("No RIF configuration available"); 221 222 hpdma_d->nb_channels = (unsigned int)(lenp / sizeof(uint32_t)); 223 assert(hpdma_d->nb_channels <= HPDMA_RIF_CHANNELS); 224 225 hpdma_d->conf_data.cid_confs = calloc(HPDMA_RIF_CHANNELS, 226 sizeof(uint32_t)); 227 hpdma_d->conf_data.sec_conf = calloc(1, sizeof(uint32_t)); 228 hpdma_d->conf_data.priv_conf = calloc(1, sizeof(uint32_t)); 229 hpdma_d->conf_data.access_mask = calloc(1, sizeof(uint32_t)); 230 hpdma_d->conf_data.lock_conf = calloc(1, sizeof(uint32_t)); 231 assert(hpdma_d->conf_data.cid_confs && hpdma_d->conf_data.sec_conf && 232 hpdma_d->conf_data.priv_conf && hpdma_d->conf_data.access_mask && 233 hpdma_d->conf_data.lock_conf); 234 235 for (i = 0; i < hpdma_d->nb_channels; i++) 236 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), &hpdma_d->conf_data, 237 HPDMA_NB_MAX_CID_SUPPORTED, 238 HPDMA_RIF_CHANNELS); 239 240 return TEE_SUCCESS; 241 } 242 243 static void stm32_hpdma_pm_resume(struct hpdma_pdata *hpdma) 244 { 245 if (apply_rif_config(hpdma, true)) 246 panic("Failed to resume HPDMA"); 247 } 248 249 static void stm32_hpdma_pm_suspend(struct hpdma_pdata *hpdma) 250 { 251 size_t i = 0; 252 253 for (i = 0; i < HPDMA_RIF_CHANNELS; i++) 254 hpdma->conf_data.cid_confs[i] = io_read32(hpdma->base + 255 _HPDMA_CIDCFGR(i)) & 256 _HPDMA_CIDCFGR_CONF_MASK; 257 258 hpdma->conf_data.priv_conf[0] = io_read32(hpdma->base + 259 _HPDMA_PRIVCFGR) & 260 _HPDMA_PRIVCFGR_MASK; 261 hpdma->conf_data.sec_conf[0] = io_read32(hpdma->base + 262 _HPDMA_SECCFGR) & 263 _HPDMA_SECCFGR_MASK; 264 hpdma->conf_data.lock_conf[0] = io_read32(hpdma->base + 265 _HPDMA_RCFGLOCKR) & 266 _HPDMA_RCFGLOCKR_MASK; 267 268 /* 269 * The access mask is modified to restore the conf for all 270 * resources. 271 */ 272 hpdma->conf_data.access_mask[0] = GENMASK_32(HPDMA_RIF_CHANNELS - 1, 0); 273 } 274 275 static TEE_Result 276 stm32_hpdma_pm(enum pm_op op, unsigned int pm_hint, 277 const struct pm_callback_handle *pm_handle) 278 { 279 struct hpdma_pdata *hpdma = pm_handle->handle; 280 TEE_Result res = TEE_ERROR_GENERIC; 281 bool is_tdcid = false; 282 283 res = stm32_rifsc_check_tdcid(&is_tdcid); 284 if (res) 285 panic(); 286 287 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT) || !is_tdcid) 288 return TEE_SUCCESS; 289 290 res = clk_enable(hpdma->hpdma_clock); 291 if (res) 292 return res; 293 294 if (op == PM_OP_RESUME) 295 stm32_hpdma_pm_resume(hpdma); 296 else 297 stm32_hpdma_pm_suspend(hpdma); 298 299 clk_disable(hpdma->hpdma_clock); 300 301 return TEE_SUCCESS; 302 } 303 304 static TEE_Result stm32_hpdma_probe(const void *fdt, int node, 305 const void *compat_data __unused) 306 { 307 TEE_Result res = TEE_ERROR_GENERIC; 308 struct hpdma_pdata *hpdma_d = NULL; 309 bool is_tdcid = false; 310 311 res = stm32_rifsc_check_tdcid(&is_tdcid); 312 if (res) 313 return res; 314 315 hpdma_d = calloc(1, sizeof(*hpdma_d)); 316 if (!hpdma_d) 317 return TEE_ERROR_OUT_OF_MEMORY; 318 319 res = parse_dt(fdt, node, hpdma_d); 320 if (res) { 321 free(hpdma_d); 322 return res; 323 } 324 325 if (clk_enable(hpdma_d->hpdma_clock)) 326 panic("Cannot access hpdma clock"); 327 328 res = apply_rif_config(hpdma_d, is_tdcid); 329 if (res) 330 panic("Failed to apply RIF config"); 331 332 clk_disable(hpdma_d->hpdma_clock); 333 334 SLIST_INSERT_HEAD(&hpdma_list, hpdma_d, link); 335 336 register_pm_core_service_cb(stm32_hpdma_pm, hpdma_d, "stm32-hpdma"); 337 338 return TEE_SUCCESS; 339 } 340 341 static const struct dt_device_match stm32_hpdma_match_table[] = { 342 { .compatible = "st,stm32-dma3" }, 343 { } 344 }; 345 346 DEFINE_DT_DRIVER(stm32_hpdma_dt_driver) = { 347 .name = "st,stm32-hpdma", 348 .match_table = stm32_hpdma_match_table, 349 .probe = stm32_hpdma_probe, 350 }; 351