1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <drivers/gpio.h> 12 #include <drivers/stm32_gpio.h> 13 #include <io.h> 14 #include <kernel/dt.h> 15 #include <kernel/boot.h> 16 #include <kernel/panic.h> 17 #include <kernel/spinlock.h> 18 #include <libfdt.h> 19 #include <mm/core_memprot.h> 20 #include <stdbool.h> 21 #include <stm32_util.h> 22 #include <sys/queue.h> 23 #include <trace.h> 24 #include <util.h> 25 26 #ifndef CFG_DRIVERS_GPIO 27 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 28 #endif 29 30 #define GPIO_PIN_MAX 15 31 32 #define GPIO_MODER_OFFSET 0x00 33 #define GPIO_OTYPER_OFFSET 0x04 34 #define GPIO_OSPEEDR_OFFSET 0x08 35 #define GPIO_PUPDR_OFFSET 0x0c 36 #define GPIO_IDR_OFFSET 0x10 37 #define GPIO_ODR_OFFSET 0x14 38 #define GPIO_BSRR_OFFSET 0x18 39 #define GPIO_AFRL_OFFSET 0x20 40 #define GPIO_AFRH_OFFSET 0x24 41 #define GPIO_SECR_OFFSET 0x30 42 43 #define GPIO_ALT_LOWER_LIMIT 0x8 44 45 #define GPIO_MODE_MASK GENMASK_32(1, 0) 46 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 47 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 48 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 49 50 #define DT_GPIO_BANK_SHIFT 12 51 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 52 #define DT_GPIO_PIN_SHIFT 8 53 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 54 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 55 56 #define DT_GPIO_BANK_NAME0 "GPIOA" 57 58 /** 59 * struct stm32_gpio_bank - GPIO bank instance 60 * 61 * @base: base address of the GPIO controller registers. 62 * @clock: clock identifier. 63 * @gpio_chip: GPIO chip reference for that GPIO bank 64 * @ngpios: number of GPIOs. 65 * @bank_id: Id of the bank. 66 * @lock: lock protecting the GPIO bank access. 67 * @sec_support: True if bank supports pin security protection, otherwise false 68 * @seccfgr: Secure configuration register value. 69 * @link: Link in bank list 70 */ 71 struct stm32_gpio_bank { 72 vaddr_t base; 73 struct clk *clock; 74 struct gpio_chip gpio_chip; 75 unsigned int ngpios; 76 unsigned int bank_id; 77 unsigned int lock; 78 STAILQ_ENTRY(stm32_gpio_bank) link; 79 }; 80 81 static unsigned int gpio_lock; 82 83 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 84 STAILQ_HEAD_INITIALIZER(bank_list); 85 86 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 87 88 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 89 { 90 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 91 } 92 93 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 94 unsigned int gpio_pin) 95 { 96 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 97 enum gpio_level level = GPIO_LEVEL_HIGH; 98 unsigned int reg_offset = 0; 99 unsigned int mode = 0; 100 101 assert(gpio_pin < bank->ngpios); 102 103 if (clk_enable(bank->clock)) 104 panic(); 105 106 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 107 GPIO_MODE_MASK; 108 109 switch (mode) { 110 case GPIO_MODE_INPUT: 111 reg_offset = GPIO_IDR_OFFSET; 112 break; 113 case GPIO_MODE_OUTPUT: 114 reg_offset = GPIO_ODR_OFFSET; 115 break; 116 default: 117 panic(); 118 } 119 120 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 121 level = GPIO_LEVEL_HIGH; 122 else 123 level = GPIO_LEVEL_LOW; 124 125 clk_disable(bank->clock); 126 127 return level; 128 } 129 130 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 131 enum gpio_level level) 132 { 133 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 134 135 assert(gpio_pin < bank->ngpios); 136 137 if (clk_enable(bank->clock)) 138 panic(); 139 140 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 141 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 142 143 if (level == GPIO_LEVEL_HIGH) 144 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 145 else 146 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 147 148 clk_disable(bank->clock); 149 } 150 151 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 152 unsigned int gpio_pin) 153 { 154 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 155 uint32_t mode = 0; 156 157 assert(gpio_pin < bank->ngpios); 158 159 if (clk_enable(bank->clock)) 160 panic(); 161 162 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 163 GPIO_MODE_MASK; 164 165 clk_disable(bank->clock); 166 167 switch (mode) { 168 case GPIO_MODE_INPUT: 169 return GPIO_DIR_IN; 170 case GPIO_MODE_OUTPUT: 171 return GPIO_DIR_OUT; 172 default: 173 panic(); 174 } 175 } 176 177 static void stm32_gpio_set_direction(struct gpio_chip *chip, 178 unsigned int gpio_pin, 179 enum gpio_dir direction) 180 { 181 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 182 uint32_t exceptions = 0; 183 uint32_t mode = 0; 184 185 assert(gpio_pin < bank->ngpios); 186 187 if (direction == GPIO_DIR_IN) 188 mode = GPIO_MODE_INPUT; 189 else 190 mode = GPIO_MODE_OUTPUT; 191 192 if (clk_enable(bank->clock)) 193 panic(); 194 exceptions = cpu_spin_lock_xsave(&gpio_lock); 195 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 196 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 197 SHIFT_U32(mode, gpio_pin << 1)); 198 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 199 clk_disable(bank->clock); 200 } 201 202 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 203 struct gpio *gpio) 204 { 205 assert(is_stm32_gpio_chip(chip)); 206 free(gpio); 207 } 208 209 static const struct gpio_ops stm32_gpio_ops = { 210 .get_direction = stm32_gpio_get_direction, 211 .set_direction = stm32_gpio_set_direction, 212 .get_value = stm32_gpio_get_level, 213 .set_value = stm32_gpio_set_level, 214 .put = stm32_gpio_put_gpio, 215 }; 216 217 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 218 { 219 return chip && chip->ops == &stm32_gpio_ops; 220 } 221 222 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 223 { 224 struct stm32_gpio_bank *bank = NULL; 225 226 STAILQ_FOREACH(bank, &bank_list, link) 227 if (bank_id == bank->bank_id) 228 return bank; 229 230 panic(); 231 } 232 233 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 234 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 235 { 236 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 237 238 if (clk_enable(bank->clock)) 239 panic(); 240 241 /* 242 * Save GPIO configuration bits spread over the few bank registers. 243 * 1bit fields are accessed at bit position being the pin index. 244 * 2bit fields are accessed at bit position being twice the pin index. 245 * 4bit fields are accessed at bit position being fourth the pin index 246 * but accessed from 2 32bit registers at incremental addresses. 247 */ 248 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 249 GPIO_MODE_MASK; 250 251 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 252 253 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 254 (pin << 1)) & GPIO_OSPEED_MASK; 255 256 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 257 GPIO_PUPD_PULL_MASK; 258 259 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 260 261 if (pin < GPIO_ALT_LOWER_LIMIT) 262 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 263 (pin << 2)) & GPIO_ALTERNATE_MASK; 264 else 265 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 266 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 267 GPIO_ALTERNATE_MASK; 268 269 clk_disable(bank->clock); 270 } 271 272 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 273 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 274 { 275 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 276 uint32_t exceptions = 0; 277 278 if (clk_enable(bank->clock)) 279 panic(); 280 exceptions = cpu_spin_lock_xsave(&gpio_lock); 281 282 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 283 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 284 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 285 SHIFT_U32(cfg->mode, pin << 1)); 286 287 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 288 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 289 SHIFT_U32(cfg->otype, pin)); 290 291 /* Load GPIO Output Speed confguration, 2bit value */ 292 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 293 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 294 SHIFT_U32(cfg->ospeed, pin << 1)); 295 296 /* Load GPIO pull configuration, 2bit value */ 297 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 298 SHIFT_U32(cfg->pupd, pin << 1)); 299 300 /* Load pin mux Alternate Function configuration, 4bit value */ 301 if (pin < GPIO_ALT_LOWER_LIMIT) { 302 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 303 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 304 SHIFT_U32(cfg->af, pin << 2)); 305 } else { 306 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 307 308 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 309 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 310 SHIFT_U32(cfg->af, shift)); 311 } 312 313 /* Load GPIO Output direction confuguration, 1bit */ 314 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 315 316 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 317 clk_disable(bank->clock); 318 } 319 320 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 321 { 322 size_t n = 0; 323 324 for (n = 0; n < cnt; n++) 325 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 326 &pinctrl[n].active_cfg); 327 } 328 329 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 330 { 331 size_t n = 0; 332 333 for (n = 0; n < cnt; n++) 334 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 335 &pinctrl[n].standby_cfg); 336 } 337 338 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 339 { 340 size_t n = 0; 341 342 for (n = 0; n < cnt; n++) 343 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 344 &pinctrl[n].standby_cfg); 345 } 346 347 /* Panic if GPIO bank information from platform do not match DTB description */ 348 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 349 { 350 int pinctrl_subnode = 0; 351 352 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 353 const fdt32_t *cuint = NULL; 354 355 if (fdt_getprop(fdt, pinctrl_subnode, 356 "gpio-controller", NULL) == NULL) 357 continue; 358 359 /* Check bank register offset matches platform assumptions */ 360 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 361 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 362 continue; 363 364 /* Check controller is enabled */ 365 if (fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 366 panic(); 367 368 return; 369 } 370 371 panic(); 372 } 373 374 /* Count pins described in the DT node and get related data if possible */ 375 static int get_pinctrl_from_fdt(void *fdt, int node, 376 struct stm32_pinctrl *pinctrl, size_t count) 377 { 378 const fdt32_t *cuint, *slewrate; 379 int len = 0; 380 int pinctrl_node = 0; 381 uint32_t i = 0; 382 uint32_t speed = GPIO_OSPEED_LOW; 383 uint32_t pull = GPIO_PUPD_NO_PULL; 384 size_t found = 0; 385 386 cuint = fdt_getprop(fdt, node, "pinmux", &len); 387 if (!cuint) 388 return -FDT_ERR_NOTFOUND; 389 390 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 391 if (pinctrl_node < 0) 392 return -FDT_ERR_NOTFOUND; 393 394 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 395 if (slewrate) 396 speed = fdt32_to_cpu(*slewrate); 397 398 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 399 pull = GPIO_PUPD_PULL_UP; 400 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 401 pull = GPIO_PUPD_PULL_DOWN; 402 403 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 404 uint32_t pincfg = 0; 405 uint32_t bank = 0; 406 uint32_t pin = 0; 407 uint32_t mode = 0; 408 uint32_t alternate = 0; 409 uint32_t odata = 0; 410 bool opendrain = false; 411 412 pincfg = fdt32_to_cpu(*cuint); 413 cuint++; 414 415 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 416 417 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 418 419 mode = pincfg & DT_GPIO_MODE_MASK; 420 421 switch (mode) { 422 case 0: 423 mode = GPIO_MODE_INPUT; 424 break; 425 case 1: 426 case 2: 427 case 3: 428 case 4: 429 case 5: 430 case 6: 431 case 7: 432 case 8: 433 case 9: 434 case 10: 435 case 11: 436 case 12: 437 case 13: 438 case 14: 439 case 15: 440 case 16: 441 alternate = mode - 1U; 442 mode = GPIO_MODE_ALTERNATE; 443 break; 444 case 17: 445 mode = GPIO_MODE_ANALOG; 446 break; 447 default: 448 mode = GPIO_MODE_OUTPUT; 449 break; 450 } 451 452 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 453 opendrain = true; 454 455 if (fdt_getprop(fdt, node, "output-high", NULL) && 456 mode == GPIO_MODE_INPUT) { 457 mode = GPIO_MODE_OUTPUT; 458 odata = 1; 459 } 460 461 if (fdt_getprop(fdt, node, "output-low", NULL) && 462 mode == GPIO_MODE_INPUT) { 463 mode = GPIO_MODE_OUTPUT; 464 odata = 0; 465 } 466 467 /* Check GPIO bank clock/base address against platform */ 468 ckeck_gpio_bank(fdt, bank, pinctrl_node); 469 470 if (found < count) { 471 struct stm32_pinctrl *ref = &pinctrl[found]; 472 473 ref->bank = (uint8_t)bank; 474 ref->pin = (uint8_t)pin; 475 ref->active_cfg.mode = mode; 476 ref->active_cfg.otype = opendrain ? 1 : 0; 477 ref->active_cfg.ospeed = speed; 478 ref->active_cfg.pupd = pull; 479 ref->active_cfg.od = odata; 480 ref->active_cfg.af = alternate; 481 /* Default to analog mode for standby state */ 482 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 483 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 484 } 485 486 found++; 487 } 488 489 return (int)found; 490 } 491 492 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 493 struct gpio **out_gpio) 494 { 495 TEE_Result res = TEE_ERROR_GENERIC; 496 struct stm32_gpio_bank *bank = data; 497 struct gpio *gpio = NULL; 498 unsigned int shift_1b = 0; 499 unsigned int shift_2b = 0; 500 uint32_t exceptions = 0; 501 uint32_t otype = 0; 502 uint32_t pupd = 0; 503 uint32_t mode = 0; 504 505 res = gpio_dt_alloc_pin(pargs, &gpio); 506 if (res) 507 return res; 508 509 if (gpio->pin >= bank->ngpios) { 510 DMSG("Invalid GPIO reference"); 511 free(gpio); 512 return TEE_ERROR_GENERIC; 513 } 514 515 shift_1b = gpio->pin; 516 shift_2b = SHIFT_U32(gpio->pin, 1); 517 518 if (gpio->dt_flags & GPIO_PULL_UP) 519 pupd = GPIO_PUPD_PULL_UP; 520 else if (gpio->dt_flags & GPIO_PULL_DOWN) 521 pupd = GPIO_PUPD_PULL_DOWN; 522 else 523 pupd = GPIO_PUPD_NO_PULL; 524 525 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 526 otype = GPIO_OTYPE_OPEN_DRAIN; 527 else 528 otype = GPIO_OTYPE_PUSH_PULL; 529 530 if (clk_enable(bank->clock)) 531 panic(); 532 exceptions = cpu_spin_lock_xsave(&gpio_lock); 533 534 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 535 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 536 SHIFT_U32(mode, shift_2b)); 537 538 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 539 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 540 SHIFT_U32(otype, shift_1b)); 541 542 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 543 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 544 SHIFT_U32(pupd, shift_2b)); 545 546 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 547 clk_disable(bank->clock); 548 549 gpio->chip = &bank->gpio_chip; 550 551 *out_gpio = gpio; 552 553 return TEE_SUCCESS; 554 } 555 556 /* Get bank ID from bank node property st,bank-name or panic on failure */ 557 static unsigned int dt_get_bank_id(const void *fdt, int node) 558 { 559 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 560 const fdt32_t *cuint = NULL; 561 int len = 0; 562 563 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 564 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 565 if (!cuint || (len != dt_name_len + 1)) 566 panic("Missing/wrong st,bank-name property"); 567 568 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 569 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 570 panic("Wrong st,bank-name property"); 571 572 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 573 } 574 575 /* 576 * Return whether or not the GPIO bank related to a DT node is already 577 * registered in the GPIO bank link. 578 */ 579 static bool bank_is_registered(const void *fdt, int node) 580 { 581 unsigned int bank_id = dt_get_bank_id(fdt, node); 582 struct stm32_gpio_bank *bank = NULL; 583 584 STAILQ_FOREACH(bank, &bank_list, link) 585 if (bank->bank_id == bank_id) 586 return true; 587 588 return false; 589 } 590 591 /* Get GPIO bank information from the DT */ 592 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 593 const void *compat_data __unused, 594 int range_offset, 595 struct stm32_gpio_bank **out_bank) 596 { 597 TEE_Result res = TEE_ERROR_GENERIC; 598 struct stm32_gpio_bank *bank = NULL; 599 const fdt32_t *cuint = NULL; 600 struct io_pa_va pa_va = { }; 601 struct clk *clk = NULL; 602 size_t blen = 0; 603 paddr_t pa = 0; 604 int len = 0; 605 int i = 0; 606 607 assert(out_bank); 608 609 /* Probe deferrable devices first */ 610 res = clk_dt_get_by_index(fdt, node, 0, &clk); 611 if (res) 612 return res; 613 614 bank = calloc(1, sizeof(*bank)); 615 if (!bank) 616 return TEE_ERROR_OUT_OF_MEMORY; 617 618 /* 619 * Do not rely *only* on the "reg" property to get the address, 620 * but consider also the "ranges" translation property 621 */ 622 pa = fdt_reg_base_address(fdt, node); 623 if (pa == DT_INFO_INVALID_REG) 624 panic("missing reg property"); 625 626 pa_va.pa = pa + range_offset; 627 628 blen = fdt_reg_size(fdt, node); 629 if (blen == DT_INFO_INVALID_REG_SIZE) 630 panic("missing reg size property"); 631 632 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 633 bank->base = io_pa_or_va_secure(&pa_va, blen); 634 bank->bank_id = dt_get_bank_id(fdt, node); 635 bank->clock = clk; 636 bank->gpio_chip.ops = &stm32_gpio_ops; 637 638 /* Parse gpio-ranges with its 4 parameters */ 639 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 640 len /= sizeof(*cuint); 641 if (len % 4) 642 panic("wrong gpio-ranges syntax"); 643 644 /* Get the last defined gpio line (offset + nb of pins) */ 645 for (i = 0; i < len / 4; i++) { 646 bank->ngpios = MAX(bank->ngpios, 647 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 648 fdt32_to_cpu(*(cuint + 3)))); 649 cuint += 4; 650 } 651 652 *out_bank = bank; 653 return TEE_SUCCESS; 654 } 655 656 static void set_bank_gpio_non_secure(struct stm32_gpio_bank *bank) 657 { 658 unsigned int pin = 0; 659 660 for (pin = 0; pin <= bank->ngpios; pin++) 661 stm32_gpio_set_secure_cfg(bank->bank_id, pin, false); 662 } 663 664 /* Parse a pinctrl node to register the GPIO banks it describes */ 665 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 666 const void *compat_data) 667 { 668 TEE_Result res = TEE_SUCCESS; 669 const fdt32_t *cuint = NULL; 670 int range_offs = 0; 671 int b_node = 0; 672 int len = 0; 673 674 /* Read the ranges property (for regs memory translation) */ 675 cuint = fdt_getprop(fdt, node, "ranges", &len); 676 if (!cuint) 677 panic("missing ranges property"); 678 679 len /= sizeof(*cuint); 680 if (len == 3) 681 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 682 683 fdt_for_each_subnode(b_node, fdt, node) { 684 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 685 if (cuint) { 686 /* 687 * We found a property "gpio-controller" in the node: 688 * the node is a GPIO bank description, add it to the 689 * bank list. 690 */ 691 struct stm32_gpio_bank *bank = NULL; 692 693 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 694 bank_is_registered(fdt, b_node)) 695 continue; 696 697 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 698 range_offs, &bank); 699 if (res) 700 return res; 701 702 /* Registering a provider should not defer probe */ 703 res = gpio_register_provider(fdt, b_node, 704 stm32_gpio_get_dt, bank); 705 if (res) 706 panic(); 707 708 STAILQ_INSERT_TAIL(&bank_list, bank, link); 709 710 if (IS_ENABLED(CFG_STM32MP13)) 711 set_bank_gpio_non_secure(bank); 712 } else { 713 if (len != -FDT_ERR_NOTFOUND) 714 panic(); 715 } 716 } 717 718 return TEE_SUCCESS; 719 } 720 721 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 722 struct stm32_pinctrl *pinctrl, size_t count) 723 { 724 const fdt32_t *cuint = NULL; 725 int lenp = 0; 726 int i = 0; 727 size_t found = 0; 728 729 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 730 if (!cuint) 731 return -FDT_ERR_NOTFOUND; 732 733 for (i = 0; i < (lenp / 4); i++) { 734 int node = 0; 735 int subnode = 0; 736 737 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 738 if (node < 0) 739 return -FDT_ERR_NOTFOUND; 740 741 fdt_for_each_subnode(subnode, fdt, node) { 742 size_t n = 0; 743 int rc = 0; 744 745 if (count > found) 746 n = count - found; 747 else 748 n = 0; 749 750 rc = get_pinctrl_from_fdt(fdt, subnode, 751 &pinctrl[found], n); 752 if (rc < 0) 753 return rc; 754 755 found += (size_t)rc; 756 } 757 758 cuint++; 759 } 760 761 return (int)found; 762 } 763 764 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 765 { 766 int node = 0; 767 const fdt32_t *cuint = NULL; 768 769 fdt_for_each_subnode(node, fdt, pinctrl_node) { 770 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 771 continue; 772 773 cuint = fdt_getprop(fdt, node, "reg", NULL); 774 if (!cuint) 775 continue; 776 777 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 778 continue; 779 780 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 781 if (!cuint) 782 panic(); 783 784 return (int)fdt32_to_cpu(*cuint); 785 } 786 787 return -1; 788 } 789 790 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 791 bool secure) 792 { 793 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 794 uint32_t exceptions = 0; 795 796 if (clk_enable(bank->clock)) 797 panic(); 798 exceptions = cpu_spin_lock_xsave(&gpio_lock); 799 800 if (secure) 801 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 802 else 803 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 804 805 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 806 clk_disable(bank->clock); 807 } 808 809 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 810 const void *compat_data) 811 { 812 /* Register GPIO banks described in this pin control node */ 813 return dt_stm32_gpio_pinctrl(fdt, node, compat_data); 814 } 815 816 static const struct dt_device_match stm32_pinctrl_match_table[] = { 817 { .compatible = "st,stm32mp135-pinctrl" }, 818 { .compatible = "st,stm32mp157-pinctrl" }, 819 { .compatible = "st,stm32mp157-z-pinctrl" }, 820 { } 821 }; 822 823 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 824 .name = "stm32_gpio-pinctrl", 825 .type = DT_DRIVER_PINCTRL, 826 .match_table = stm32_pinctrl_match_table, 827 .probe = stm32_pinctrl_probe, 828 }; 829