1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2020, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32_bsec.h> 9 #include <io.h> 10 #include <kernel/delay.h> 11 #include <kernel/dt.h> 12 #include <kernel/boot.h> 13 #include <kernel/spinlock.h> 14 #include <libfdt.h> 15 #include <limits.h> 16 #include <mm/core_memprot.h> 17 #include <platform_config.h> 18 #include <stm32_util.h> 19 #include <string.h> 20 #include <tee_api_defines.h> 21 #include <types_ext.h> 22 #include <util.h> 23 24 #define BSEC_OTP_MASK GENMASK_32(4, 0) 25 #define BSEC_OTP_BANK_SHIFT 5 26 27 /* Permanent lock bitmasks */ 28 #define ADDR_LOWER_OTP_PERLOCK_SHIFT 3 29 #define DATA_LOWER_OTP_PERLOCK_BIT 3 30 #define DATA_LOWER_OTP_PERLOCK_MASK GENMASK_32(2, 0) 31 #define ADDR_UPPER_OTP_PERLOCK_SHIFT 4 32 #define DATA_UPPER_OTP_PERLOCK_BIT 1 33 #define DATA_UPPER_OTP_PERLOCK_MASK GENMASK_32(3, 0) 34 35 /* BSEC register offset */ 36 #define BSEC_OTP_CONF_OFF 0x000U 37 #define BSEC_OTP_CTRL_OFF 0x004U 38 #define BSEC_OTP_WRDATA_OFF 0x008U 39 #define BSEC_OTP_STATUS_OFF 0x00CU 40 #define BSEC_OTP_LOCK_OFF 0x010U 41 #define BSEC_DEN_OFF 0x014U 42 #define BSEC_FEN_OFF 0x018U 43 #define BSEC_DISTURBED_OFF 0x01CU 44 #define BSEC_DISTURBED1_OFF 0x020U 45 #define BSEC_DISTURBED2_OFF 0x024U 46 #define BSEC_ERROR_OFF 0x034U 47 #define BSEC_ERROR1_OFF 0x038U 48 #define BSEC_ERROR2_OFF 0x03CU 49 #define BSEC_WRLOCK_OFF 0x04CU 50 #define BSEC_WRLOCK1_OFF 0x050U 51 #define BSEC_WRLOCK2_OFF 0x054U 52 #define BSEC_SPLOCK_OFF 0x064U 53 #define BSEC_SPLOCK1_OFF 0x068U 54 #define BSEC_SPLOCK2_OFF 0x06CU 55 #define BSEC_SWLOCK_OFF 0x07CU 56 #define BSEC_SWLOCK1_OFF 0x080U 57 #define BSEC_SWLOCK2_OFF 0x084U 58 #define BSEC_SRLOCK_OFF 0x094U 59 #define BSEC_SRLOCK1_OFF 0x098U 60 #define BSEC_SRLOCK2_OFF 0x09CU 61 #define BSEC_JTAG_IN_OFF 0x0ACU 62 #define BSEC_JTAG_OUT_OFF 0x0B0U 63 #define BSEC_SCRATCH_OFF 0x0B4U 64 #define BSEC_OTP_DATA_OFF 0x200U 65 #define BSEC_IPHW_CFG_OFF 0xFF0U 66 #define BSEC_IPVR_OFF 0xFF4U 67 #define BSEC_IP_ID_OFF 0xFF8U 68 #define BSEC_IP_MAGIC_ID_OFF 0xFFCU 69 70 /* BSEC_CONFIGURATION Register */ 71 #define BSEC_CONF_POWER_UP_MASK BIT(0) 72 #define BSEC_CONF_POWER_UP_SHIFT 0 73 #define BSEC_CONF_FRQ_MASK GENMASK_32(2, 1) 74 #define BSEC_CONF_FRQ_SHIFT 1 75 #define BSEC_CONF_PRG_WIDTH_MASK GENMASK_32(6, 3) 76 #define BSEC_CONF_PRG_WIDTH_SHIFT 3 77 #define BSEC_CONF_TREAD_MASK GENMASK_32(8, 7) 78 #define BSEC_CONF_TREAD_SHIFT 7 79 80 /* BSEC_CONTROL Register */ 81 #define BSEC_READ 0x000U 82 #define BSEC_WRITE 0x100U 83 #define BSEC_LOCK 0x200U 84 85 /* BSEC_STATUS Register */ 86 #define BSEC_MODE_STATUS_MASK GENMASK_32(2, 0) 87 #define BSEC_MODE_BUSY_MASK BIT(3) 88 #define BSEC_MODE_PROGFAIL_MASK BIT(4) 89 #define BSEC_MODE_PWR_MASK BIT(5) 90 #define BSEC_MODE_BIST1_LOCK_MASK BIT(6) 91 #define BSEC_MODE_BIST2_LOCK_MASK BIT(7) 92 93 /* BSEC_DEBUG */ 94 #define BSEC_HDPEN BIT(4) 95 #define BSEC_SPIDEN BIT(5) 96 #define BSEC_SPINDEN BIT(6) 97 #define BSEC_DBGSWGEN BIT(10) 98 #define BSEC_DEN_ALL_MSK GENMASK_32(10, 0) 99 100 /* 101 * OTP Lock services definition 102 * Value must corresponding to the bit position in the register 103 */ 104 #define BSEC_LOCK_UPPER_OTP 0x00 105 #define BSEC_LOCK_DEBUG 0x02 106 #define BSEC_LOCK_PROGRAM 0x04 107 108 /* Timeout when polling on status */ 109 #define BSEC_TIMEOUT_US 1000 110 111 #define BITS_PER_WORD (CHAR_BIT * sizeof(uint32_t)) 112 113 struct bsec_dev { 114 struct io_pa_va base; 115 unsigned int upper_base; 116 unsigned int max_id; 117 uint32_t *nsec_access; 118 }; 119 120 /* Only 1 instance of BSEC is expected per platform */ 121 static struct bsec_dev bsec_dev; 122 123 /* BSEC access protection */ 124 static unsigned int lock = SPINLOCK_UNLOCK; 125 126 static uint32_t bsec_lock(void) 127 { 128 return may_spin_lock(&lock); 129 } 130 131 static void bsec_unlock(uint32_t exceptions) 132 { 133 may_spin_unlock(&lock, exceptions); 134 } 135 136 static uint32_t otp_max_id(void) 137 { 138 return bsec_dev.max_id; 139 } 140 141 static uint32_t otp_bank_offset(uint32_t otp_id) 142 { 143 assert(otp_id <= otp_max_id()); 144 145 return ((otp_id & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT) * 146 sizeof(uint32_t); 147 } 148 149 static vaddr_t bsec_base(void) 150 { 151 return io_pa_or_va_secure(&bsec_dev.base); 152 } 153 154 static uint32_t bsec_status(void) 155 { 156 return io_read32(bsec_base() + BSEC_OTP_STATUS_OFF); 157 } 158 159 /* 160 * Check that BSEC interface does not report an error 161 * @otp_id : OTP number 162 * @check_disturbed: check only error (false) or all sources (true) 163 * Return a TEE_Result compliant value 164 */ 165 static TEE_Result check_no_error(uint32_t otp_id, bool check_disturbed) 166 { 167 uint32_t bit = BIT(otp_id & BSEC_OTP_MASK); 168 uint32_t bank = otp_bank_offset(otp_id); 169 170 if (io_read32(bsec_base() + BSEC_ERROR_OFF + bank) & bit) 171 return TEE_ERROR_GENERIC; 172 173 if (check_disturbed && 174 io_read32(bsec_base() + BSEC_DISTURBED_OFF + bank) & bit) 175 return TEE_ERROR_GENERIC; 176 177 return TEE_SUCCESS; 178 } 179 180 static TEE_Result power_up_safmem(void) 181 { 182 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 183 184 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP_MASK, 185 BSEC_CONF_POWER_UP_MASK); 186 187 /* 188 * If a timeout is detected, test the condition again to consider 189 * cases where timeout is due to the executing TEE thread rescheduling. 190 */ 191 while (!timeout_elapsed(timeout_ref)) 192 if (bsec_status() & BSEC_MODE_PWR_MASK) 193 break; 194 195 if (bsec_status() & BSEC_MODE_PWR_MASK) 196 return TEE_SUCCESS; 197 198 return TEE_ERROR_GENERIC; 199 } 200 201 static TEE_Result power_down_safmem(void) 202 { 203 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 204 205 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, 0, BSEC_CONF_POWER_UP_MASK); 206 207 /* 208 * If a timeout is detected, test the condition again to consider 209 * cases where timeout is due to the executing TEE thread rescheduling. 210 */ 211 while (!timeout_elapsed(timeout_ref)) 212 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 213 break; 214 215 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 216 return TEE_SUCCESS; 217 218 return TEE_ERROR_GENERIC; 219 } 220 221 TEE_Result stm32_bsec_shadow_register(uint32_t otp_id) 222 { 223 TEE_Result result = 0; 224 uint32_t exceptions = 0; 225 uint64_t timeout_ref = 0; 226 bool locked = false; 227 228 /* Check if shadowing of OTP is locked, informative only */ 229 result = stm32_bsec_read_sr_lock(otp_id, &locked); 230 if (result) 231 return result; 232 233 if (locked) 234 DMSG("BSEC shadow warning: OTP locked"); 235 236 exceptions = bsec_lock(); 237 238 result = power_up_safmem(); 239 if (result) 240 return result; 241 242 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_READ); 243 244 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 245 while (!timeout_elapsed(timeout_ref)) 246 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 247 break; 248 249 if (bsec_status() & BSEC_MODE_BUSY_MASK) 250 result = TEE_ERROR_GENERIC; 251 else 252 result = check_no_error(otp_id, true /* check-disturbed */); 253 254 power_down_safmem(); 255 256 bsec_unlock(exceptions); 257 258 return result; 259 } 260 261 TEE_Result stm32_bsec_read_otp(uint32_t *value, uint32_t otp_id) 262 { 263 if (otp_id > otp_max_id()) 264 return TEE_ERROR_BAD_PARAMETERS; 265 266 *value = io_read32(bsec_base() + BSEC_OTP_DATA_OFF + 267 (otp_id * sizeof(uint32_t))); 268 269 return TEE_SUCCESS; 270 } 271 272 TEE_Result stm32_bsec_shadow_read_otp(uint32_t *otp_value, uint32_t otp_id) 273 { 274 TEE_Result result = 0; 275 276 result = stm32_bsec_shadow_register(otp_id); 277 if (result) { 278 EMSG("BSEC %"PRIu32" Shadowing Error %#"PRIx32, otp_id, result); 279 return result; 280 } 281 282 result = stm32_bsec_read_otp(otp_value, otp_id); 283 if (result) 284 EMSG("BSEC %"PRIu32" Read Error %#"PRIx32, otp_id, result); 285 286 return result; 287 } 288 289 TEE_Result stm32_bsec_write_otp(uint32_t value, uint32_t otp_id) 290 { 291 TEE_Result result = 0; 292 uint32_t exceptions = 0; 293 vaddr_t otp_data_base = bsec_base() + BSEC_OTP_DATA_OFF; 294 bool locked = false; 295 296 /* Check if write of OTP is locked, informative only */ 297 result = stm32_bsec_read_sw_lock(otp_id, &locked); 298 if (result) 299 return result; 300 301 if (locked) 302 DMSG("BSEC write warning: OTP locked"); 303 304 exceptions = bsec_lock(); 305 306 io_write32(otp_data_base + (otp_id * sizeof(uint32_t)), value); 307 308 bsec_unlock(exceptions); 309 310 return TEE_SUCCESS; 311 } 312 313 #ifdef CFG_STM32_BSEC_WRITE 314 TEE_Result stm32_bsec_program_otp(uint32_t value, uint32_t otp_id) 315 { 316 TEE_Result result = 0; 317 uint32_t exceptions = 0; 318 uint64_t timeout_ref = 0; 319 bool locked = false; 320 321 /* Check if shadowing of OTP is locked, informative only */ 322 result = stm32_bsec_read_sp_lock(otp_id, &locked); 323 if (result) 324 return result; 325 326 if (locked) 327 DMSG("BSEC program warning: OTP locked"); 328 329 if (io_read32(bsec_base() + BSEC_OTP_LOCK_OFF) & BIT(BSEC_LOCK_PROGRAM)) 330 DMSG("BSEC program warning: GPLOCK activated"); 331 332 exceptions = bsec_lock(); 333 334 result = power_up_safmem(); 335 if (result) 336 return result; 337 338 io_write32(bsec_base() + BSEC_OTP_WRDATA_OFF, value); 339 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_WRITE); 340 341 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 342 while (!timeout_elapsed(timeout_ref)) 343 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 344 break; 345 346 if (bsec_status() & (BSEC_MODE_BUSY_MASK | BSEC_MODE_PROGFAIL_MASK)) 347 result = TEE_ERROR_GENERIC; 348 else 349 result = check_no_error(otp_id, true /* check-disturbed */); 350 351 power_down_safmem(); 352 353 bsec_unlock(exceptions); 354 355 return result; 356 } 357 #endif /*CFG_STM32_BSEC_WRITE*/ 358 359 TEE_Result stm32_bsec_permanent_lock_otp(uint32_t otp_id) 360 { 361 TEE_Result result = 0; 362 uint32_t data = 0; 363 uint32_t addr = 0; 364 uint32_t exceptions = 0; 365 vaddr_t base = bsec_base(); 366 uint64_t timeout_ref; 367 368 if (otp_id > otp_max_id()) 369 return TEE_ERROR_BAD_PARAMETERS; 370 371 if (otp_id < bsec_dev.upper_base) { 372 addr = otp_id >> ADDR_LOWER_OTP_PERLOCK_SHIFT; 373 data = DATA_LOWER_OTP_PERLOCK_BIT << 374 ((otp_id & DATA_LOWER_OTP_PERLOCK_MASK) << 1U); 375 } else { 376 addr = (otp_id >> ADDR_UPPER_OTP_PERLOCK_SHIFT) + 2U; 377 data = DATA_UPPER_OTP_PERLOCK_BIT << 378 (otp_id & DATA_UPPER_OTP_PERLOCK_MASK); 379 } 380 381 exceptions = bsec_lock(); 382 383 result = power_up_safmem(); 384 if (result) 385 return result; 386 387 io_write32(base + BSEC_OTP_WRDATA_OFF, data); 388 io_write32(base + BSEC_OTP_CTRL_OFF, addr | BSEC_WRITE | BSEC_LOCK); 389 390 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 391 while (!timeout_elapsed(timeout_ref)) 392 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 393 break; 394 395 if (bsec_status() & (BSEC_MODE_BUSY_MASK | BSEC_MODE_PROGFAIL_MASK)) 396 result = TEE_ERROR_BAD_PARAMETERS; 397 else 398 result = check_no_error(otp_id, false /* not-disturbed */); 399 400 power_down_safmem(); 401 402 bsec_unlock(exceptions); 403 404 return result; 405 } 406 407 #ifdef CFG_STM32_BSEC_WRITE 408 TEE_Result stm32_bsec_write_debug_conf(uint32_t value) 409 { 410 TEE_Result result = TEE_ERROR_GENERIC; 411 uint32_t masked_val = value & BSEC_DEN_ALL_MSK; 412 uint32_t exceptions = 0; 413 414 exceptions = bsec_lock(); 415 416 io_write32(bsec_base() + BSEC_DEN_OFF, value); 417 418 if ((io_read32(bsec_base() + BSEC_DEN_OFF) ^ masked_val) == 0U) 419 result = TEE_SUCCESS; 420 421 bsec_unlock(exceptions); 422 423 return result; 424 } 425 #endif /*CFG_STM32_BSEC_WRITE*/ 426 427 uint32_t stm32_bsec_read_debug_conf(void) 428 { 429 return io_read32(bsec_base() + BSEC_DEN_OFF); 430 } 431 432 static TEE_Result set_bsec_lock(uint32_t otp_id, size_t lock_offset) 433 { 434 uint32_t bank = otp_bank_offset(otp_id); 435 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 436 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 437 uint32_t exceptions = 0; 438 439 if (otp_id > STM32MP1_OTP_MAX_ID) 440 return TEE_ERROR_BAD_PARAMETERS; 441 442 exceptions = bsec_lock(); 443 444 io_write32(lock_addr, otp_mask); 445 446 bsec_unlock(exceptions); 447 448 return TEE_SUCCESS; 449 } 450 451 TEE_Result stm32_bsec_set_sr_lock(uint32_t otp_id) 452 { 453 return set_bsec_lock(otp_id, BSEC_SRLOCK_OFF); 454 } 455 456 TEE_Result stm32_bsec_set_sw_lock(uint32_t otp_id) 457 { 458 return set_bsec_lock(otp_id, BSEC_SWLOCK_OFF); 459 } 460 461 TEE_Result stm32_bsec_set_sp_lock(uint32_t otp_id) 462 { 463 return set_bsec_lock(otp_id, BSEC_SPLOCK_OFF); 464 } 465 466 static TEE_Result read_bsec_lock(uint32_t otp_id, bool *locked, 467 size_t lock_offset) 468 { 469 uint32_t bank = otp_bank_offset(otp_id); 470 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 471 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 472 473 if (otp_id > STM32MP1_OTP_MAX_ID) 474 return TEE_ERROR_BAD_PARAMETERS; 475 476 *locked = (io_read32(lock_addr) & otp_mask) != 0; 477 478 return TEE_SUCCESS; 479 } 480 481 TEE_Result stm32_bsec_read_sr_lock(uint32_t otp_id, bool *locked) 482 { 483 return read_bsec_lock(otp_id, locked, BSEC_SRLOCK_OFF); 484 } 485 486 TEE_Result stm32_bsec_read_sw_lock(uint32_t otp_id, bool *locked) 487 { 488 return read_bsec_lock(otp_id, locked, BSEC_SWLOCK_OFF); 489 } 490 491 TEE_Result stm32_bsec_read_sp_lock(uint32_t otp_id, bool *locked) 492 { 493 return read_bsec_lock(otp_id, locked, BSEC_SPLOCK_OFF); 494 } 495 496 TEE_Result stm32_bsec_read_permanent_lock(uint32_t otp_id, bool *locked) 497 { 498 return read_bsec_lock(otp_id, locked, BSEC_WRLOCK_OFF); 499 } 500 501 TEE_Result stm32_bsec_otp_lock(uint32_t service) 502 { 503 vaddr_t addr = bsec_base() + BSEC_OTP_LOCK_OFF; 504 505 switch (service) { 506 case BSEC_LOCK_UPPER_OTP: 507 io_write32(addr, BIT(BSEC_LOCK_UPPER_OTP)); 508 break; 509 case BSEC_LOCK_DEBUG: 510 io_write32(addr, BIT(BSEC_LOCK_DEBUG)); 511 break; 512 case BSEC_LOCK_PROGRAM: 513 io_write32(addr, BIT(BSEC_LOCK_PROGRAM)); 514 break; 515 default: 516 return TEE_ERROR_BAD_PARAMETERS; 517 } 518 519 return TEE_SUCCESS; 520 } 521 522 static size_t nsec_access_array_size(void) 523 { 524 size_t upper_count = otp_max_id() - bsec_dev.upper_base + 1; 525 526 return ROUNDUP(upper_count, BITS_PER_WORD) / BITS_PER_WORD; 527 } 528 529 static bool nsec_access_granted(unsigned int index) 530 { 531 uint32_t *array = bsec_dev.nsec_access; 532 533 return array && 534 (index / BITS_PER_WORD) < nsec_access_array_size() && 535 array[index / BITS_PER_WORD] & BIT(index % BITS_PER_WORD); 536 } 537 538 bool stm32_bsec_nsec_can_access_otp(uint32_t otp_id) 539 { 540 return otp_id < bsec_dev.upper_base || 541 nsec_access_granted(otp_id - bsec_dev.upper_base); 542 } 543 544 #ifdef CFG_DT 545 static void enable_nsec_access(unsigned int otp_id) 546 { 547 unsigned int idx = (otp_id - bsec_dev.upper_base) / BITS_PER_WORD; 548 549 if (otp_id < bsec_dev.upper_base) 550 return; 551 552 if (otp_id > otp_max_id() || stm32_bsec_shadow_register(otp_id)) 553 panic(); 554 555 bsec_dev.nsec_access[idx] |= BIT(otp_id % BITS_PER_WORD); 556 } 557 558 static void bsec_dt_otp_nsec_access(void *fdt, int bsec_node) 559 { 560 int bsec_subnode = 0; 561 562 bsec_dev.nsec_access = calloc(nsec_access_array_size(), 563 sizeof(*bsec_dev.nsec_access)); 564 if (!bsec_dev.nsec_access) 565 panic(); 566 567 fdt_for_each_subnode(bsec_subnode, fdt, bsec_node) { 568 const fdt32_t *cuint = NULL; 569 unsigned int otp_id = 0; 570 unsigned int i = 0; 571 size_t size = 0; 572 uint32_t offset = 0; 573 uint32_t length = 0; 574 575 cuint = fdt_getprop(fdt, bsec_subnode, "reg", NULL); 576 assert(cuint); 577 578 offset = fdt32_to_cpu(*cuint); 579 cuint++; 580 length = fdt32_to_cpu(*cuint); 581 582 otp_id = offset / sizeof(uint32_t); 583 584 if (otp_id < STM32MP1_UPPER_OTP_START) { 585 unsigned int otp_end = ROUNDUP(offset + length, 586 sizeof(uint32_t)) / 587 sizeof(uint32_t); 588 589 if (otp_end > STM32MP1_UPPER_OTP_START) { 590 /* 591 * OTP crosses Lower/Upper boundary, consider 592 * only the upper part. 593 */ 594 otp_id = STM32MP1_UPPER_OTP_START; 595 length -= (STM32MP1_UPPER_OTP_START * 596 sizeof(uint32_t)) - offset; 597 offset = STM32MP1_UPPER_OTP_START * 598 sizeof(uint32_t); 599 600 DMSG("OTP crosses Lower/Upper boundary"); 601 } else { 602 continue; 603 } 604 } 605 606 if (!fdt_getprop(fdt, bsec_subnode, "st,non-secure-otp", NULL)) 607 continue; 608 609 if ((offset % sizeof(uint32_t)) || (length % sizeof(uint32_t))) 610 panic("Unaligned non-secure OTP"); 611 612 size = length / sizeof(uint32_t); 613 614 if (otp_id + size > STM32MP1_OTP_MAX_ID) 615 panic("OTP range oversized"); 616 617 for (i = otp_id; i < otp_id + size; i++) 618 enable_nsec_access(i); 619 } 620 } 621 622 static void initialize_bsec_from_dt(void) 623 { 624 void *fdt = NULL; 625 int node = 0; 626 struct dt_node_info bsec_info = { }; 627 628 fdt = get_embedded_dt(); 629 node = fdt_node_offset_by_compatible(fdt, 0, "st,stm32mp15-bsec"); 630 if (node < 0) 631 panic(); 632 633 _fdt_fill_device_info(fdt, &bsec_info, node); 634 635 if (bsec_info.reg != bsec_dev.base.pa || 636 !(bsec_info.status & DT_STATUS_OK_SEC)) 637 panic(); 638 639 bsec_dt_otp_nsec_access(fdt, node); 640 } 641 #else 642 static void initialize_bsec_from_dt(void) 643 { 644 } 645 #endif /*CFG_DT*/ 646 647 static TEE_Result initialize_bsec(void) 648 { 649 struct stm32_bsec_static_cfg cfg = { }; 650 651 stm32mp_get_bsec_static_cfg(&cfg); 652 653 bsec_dev.base.pa = cfg.base; 654 bsec_dev.upper_base = cfg.upper_start; 655 bsec_dev.max_id = cfg.max_id; 656 657 if (IS_ENABLED(CFG_EMBED_DTB)) 658 initialize_bsec_from_dt(); 659 660 return TEE_SUCCESS; 661 } 662 663 driver_init(initialize_bsec); 664