1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2020, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32_bsec.h> 9 #include <io.h> 10 #include <kernel/delay.h> 11 #include <kernel/dt.h> 12 #include <kernel/generic_boot.h> 13 #include <kernel/spinlock.h> 14 #include <limits.h> 15 #include <mm/core_memprot.h> 16 #include <platform_config.h> 17 #include <stm32_util.h> 18 #include <string.h> 19 #include <tee_api_defines.h> 20 #include <types_ext.h> 21 #include <util.h> 22 23 #ifdef CFG_DT 24 #include <libfdt.h> 25 #endif 26 27 #define BSEC_OTP_MASK GENMASK_32(4, 0) 28 #define BSEC_OTP_BANK_SHIFT 5 29 30 /* Permanent lock bitmasks */ 31 #define ADDR_LOWER_OTP_PERLOCK_SHIFT 3 32 #define DATA_LOWER_OTP_PERLOCK_BIT 3 33 #define DATA_LOWER_OTP_PERLOCK_MASK GENMASK_32(2, 0) 34 #define ADDR_UPPER_OTP_PERLOCK_SHIFT 4 35 #define DATA_UPPER_OTP_PERLOCK_BIT 1 36 #define DATA_UPPER_OTP_PERLOCK_MASK GENMASK_32(3, 0) 37 38 /* BSEC register offset */ 39 #define BSEC_OTP_CONF_OFF 0x000U 40 #define BSEC_OTP_CTRL_OFF 0x004U 41 #define BSEC_OTP_WRDATA_OFF 0x008U 42 #define BSEC_OTP_STATUS_OFF 0x00CU 43 #define BSEC_OTP_LOCK_OFF 0x010U 44 #define BSEC_DEN_OFF 0x014U 45 #define BSEC_FEN_OFF 0x018U 46 #define BSEC_DISTURBED_OFF 0x01CU 47 #define BSEC_DISTURBED1_OFF 0x020U 48 #define BSEC_DISTURBED2_OFF 0x024U 49 #define BSEC_ERROR_OFF 0x034U 50 #define BSEC_ERROR1_OFF 0x038U 51 #define BSEC_ERROR2_OFF 0x03CU 52 #define BSEC_WRLOCK_OFF 0x04CU 53 #define BSEC_WRLOCK1_OFF 0x050U 54 #define BSEC_WRLOCK2_OFF 0x054U 55 #define BSEC_SPLOCK_OFF 0x064U 56 #define BSEC_SPLOCK1_OFF 0x068U 57 #define BSEC_SPLOCK2_OFF 0x06CU 58 #define BSEC_SWLOCK_OFF 0x07CU 59 #define BSEC_SWLOCK1_OFF 0x080U 60 #define BSEC_SWLOCK2_OFF 0x084U 61 #define BSEC_SRLOCK_OFF 0x094U 62 #define BSEC_SRLOCK1_OFF 0x098U 63 #define BSEC_SRLOCK2_OFF 0x09CU 64 #define BSEC_JTAG_IN_OFF 0x0ACU 65 #define BSEC_JTAG_OUT_OFF 0x0B0U 66 #define BSEC_SCRATCH_OFF 0x0B4U 67 #define BSEC_OTP_DATA_OFF 0x200U 68 #define BSEC_IPHW_CFG_OFF 0xFF0U 69 #define BSEC_IPVR_OFF 0xFF4U 70 #define BSEC_IP_ID_OFF 0xFF8U 71 #define BSEC_IP_MAGIC_ID_OFF 0xFFCU 72 73 /* BSEC_CONFIGURATION Register */ 74 #define BSEC_CONF_POWER_UP_MASK BIT(0) 75 #define BSEC_CONF_POWER_UP_SHIFT 0 76 #define BSEC_CONF_FRQ_MASK GENMASK_32(2, 1) 77 #define BSEC_CONF_FRQ_SHIFT 1 78 #define BSEC_CONF_PRG_WIDTH_MASK GENMASK_32(6, 3) 79 #define BSEC_CONF_PRG_WIDTH_SHIFT 3 80 #define BSEC_CONF_TREAD_MASK GENMASK_32(8, 7) 81 #define BSEC_CONF_TREAD_SHIFT 7 82 83 /* BSEC_CONTROL Register */ 84 #define BSEC_READ 0x000U 85 #define BSEC_WRITE 0x100U 86 #define BSEC_LOCK 0x200U 87 88 /* BSEC_STATUS Register */ 89 #define BSEC_MODE_STATUS_MASK GENMASK_32(2, 0) 90 #define BSEC_MODE_BUSY_MASK BIT(3) 91 #define BSEC_MODE_PROGFAIL_MASK BIT(4) 92 #define BSEC_MODE_PWR_MASK BIT(5) 93 #define BSEC_MODE_BIST1_LOCK_MASK BIT(6) 94 #define BSEC_MODE_BIST2_LOCK_MASK BIT(7) 95 96 /* BSEC_DEBUG */ 97 #define BSEC_HDPEN BIT(4) 98 #define BSEC_SPIDEN BIT(5) 99 #define BSEC_SPINDEN BIT(6) 100 #define BSEC_DBGSWGEN BIT(10) 101 #define BSEC_DEN_ALL_MSK GENMASK_32(10, 0) 102 103 /* 104 * OTP Lock services definition 105 * Value must corresponding to the bit position in the register 106 */ 107 #define BSEC_LOCK_UPPER_OTP 0x00 108 #define BSEC_LOCK_DEBUG 0x02 109 #define BSEC_LOCK_PROGRAM 0x04 110 111 /* Timeout when polling on status */ 112 #define BSEC_TIMEOUT_US 1000 113 114 #define BITS_PER_WORD (CHAR_BIT * sizeof(uint32_t)) 115 116 struct bsec_dev { 117 struct io_pa_va base; 118 unsigned int upper_base; 119 unsigned int max_id; 120 uint32_t *nsec_access; 121 }; 122 123 /* Only 1 instance of BSEC is expected per platform */ 124 static struct bsec_dev bsec_dev; 125 126 /* BSEC access protection */ 127 static unsigned int lock = SPINLOCK_UNLOCK; 128 129 static uint32_t bsec_lock(void) 130 { 131 return may_spin_lock(&lock); 132 } 133 134 static void bsec_unlock(uint32_t exceptions) 135 { 136 may_spin_unlock(&lock, exceptions); 137 } 138 139 static uint32_t otp_max_id(void) 140 { 141 return bsec_dev.max_id; 142 } 143 144 static uint32_t otp_bank_offset(uint32_t otp_id) 145 { 146 assert(otp_id <= otp_max_id()); 147 148 return ((otp_id & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT) * 149 sizeof(uint32_t); 150 } 151 152 static vaddr_t bsec_base(void) 153 { 154 return io_pa_or_va_secure(&bsec_dev.base); 155 } 156 157 static uint32_t bsec_status(void) 158 { 159 return io_read32(bsec_base() + BSEC_OTP_STATUS_OFF); 160 } 161 162 /* 163 * Check that BSEC interface does not report an error 164 * @otp_id : OTP number 165 * @check_disturbed: check only error (false) or all sources (true) 166 * Return a TEE_Result compliant value 167 */ 168 static TEE_Result check_no_error(uint32_t otp_id, bool check_disturbed) 169 { 170 uint32_t bit = BIT(otp_id & BSEC_OTP_MASK); 171 uint32_t bank = otp_bank_offset(otp_id); 172 173 if (io_read32(bsec_base() + BSEC_ERROR_OFF + bank) & bit) 174 return TEE_ERROR_GENERIC; 175 176 if (check_disturbed && 177 io_read32(bsec_base() + BSEC_DISTURBED_OFF + bank) & bit) 178 return TEE_ERROR_GENERIC; 179 180 return TEE_SUCCESS; 181 } 182 183 static TEE_Result power_up_safmem(void) 184 { 185 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 186 187 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP_MASK, 188 BSEC_CONF_POWER_UP_MASK); 189 190 /* 191 * If a timeout is detected, test the condition again to consider 192 * cases where timeout is due to the executing TEE thread rescheduling. 193 */ 194 while (!timeout_elapsed(timeout_ref)) 195 if (bsec_status() & BSEC_MODE_PWR_MASK) 196 break; 197 198 if (bsec_status() & BSEC_MODE_PWR_MASK) 199 return TEE_SUCCESS; 200 201 return TEE_ERROR_GENERIC; 202 } 203 204 static TEE_Result power_down_safmem(void) 205 { 206 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 207 208 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, 0, BSEC_CONF_POWER_UP_MASK); 209 210 /* 211 * If a timeout is detected, test the condition again to consider 212 * cases where timeout is due to the executing TEE thread rescheduling. 213 */ 214 while (!timeout_elapsed(timeout_ref)) 215 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 216 break; 217 218 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 219 return TEE_SUCCESS; 220 221 return TEE_ERROR_GENERIC; 222 } 223 224 TEE_Result stm32_bsec_shadow_register(uint32_t otp_id) 225 { 226 TEE_Result result = 0; 227 uint32_t exceptions = 0; 228 uint64_t timeout_ref = 0; 229 bool locked = false; 230 231 /* Check if shadowing of OTP is locked, informative only */ 232 result = stm32_bsec_read_sr_lock(otp_id, &locked); 233 if (result) 234 return result; 235 236 if (locked) 237 DMSG("BSEC shadow warning: OTP locked"); 238 239 exceptions = bsec_lock(); 240 241 result = power_up_safmem(); 242 if (result) 243 return result; 244 245 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_READ); 246 247 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 248 while (!timeout_elapsed(timeout_ref)) 249 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 250 break; 251 252 if (bsec_status() & BSEC_MODE_BUSY_MASK) 253 result = TEE_ERROR_GENERIC; 254 else 255 result = check_no_error(otp_id, true /* check-disturbed */); 256 257 power_down_safmem(); 258 259 bsec_unlock(exceptions); 260 261 return result; 262 } 263 264 TEE_Result stm32_bsec_read_otp(uint32_t *value, uint32_t otp_id) 265 { 266 if (otp_id > otp_max_id()) 267 return TEE_ERROR_BAD_PARAMETERS; 268 269 *value = io_read32(bsec_base() + BSEC_OTP_DATA_OFF + 270 (otp_id * sizeof(uint32_t))); 271 272 return TEE_SUCCESS; 273 } 274 275 TEE_Result stm32_bsec_shadow_read_otp(uint32_t *otp_value, uint32_t otp_id) 276 { 277 TEE_Result result = 0; 278 279 result = stm32_bsec_shadow_register(otp_id); 280 if (result) { 281 EMSG("BSEC %"PRIu32" Shadowing Error %#"PRIx32, otp_id, result); 282 return result; 283 } 284 285 result = stm32_bsec_read_otp(otp_value, otp_id); 286 if (result) 287 EMSG("BSEC %"PRIu32" Read Error %#"PRIx32, otp_id, result); 288 289 return result; 290 } 291 292 #ifdef CFG_STM32_BSEC_WRITE 293 TEE_Result stm32_bsec_write_otp(uint32_t value, uint32_t otp_id) 294 { 295 TEE_Result result = 0; 296 uint32_t exceptions = 0; 297 vaddr_t otp_data_base = bsec_base() + BSEC_OTP_DATA_OFF; 298 bool locked = false; 299 300 /* Check if write of OTP is locked, informative only */ 301 result = stm32_bsec_read_sw_lock(otp_id, &locked); 302 if (result) 303 return result; 304 305 if (locked) 306 DMSG("BSEC write warning: OTP locked"); 307 308 exceptions = bsec_lock(); 309 310 io_write32(otp_data_base + (otp_id * sizeof(uint32_t)), value); 311 312 bsec_unlock(exceptions); 313 314 return TEE_SUCCESS; 315 } 316 317 TEE_Result stm32_bsec_program_otp(uint32_t value, uint32_t otp_id) 318 { 319 TEE_Result result = 0; 320 uint32_t exceptions = 0; 321 uint64_t timeout_ref = 0; 322 bool locked = false; 323 324 /* Check if shadowing of OTP is locked, informative only */ 325 result = stm32_bsec_read_sp_lock(otp_id, &locked); 326 if (result) 327 return result; 328 329 if (locked) 330 DMSG("BSEC program warning: OTP locked"); 331 332 if (io_read32(bsec_base() + BSEC_OTP_LOCK_OFF) & BIT(BSEC_LOCK_PROGRAM)) 333 DMSG("BSEC program warning: GPLOCK activated"); 334 335 exceptions = bsec_lock(); 336 337 result = power_up_safmem(); 338 if (result) 339 return result; 340 341 io_write32(bsec_base() + BSEC_OTP_WRDATA_OFF, value); 342 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_WRITE); 343 344 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 345 while (!timeout_elapsed(timeout_ref)) 346 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 347 break; 348 349 if (bsec_status() & (BSEC_MODE_BUSY_MASK | BSEC_MODE_PROGFAIL_MASK)) 350 result = TEE_ERROR_GENERIC; 351 else 352 result = check_no_error(otp_id, true /* check-disturbed */); 353 354 power_down_safmem(); 355 356 bsec_unlock(exceptions); 357 358 return result; 359 } 360 #endif /*CFG_STM32_BSEC_WRITE*/ 361 362 TEE_Result stm32_bsec_permanent_lock_otp(uint32_t otp_id) 363 { 364 TEE_Result result = 0; 365 uint32_t data = 0; 366 uint32_t addr = 0; 367 uint32_t exceptions = 0; 368 vaddr_t base = bsec_base(); 369 uint64_t timeout_ref; 370 371 if (otp_id > otp_max_id()) 372 return TEE_ERROR_BAD_PARAMETERS; 373 374 if (otp_id < bsec_dev.upper_base) { 375 addr = otp_id >> ADDR_LOWER_OTP_PERLOCK_SHIFT; 376 data = DATA_LOWER_OTP_PERLOCK_BIT << 377 ((otp_id & DATA_LOWER_OTP_PERLOCK_MASK) << 1U); 378 } else { 379 addr = (otp_id >> ADDR_UPPER_OTP_PERLOCK_SHIFT) + 2U; 380 data = DATA_UPPER_OTP_PERLOCK_BIT << 381 (otp_id & DATA_UPPER_OTP_PERLOCK_MASK); 382 } 383 384 exceptions = bsec_lock(); 385 386 result = power_up_safmem(); 387 if (result) 388 return result; 389 390 io_write32(base + BSEC_OTP_WRDATA_OFF, data); 391 io_write32(base + BSEC_OTP_CTRL_OFF, addr | BSEC_WRITE | BSEC_LOCK); 392 393 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 394 while (!timeout_elapsed(timeout_ref)) 395 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 396 break; 397 398 if (bsec_status() & (BSEC_MODE_BUSY_MASK | BSEC_MODE_PROGFAIL_MASK)) 399 result = TEE_ERROR_BAD_PARAMETERS; 400 else 401 result = check_no_error(otp_id, false /* not-disturbed */); 402 403 power_down_safmem(); 404 405 bsec_unlock(exceptions); 406 407 return result; 408 } 409 410 #ifdef CFG_STM32_BSEC_WRITE 411 TEE_Result stm32_bsec_write_debug_conf(uint32_t value) 412 { 413 TEE_Result result = TEE_ERROR_GENERIC; 414 uint32_t masked_val = value & BSEC_DEN_ALL_MSK; 415 uint32_t exceptions = 0; 416 417 exceptions = bsec_lock(); 418 419 io_write32(bsec_base() + BSEC_DEN_OFF, value); 420 421 if ((io_read32(bsec_base() + BSEC_DEN_OFF) ^ masked_val) == 0U) 422 result = TEE_SUCCESS; 423 424 bsec_unlock(exceptions); 425 426 return result; 427 } 428 #endif /*CFG_STM32_BSEC_WRITE*/ 429 430 uint32_t stm32_bsec_read_debug_conf(void) 431 { 432 return io_read32(bsec_base() + BSEC_DEN_OFF); 433 } 434 435 static TEE_Result set_bsec_lock(uint32_t otp_id, size_t lock_offset) 436 { 437 uint32_t bank = otp_bank_offset(otp_id); 438 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 439 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 440 uint32_t exceptions = 0; 441 442 if (otp_id > STM32MP1_OTP_MAX_ID) 443 return TEE_ERROR_BAD_PARAMETERS; 444 445 exceptions = bsec_lock(); 446 447 io_write32(lock_addr, otp_mask); 448 449 bsec_unlock(exceptions); 450 451 return TEE_SUCCESS; 452 } 453 454 TEE_Result stm32_bsec_set_sr_lock(uint32_t otp_id) 455 { 456 return set_bsec_lock(otp_id, BSEC_SRLOCK_OFF); 457 } 458 459 TEE_Result stm32_bsec_set_sw_lock(uint32_t otp_id) 460 { 461 return set_bsec_lock(otp_id, BSEC_SWLOCK_OFF); 462 } 463 464 TEE_Result stm32_bsec_set_sp_lock(uint32_t otp_id) 465 { 466 return set_bsec_lock(otp_id, BSEC_SPLOCK_OFF); 467 } 468 469 static TEE_Result read_bsec_lock(uint32_t otp_id, bool *locked, 470 size_t lock_offset) 471 { 472 uint32_t bank = otp_bank_offset(otp_id); 473 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 474 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 475 476 if (otp_id > STM32MP1_OTP_MAX_ID) 477 return TEE_ERROR_BAD_PARAMETERS; 478 479 *locked = (io_read32(lock_addr) & otp_mask) != 0; 480 481 return TEE_SUCCESS; 482 } 483 484 TEE_Result stm32_bsec_read_sr_lock(uint32_t otp_id, bool *locked) 485 { 486 return read_bsec_lock(otp_id, locked, BSEC_SRLOCK_OFF); 487 } 488 489 TEE_Result stm32_bsec_read_sw_lock(uint32_t otp_id, bool *locked) 490 { 491 return read_bsec_lock(otp_id, locked, BSEC_SWLOCK_OFF); 492 } 493 494 TEE_Result stm32_bsec_read_sp_lock(uint32_t otp_id, bool *locked) 495 { 496 return read_bsec_lock(otp_id, locked, BSEC_SPLOCK_OFF); 497 } 498 499 TEE_Result stm32_bsec_read_permanent_lock(uint32_t otp_id, bool *locked) 500 { 501 return read_bsec_lock(otp_id, locked, BSEC_WRLOCK_OFF); 502 } 503 504 TEE_Result stm32_bsec_otp_lock(uint32_t service) 505 { 506 vaddr_t addr = bsec_base() + BSEC_OTP_LOCK_OFF; 507 508 switch (service) { 509 case BSEC_LOCK_UPPER_OTP: 510 io_write32(addr, BIT(BSEC_LOCK_UPPER_OTP)); 511 break; 512 case BSEC_LOCK_DEBUG: 513 io_write32(addr, BIT(BSEC_LOCK_DEBUG)); 514 break; 515 case BSEC_LOCK_PROGRAM: 516 io_write32(addr, BIT(BSEC_LOCK_PROGRAM)); 517 break; 518 default: 519 return TEE_ERROR_BAD_PARAMETERS; 520 } 521 522 return TEE_SUCCESS; 523 } 524 525 static size_t nsec_access_array_size(void) 526 { 527 size_t upper_count = otp_max_id() - bsec_dev.upper_base + 1; 528 529 return ROUNDUP(upper_count, BITS_PER_WORD) / BITS_PER_WORD; 530 } 531 532 static bool nsec_access_granted(unsigned int index) 533 { 534 uint32_t *array = bsec_dev.nsec_access; 535 536 return array && 537 (index / BITS_PER_WORD) < nsec_access_array_size() && 538 array[index / BITS_PER_WORD] & BIT(index % BITS_PER_WORD); 539 } 540 541 bool stm32_bsec_nsec_can_access_otp(uint32_t otp_id) 542 { 543 return otp_id < bsec_dev.upper_base || 544 nsec_access_granted(otp_id - bsec_dev.upper_base); 545 } 546 547 #ifdef CFG_DT 548 static void enable_nsec_access(unsigned int otp_id) 549 { 550 unsigned int idx = (otp_id - bsec_dev.upper_base) / BITS_PER_WORD; 551 552 if (otp_id < bsec_dev.upper_base) 553 return; 554 555 if (otp_id > otp_max_id() || stm32_bsec_shadow_register(otp_id)) 556 panic(); 557 558 bsec_dev.nsec_access[idx] |= BIT(otp_id % BITS_PER_WORD); 559 } 560 561 static void bsec_dt_otp_nsec_access(void *fdt, int bsec_node) 562 { 563 int bsec_subnode = 0; 564 565 bsec_dev.nsec_access = calloc(nsec_access_array_size(), 566 sizeof(*bsec_dev.nsec_access)); 567 if (!bsec_dev.nsec_access) 568 panic(); 569 570 fdt_for_each_subnode(bsec_subnode, fdt, bsec_node) { 571 const fdt32_t *cuint = NULL; 572 unsigned int otp_id = 0; 573 unsigned int i = 0; 574 size_t size = 0; 575 uint32_t offset = 0; 576 uint32_t length = 0; 577 578 cuint = fdt_getprop(fdt, bsec_subnode, "reg", NULL); 579 assert(cuint); 580 581 offset = fdt32_to_cpu(*cuint); 582 cuint++; 583 length = fdt32_to_cpu(*cuint); 584 585 otp_id = offset / sizeof(uint32_t); 586 587 if (otp_id < STM32MP1_UPPER_OTP_START) { 588 unsigned int otp_end = ROUNDUP(offset + length, 589 sizeof(uint32_t)) / 590 sizeof(uint32_t); 591 592 if (otp_end > STM32MP1_UPPER_OTP_START) { 593 /* 594 * OTP crosses Lower/Upper boundary, consider 595 * only the upper part. 596 */ 597 otp_id = STM32MP1_UPPER_OTP_START; 598 length -= (STM32MP1_UPPER_OTP_START * 599 sizeof(uint32_t)) - offset; 600 offset = STM32MP1_UPPER_OTP_START * 601 sizeof(uint32_t); 602 603 DMSG("OTP crosses Lower/Upper boundary"); 604 } else { 605 continue; 606 } 607 } 608 609 if (!fdt_getprop(fdt, bsec_subnode, "st,non-secure-otp", NULL)) 610 continue; 611 612 if ((offset % sizeof(uint32_t)) || (length % sizeof(uint32_t))) 613 panic("Unaligned non-secure OTP"); 614 615 size = length / sizeof(uint32_t); 616 617 if (otp_id + size > STM32MP1_OTP_MAX_ID) 618 panic("OTP range oversized"); 619 620 for (i = otp_id; i < otp_id + size; i++) 621 enable_nsec_access(i); 622 } 623 } 624 625 static void initialize_bsec_from_dt(void) 626 { 627 void *fdt = NULL; 628 int node = 0; 629 struct dt_node_info bsec_info = { }; 630 631 fdt = get_embedded_dt(); 632 node = fdt_node_offset_by_compatible(fdt, 0, "st,stm32mp15-bsec"); 633 if (node < 0) 634 panic(); 635 636 _fdt_fill_device_info(fdt, &bsec_info, node); 637 638 if (bsec_info.reg != bsec_dev.base.pa || 639 !(bsec_info.status & DT_STATUS_OK_SEC)) 640 panic(); 641 642 bsec_dt_otp_nsec_access(fdt, node); 643 } 644 #else 645 static void initialize_bsec_from_dt(void) 646 { 647 } 648 #endif /*CFG_DT*/ 649 650 static TEE_Result initialize_bsec(void) 651 { 652 struct stm32_bsec_static_cfg cfg = { }; 653 654 stm32mp_get_bsec_static_cfg(&cfg); 655 656 bsec_dev.base.pa = cfg.base; 657 bsec_dev.upper_base = cfg.upper_start; 658 bsec_dev.max_id = cfg.max_id; 659 660 if (IS_ENABLED(CFG_EMBED_DTB)) 661 initialize_bsec_from_dt(); 662 663 return TEE_SUCCESS; 664 } 665 666 driver_init(initialize_bsec); 667