1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2020, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <drivers/stm32_bsec.h> 8 #include <io.h> 9 #include <kernel/delay.h> 10 #include <kernel/generic_boot.h> 11 #include <kernel/spinlock.h> 12 #include <limits.h> 13 #include <mm/core_memprot.h> 14 #include <platform_config.h> 15 #include <stm32_util.h> 16 #include <string.h> 17 #include <tee_api_defines.h> 18 #include <types_ext.h> 19 #include <util.h> 20 21 #define BSEC_OTP_MASK GENMASK_32(4, 0) 22 #define BSEC_OTP_BANK_SHIFT 5 23 24 /* Permanent lock bitmasks */ 25 #define ADDR_LOWER_OTP_PERLOCK_SHIFT 3 26 #define DATA_LOWER_OTP_PERLOCK_BIT 3 27 #define DATA_LOWER_OTP_PERLOCK_MASK GENMASK_32(2, 0) 28 #define ADDR_UPPER_OTP_PERLOCK_SHIFT 4 29 #define DATA_UPPER_OTP_PERLOCK_BIT 1 30 #define DATA_UPPER_OTP_PERLOCK_MASK GENMASK_32(3, 0) 31 32 /* BSEC register offset */ 33 #define BSEC_OTP_CONF_OFF 0x000U 34 #define BSEC_OTP_CTRL_OFF 0x004U 35 #define BSEC_OTP_WRDATA_OFF 0x008U 36 #define BSEC_OTP_STATUS_OFF 0x00CU 37 #define BSEC_OTP_LOCK_OFF 0x010U 38 #define BSEC_DEN_OFF 0x014U 39 #define BSEC_FEN_OFF 0x018U 40 #define BSEC_DISTURBED_OFF 0x01CU 41 #define BSEC_DISTURBED1_OFF 0x020U 42 #define BSEC_DISTURBED2_OFF 0x024U 43 #define BSEC_ERROR_OFF 0x034U 44 #define BSEC_ERROR1_OFF 0x038U 45 #define BSEC_ERROR2_OFF 0x03CU 46 #define BSEC_WRLOCK_OFF 0x04CU 47 #define BSEC_WRLOCK1_OFF 0x050U 48 #define BSEC_WRLOCK2_OFF 0x054U 49 #define BSEC_SPLOCK_OFF 0x064U 50 #define BSEC_SPLOCK1_OFF 0x068U 51 #define BSEC_SPLOCK2_OFF 0x06CU 52 #define BSEC_SWLOCK_OFF 0x07CU 53 #define BSEC_SWLOCK1_OFF 0x080U 54 #define BSEC_SWLOCK2_OFF 0x084U 55 #define BSEC_SRLOCK_OFF 0x094U 56 #define BSEC_SRLOCK1_OFF 0x098U 57 #define BSEC_SRLOCK2_OFF 0x09CU 58 #define BSEC_JTAG_IN_OFF 0x0ACU 59 #define BSEC_JTAG_OUT_OFF 0x0B0U 60 #define BSEC_SCRATCH_OFF 0x0B4U 61 #define BSEC_OTP_DATA_OFF 0x200U 62 #define BSEC_IPHW_CFG_OFF 0xFF0U 63 #define BSEC_IPVR_OFF 0xFF4U 64 #define BSEC_IP_ID_OFF 0xFF8U 65 #define BSEC_IP_MAGIC_ID_OFF 0xFFCU 66 67 /* BSEC_CONFIGURATION Register */ 68 #define BSEC_CONF_POWER_UP_MASK BIT(0) 69 #define BSEC_CONF_POWER_UP_SHIFT 0 70 #define BSEC_CONF_FRQ_MASK GENMASK_32(2, 1) 71 #define BSEC_CONF_FRQ_SHIFT 1 72 #define BSEC_CONF_PRG_WIDTH_MASK GENMASK_32(6, 3) 73 #define BSEC_CONF_PRG_WIDTH_SHIFT 3 74 #define BSEC_CONF_TREAD_MASK GENMASK_32(8, 7) 75 #define BSEC_CONF_TREAD_SHIFT 7 76 77 /* BSEC_CONTROL Register */ 78 #define BSEC_READ 0x000U 79 #define BSEC_WRITE 0x100U 80 #define BSEC_LOCK 0x200U 81 82 /* BSEC_STATUS Register */ 83 #define BSEC_MODE_STATUS_MASK GENMASK_32(2, 0) 84 #define BSEC_MODE_BUSY_MASK BIT(3) 85 #define BSEC_MODE_PROGFAIL_MASK BIT(4) 86 #define BSEC_MODE_PWR_MASK BIT(5) 87 #define BSEC_MODE_BIST1_LOCK_MASK BIT(6) 88 #define BSEC_MODE_BIST2_LOCK_MASK BIT(7) 89 90 /* BSEC_DEBUG */ 91 #define BSEC_HDPEN BIT(4) 92 #define BSEC_SPIDEN BIT(5) 93 #define BSEC_SPINDEN BIT(6) 94 #define BSEC_DBGSWGEN BIT(10) 95 #define BSEC_DEN_ALL_MSK GENMASK_32(10, 0) 96 97 /* 98 * OTP Lock services definition 99 * Value must corresponding to the bit position in the register 100 */ 101 #define BSEC_LOCK_UPPER_OTP 0x00 102 #define BSEC_LOCK_DEBUG 0x02 103 #define BSEC_LOCK_PROGRAM 0x04 104 105 /* Timeout when polling on status */ 106 #define BSEC_TIMEOUT_US 1000 107 108 struct bsec_dev { 109 struct io_pa_va base; 110 unsigned int upper_base; 111 unsigned int max_id; 112 bool closed_device; 113 }; 114 115 /* Only 1 instance of BSEC is expected per platform */ 116 static struct bsec_dev bsec_dev; 117 118 /* BSEC access protection */ 119 static unsigned int lock = SPINLOCK_UNLOCK; 120 121 static uint32_t bsec_lock(void) 122 { 123 return may_spin_lock(&lock); 124 } 125 126 static void bsec_unlock(uint32_t exceptions) 127 { 128 may_spin_unlock(&lock, exceptions); 129 } 130 131 static uint32_t otp_max_id(void) 132 { 133 return bsec_dev.max_id; 134 } 135 136 static uint32_t otp_bank_offset(uint32_t otp_id) 137 { 138 assert(otp_id <= otp_max_id()); 139 140 return ((otp_id & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT) * 141 sizeof(uint32_t); 142 } 143 144 static vaddr_t bsec_base(void) 145 { 146 return io_pa_or_va_secure(&bsec_dev.base); 147 } 148 149 static uint32_t bsec_status(void) 150 { 151 return io_read32(bsec_base() + BSEC_OTP_STATUS_OFF); 152 } 153 154 /* 155 * Check that BSEC interface does not report an error 156 * @otp_id : OTP number 157 * @check_disturbed: check only error (false) or all sources (true) 158 * Return a TEE_Result compliant value 159 */ 160 static TEE_Result check_no_error(uint32_t otp_id, bool check_disturbed) 161 { 162 uint32_t bit = BIT(otp_id & BSEC_OTP_MASK); 163 uint32_t bank = otp_bank_offset(otp_id); 164 165 if (io_read32(bsec_base() + BSEC_ERROR_OFF + bank) & bit) 166 return TEE_ERROR_GENERIC; 167 168 if (check_disturbed && 169 io_read32(bsec_base() + BSEC_DISTURBED_OFF + bank) & bit) 170 return TEE_ERROR_GENERIC; 171 172 return TEE_SUCCESS; 173 } 174 175 static TEE_Result power_up_safmem(void) 176 { 177 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 178 179 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP_MASK, 180 BSEC_CONF_POWER_UP_MASK); 181 182 /* 183 * If a timeout is detected, test the condition again to consider 184 * cases where timeout is due to the executing TEE thread rescheduling. 185 */ 186 while (!timeout_elapsed(timeout_ref)) 187 if (bsec_status() & BSEC_MODE_PWR_MASK) 188 break; 189 190 if (bsec_status() & BSEC_MODE_PWR_MASK) 191 return TEE_SUCCESS; 192 193 return TEE_ERROR_GENERIC; 194 } 195 196 static TEE_Result power_down_safmem(void) 197 { 198 uint64_t timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 199 200 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, 0, BSEC_CONF_POWER_UP_MASK); 201 202 /* 203 * If a timeout is detected, test the condition again to consider 204 * cases where timeout is due to the executing TEE thread rescheduling. 205 */ 206 while (!timeout_elapsed(timeout_ref)) 207 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 208 break; 209 210 if (!(bsec_status() & BSEC_MODE_PWR_MASK)) 211 return TEE_SUCCESS; 212 213 return TEE_ERROR_GENERIC; 214 } 215 216 TEE_Result stm32_bsec_shadow_register(uint32_t otp_id) 217 { 218 TEE_Result result = 0; 219 uint32_t exceptions = 0; 220 uint64_t timeout_ref = 0; 221 bool locked = false; 222 223 /* Check if shadowing of OTP is locked, informative only */ 224 result = stm32_bsec_read_sr_lock(otp_id, &locked); 225 if (result) 226 return result; 227 228 if (locked) 229 DMSG("BSEC shadow warning: OTP locked"); 230 231 exceptions = bsec_lock(); 232 233 result = power_up_safmem(); 234 if (result) 235 return result; 236 237 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_READ); 238 239 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 240 while (!timeout_elapsed(timeout_ref)) 241 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 242 break; 243 244 if (bsec_status() & BSEC_MODE_BUSY_MASK) 245 result = TEE_ERROR_GENERIC; 246 else 247 result = check_no_error(otp_id, true /* check-disturbed */); 248 249 power_down_safmem(); 250 251 bsec_unlock(exceptions); 252 253 return result; 254 } 255 256 TEE_Result stm32_bsec_read_otp(uint32_t *value, uint32_t otp_id) 257 { 258 if (otp_id > otp_max_id()) 259 return TEE_ERROR_BAD_PARAMETERS; 260 261 *value = io_read32(bsec_base() + BSEC_OTP_DATA_OFF + 262 (otp_id * sizeof(uint32_t))); 263 264 return TEE_SUCCESS; 265 } 266 267 TEE_Result stm32_bsec_shadow_read_otp(uint32_t *otp_value, uint32_t otp_id) 268 { 269 TEE_Result result = 0; 270 271 result = stm32_bsec_shadow_register(otp_id); 272 if (result) { 273 EMSG("BSEC %"PRIu32" Shadowing Error %#"PRIx32, otp_id, result); 274 return result; 275 } 276 277 result = stm32_bsec_read_otp(otp_value, otp_id); 278 if (result) 279 EMSG("BSEC %"PRIu32" Read Error %#"PRIx32, otp_id, result); 280 281 return result; 282 } 283 284 TEE_Result stm32_bsec_write_otp(uint32_t value, uint32_t otp_id) 285 { 286 TEE_Result result = 0; 287 uint32_t exceptions = 0; 288 vaddr_t otp_data_base = bsec_base() + BSEC_OTP_DATA_OFF; 289 bool locked = false; 290 291 /* Check if write of OTP is locked, informative only */ 292 result = stm32_bsec_read_sw_lock(otp_id, &locked); 293 if (result) 294 return result; 295 296 if (locked) 297 DMSG("BSEC write warning: OTP locked"); 298 299 exceptions = bsec_lock(); 300 301 io_write32(otp_data_base + (otp_id * sizeof(uint32_t)), value); 302 303 bsec_unlock(exceptions); 304 305 return TEE_SUCCESS; 306 } 307 308 TEE_Result stm32_bsec_program_otp(uint32_t value, uint32_t otp_id) 309 { 310 TEE_Result result = 0; 311 uint32_t exceptions = 0; 312 uint64_t timeout_ref = 0; 313 bool locked = false; 314 315 /* Check if shadowing of OTP is locked, informative only */ 316 result = stm32_bsec_read_sp_lock(otp_id, &locked); 317 if (result) 318 return result; 319 320 if (locked) 321 DMSG("BSEC program warning: OTP locked"); 322 323 if (io_read32(bsec_base() + BSEC_OTP_LOCK_OFF) & BIT(BSEC_LOCK_PROGRAM)) 324 DMSG("BSEC program warning: GPLOCK activated"); 325 326 exceptions = bsec_lock(); 327 328 result = power_up_safmem(); 329 if (result) 330 return result; 331 332 io_write32(bsec_base() + BSEC_OTP_WRDATA_OFF, value); 333 io_write32(bsec_base() + BSEC_OTP_CTRL_OFF, otp_id | BSEC_WRITE); 334 335 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 336 while (!timeout_elapsed(timeout_ref)) 337 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 338 break; 339 340 if (bsec_status() & (BSEC_MODE_BUSY_MASK | BSEC_MODE_PROGFAIL_MASK)) 341 result = TEE_ERROR_GENERIC; 342 else 343 result = check_no_error(otp_id, true /* check-disturbed */); 344 345 power_down_safmem(); 346 347 bsec_unlock(exceptions); 348 349 return result; 350 } 351 352 TEE_Result stm32_bsec_permanent_lock_otp(uint32_t otp_id) 353 { 354 TEE_Result result = 0; 355 uint32_t data = 0; 356 uint32_t addr = 0; 357 uint32_t exceptions = 0; 358 vaddr_t base = bsec_base(); 359 uint64_t timeout_ref; 360 361 if (otp_id > otp_max_id()) 362 return TEE_ERROR_BAD_PARAMETERS; 363 364 if (otp_id < bsec_dev.upper_base) { 365 addr = otp_id >> ADDR_LOWER_OTP_PERLOCK_SHIFT; 366 data = DATA_LOWER_OTP_PERLOCK_BIT << 367 ((otp_id & DATA_LOWER_OTP_PERLOCK_MASK) << 1U); 368 } else { 369 addr = (otp_id >> ADDR_UPPER_OTP_PERLOCK_SHIFT) + 2U; 370 data = DATA_UPPER_OTP_PERLOCK_BIT << 371 (otp_id & DATA_UPPER_OTP_PERLOCK_MASK); 372 } 373 374 exceptions = bsec_lock(); 375 376 result = power_up_safmem(); 377 if (result) 378 return result; 379 380 io_write32(base + BSEC_OTP_WRDATA_OFF, data); 381 io_write32(base + BSEC_OTP_CTRL_OFF, addr | BSEC_WRITE | BSEC_LOCK); 382 383 timeout_ref = timeout_init_us(BSEC_TIMEOUT_US); 384 while (!timeout_elapsed(timeout_ref)) 385 if (!(bsec_status() & BSEC_MODE_BUSY_MASK)) 386 break; 387 388 if (bsec_status() & (BSEC_MODE_BUSY_MASK | BSEC_MODE_PROGFAIL_MASK)) 389 result = TEE_ERROR_BAD_PARAMETERS; 390 else 391 result = check_no_error(otp_id, false /* not-disturbed */); 392 393 power_down_safmem(); 394 395 bsec_unlock(exceptions); 396 397 return result; 398 } 399 400 TEE_Result stm32_bsec_write_debug_conf(uint32_t value) 401 { 402 TEE_Result result = TEE_ERROR_GENERIC; 403 uint32_t masked_val = value & BSEC_DEN_ALL_MSK; 404 uint32_t exceptions = 0; 405 406 exceptions = bsec_lock(); 407 408 io_write32(bsec_base() + BSEC_DEN_OFF, value); 409 410 if ((io_read32(bsec_base() + BSEC_DEN_OFF) ^ masked_val) == 0U) 411 result = TEE_SUCCESS; 412 413 bsec_unlock(exceptions); 414 415 return result; 416 } 417 418 uint32_t stm32_bsec_read_debug_conf(void) 419 { 420 return io_read32(bsec_base() + BSEC_DEN_OFF); 421 } 422 423 static TEE_Result set_bsec_lock(uint32_t otp_id, size_t lock_offset) 424 { 425 uint32_t bank = otp_bank_offset(otp_id); 426 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 427 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 428 uint32_t exceptions = 0; 429 430 if (otp_id > STM32MP1_OTP_MAX_ID) 431 return TEE_ERROR_BAD_PARAMETERS; 432 433 exceptions = bsec_lock(); 434 435 io_write32(lock_addr, otp_mask); 436 437 bsec_unlock(exceptions); 438 439 return TEE_SUCCESS; 440 } 441 442 TEE_Result stm32_bsec_set_sr_lock(uint32_t otp_id) 443 { 444 return set_bsec_lock(otp_id, BSEC_SRLOCK_OFF); 445 } 446 447 TEE_Result stm32_bsec_set_sw_lock(uint32_t otp_id) 448 { 449 return set_bsec_lock(otp_id, BSEC_SWLOCK_OFF); 450 } 451 452 TEE_Result stm32_bsec_set_sp_lock(uint32_t otp_id) 453 { 454 return set_bsec_lock(otp_id, BSEC_SPLOCK_OFF); 455 } 456 457 static TEE_Result read_bsec_lock(uint32_t otp_id, bool *locked, 458 size_t lock_offset) 459 { 460 uint32_t bank = otp_bank_offset(otp_id); 461 uint32_t otp_mask = BIT(otp_id & BSEC_OTP_MASK); 462 vaddr_t lock_addr = bsec_base() + bank + lock_offset; 463 464 if (otp_id > STM32MP1_OTP_MAX_ID) 465 return TEE_ERROR_BAD_PARAMETERS; 466 467 *locked = (io_read32(lock_addr) & otp_mask) != 0; 468 469 return TEE_SUCCESS; 470 } 471 472 TEE_Result stm32_bsec_read_sr_lock(uint32_t otp_id, bool *locked) 473 { 474 return read_bsec_lock(otp_id, locked, BSEC_SRLOCK_OFF); 475 } 476 477 TEE_Result stm32_bsec_read_sw_lock(uint32_t otp_id, bool *locked) 478 { 479 return read_bsec_lock(otp_id, locked, BSEC_SWLOCK_OFF); 480 } 481 482 TEE_Result stm32_bsec_read_sp_lock(uint32_t otp_id, bool *locked) 483 { 484 return read_bsec_lock(otp_id, locked, BSEC_SPLOCK_OFF); 485 } 486 487 TEE_Result stm32_bsec_read_permanent_lock(uint32_t otp_id, bool *locked) 488 { 489 return read_bsec_lock(otp_id, locked, BSEC_WRLOCK_OFF); 490 } 491 492 TEE_Result stm32_bsec_otp_lock(uint32_t service) 493 { 494 vaddr_t addr = bsec_base() + BSEC_OTP_LOCK_OFF; 495 496 switch (service) { 497 case BSEC_LOCK_UPPER_OTP: 498 io_write32(addr, BIT(BSEC_LOCK_UPPER_OTP)); 499 break; 500 case BSEC_LOCK_DEBUG: 501 io_write32(addr, BIT(BSEC_LOCK_DEBUG)); 502 break; 503 case BSEC_LOCK_PROGRAM: 504 io_write32(addr, BIT(BSEC_LOCK_PROGRAM)); 505 break; 506 default: 507 return TEE_ERROR_BAD_PARAMETERS; 508 } 509 510 return TEE_SUCCESS; 511 } 512 513 bool stm32_bsec_nsec_can_access_otp(uint32_t otp_id) 514 { 515 if (otp_id > otp_max_id()) 516 return false; 517 518 return otp_id < bsec_dev.upper_base || !bsec_dev.closed_device; 519 } 520 521 static TEE_Result initialize_bsec(void) 522 { 523 struct stm32_bsec_static_cfg cfg = { 0 }; 524 uint32_t otp = 0; 525 TEE_Result result = 0; 526 527 stm32mp_get_bsec_static_cfg(&cfg); 528 529 bsec_dev.base.pa = cfg.base; 530 bsec_dev.upper_base = cfg.upper_start; 531 bsec_dev.max_id = cfg.max_id; 532 bsec_dev.closed_device = true; 533 534 /* Disable closed device mode upon platform closed device OTP value */ 535 result = stm32_bsec_shadow_read_otp(&otp, cfg.closed_device_id); 536 if (!result && !(otp & BIT(cfg.closed_device_position))) 537 bsec_dev.closed_device = false; 538 539 return TEE_SUCCESS; 540 } 541 542 driver_init(initialize_bsec); 543