1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <compiler.h> 29 #include <console.h> 30 #include <drivers/serial8250_uart.h> 31 #include <io.h> 32 #include <keep.h> 33 #include <util.h> 34 35 /* uart register defines */ 36 #define UART_RHR 0x0 37 #define UART_THR 0x0 38 #define UART_IER 0x4 39 #define UART_ISR 0x8 40 #define UART_FCR 0x8 41 #define UART_LCR 0xc 42 #define UART_MCR 0x10 43 #define UART_LSR 0x14 44 #define UART_MSR 0x18 45 #define UART_SPR 0x1c 46 47 /* uart status register bits */ 48 #define LSR_TEMT 0x40 /* Transmitter empty */ 49 #define LSR_THRE 0x20 /* Transmit-hold-register empty */ 50 #define LSR_EMPTY (LSR_TEMT | LSR_THRE) 51 #define LSR_DR 0x01 /* DATA Ready */ 52 53 static vaddr_t chip_to_base(struct serial_chip *chip) 54 { 55 struct serial8250_uart_data *pd = 56 container_of(chip, struct serial8250_uart_data, chip); 57 58 return io_pa_or_va(&pd->base); 59 } 60 61 static void serial8250_uart_flush(struct serial_chip *chip) 62 { 63 vaddr_t base = chip_to_base(chip); 64 65 while (1) { 66 uint32_t state = read32(base + UART_LSR); 67 68 /* Wait until transmit FIFO is empty */ 69 if ((state & LSR_EMPTY) == LSR_EMPTY) 70 break; 71 } 72 } 73 74 static bool serial8250_uart_have_rx_data(struct serial_chip *chip) 75 { 76 vaddr_t base = chip_to_base(chip); 77 78 return (read32(base + UART_LSR) & LSR_DR); 79 } 80 81 static int serial8250_uart_getchar(struct serial_chip *chip) 82 { 83 vaddr_t base = chip_to_base(chip); 84 85 while (!serial8250_uart_have_rx_data(chip)) { 86 /* Transmit FIFO is empty, waiting again */ 87 ; 88 } 89 return read32(base + UART_RHR) & 0xff; 90 } 91 92 static void serial8250_uart_putc(struct serial_chip *chip, int ch) 93 { 94 vaddr_t base = chip_to_base(chip); 95 96 serial8250_uart_flush(chip); 97 98 /* Write out character to transmit FIFO */ 99 write32(ch, base + UART_THR); 100 } 101 102 static const struct serial_ops serial8250_uart_ops = { 103 .flush = serial8250_uart_flush, 104 .getchar = serial8250_uart_getchar, 105 .have_rx_data = serial8250_uart_have_rx_data, 106 .putc = serial8250_uart_putc, 107 }; 108 KEEP_PAGER(serial8250_uart_ops); 109 110 void serial8250_uart_init(struct serial8250_uart_data *pd, paddr_t base, 111 uint32_t __unused uart_clk, 112 uint32_t __unused baud_rate) 113 114 { 115 pd->base.pa = base; 116 pd->chip.ops = &serial8250_uart_ops; 117 118 /* 119 * do nothing, debug uart(uart0) share with normal world, 120 * everything for uart0 is ready now. 121 */ 122 } 123