1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7 #ifndef SCMI_MSG_CLOCK_H 8 #define SCMI_MSG_CLOCK_H 9 10 #include <stdint.h> 11 #include <util.h> 12 13 #define SCMI_PROTOCOL_VERSION_CLOCK 0x20000 14 15 /* 16 * Identifiers of the SCMI Clock Management Protocol commands 17 */ 18 enum scmi_clock_command_id { 19 SCMI_CLOCK_ATTRIBUTES = 0x003, 20 SCMI_CLOCK_DESCRIBE_RATES = 0x004, 21 SCMI_CLOCK_RATE_SET = 0x005, 22 SCMI_CLOCK_RATE_GET = 0x006, 23 SCMI_CLOCK_CONFIG_SET = 0x007, 24 }; 25 26 /* Protocol attributes */ 27 #define SCMI_CLOCK_CLOCK_COUNT_MASK GENMASK_32(15, 0) 28 #define SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK GENMASK_32(23, 16) 29 30 #define SCMI_CLOCK_PROTOCOL_ATTRIBUTES(_max_pending, _clk_count) \ 31 ((((_max_pending) << 16) & SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK) | \ 32 (((_clk_count) & SCMI_CLOCK_CLOCK_COUNT_MASK))) 33 34 struct scmi_clock_attributes_a2p { 35 uint32_t clock_id; 36 }; 37 38 #define SCMI_CLOCK_NAME_LENGTH_MAX 16 39 40 struct scmi_clock_attributes_p2a { 41 int32_t status; 42 uint32_t attributes; 43 char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX]; 44 }; 45 46 /* 47 * Clock Rate Get 48 */ 49 50 struct scmi_clock_rate_get_a2p { 51 uint32_t clock_id; 52 }; 53 54 struct scmi_clock_rate_get_p2a { 55 int32_t status; 56 uint32_t rate[2]; 57 }; 58 59 /* 60 * Clock Rate Set 61 */ 62 63 /* If set, set the new clock rate asynchronously */ 64 #define SCMI_CLOCK_RATE_SET_ASYNC_POS 0 65 /* If set, do not send a delayed asynchronous response */ 66 #define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS 1 67 /* Round up, if set, otherwise round down */ 68 #define SCMI_CLOCK_RATE_SET_ROUND_UP_POS 2 69 /* If set, the platform chooses the appropriate rounding mode */ 70 #define SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS 3 71 72 #define SCMI_CLOCK_RATE_SET_ASYNC_MASK \ 73 BIT(SCMI_CLOCK_RATE_SET_ASYNC_POS) 74 #define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_MASK \ 75 BIT(SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS) 76 #define SCMI_CLOCK_RATE_SET_ROUND_UP_MASK \ 77 BIT(SCMI_CLOCK_RATE_SET_ROUND_UP_POS) 78 #define SCMI_CLOCK_RATE_SET_ROUND_AUTO_MASK \ 79 BIT(SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS) 80 81 struct scmi_clock_rate_set_a2p { 82 uint32_t flags; 83 uint32_t clock_id; 84 uint32_t rate[2]; 85 }; 86 87 struct scmi_clock_rate_set_p2a { 88 int32_t status; 89 }; 90 91 /* 92 * Clock Config Set 93 */ 94 95 #define SCMI_CLOCK_CONFIG_SET_ENABLE_POS 0 96 97 #define SCMI_CLOCK_CONFIG_SET_ENABLE_MASK \ 98 (0x1 << SCMI_CLOCK_CONFIG_SET_ENABLE_POS) 99 100 struct scmi_clock_config_set_a2p { 101 uint32_t clock_id; 102 uint32_t attributes; 103 }; 104 105 struct scmi_clock_config_set_p2a { 106 int32_t status; 107 }; 108 109 /* 110 * Clock Describe Rates 111 */ 112 113 #define SCMI_CLOCK_RATE_FORMAT_RANGE 1 114 #define SCMI_CLOCK_RATE_FORMAT_LIST 0 115 116 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK GENMASK_32(31, 16) 117 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS 16 118 119 #define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK BIT(12) 120 #define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS 12 121 122 #define SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK GENMASK_32(11, 0) 123 124 #define SCMI_CLOCK_DESCRIBE_RATES_NUM_RATES_FLAGS(_count, _fmt, _rem_rates) \ 125 ( \ 126 ((_count) & SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK) | \ 127 (((_rem_rates) << SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS) & \ 128 SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK) | \ 129 (((_fmt) << SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS) & \ 130 SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK) \ 131 ) 132 133 struct scmi_clock_rate { 134 uint32_t low; 135 uint32_t high; 136 }; 137 138 struct scmi_clock_describe_rates_a2p { 139 uint32_t clock_id; 140 uint32_t rate_index; 141 }; 142 143 struct scmi_clock_describe_rates_p2a { 144 int32_t status; 145 uint32_t num_rates_flags; 146 struct scmi_clock_rate rates[]; 147 }; 148 149 #endif /* SCMI_MSG_CLOCK_H */ 150