1 /* 2 * Copyright (c) 2016, GlobalLogic 3 * Copyright (c) 2017, Linaro Limited 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 #include <drivers/scif.h> 29 #include <io.h> 30 #include <keep.h> 31 #include <util.h> 32 33 #define SCIF_SCSCR (0x08) 34 #define SCIF_SCFSR (0x10) 35 #define SCIF_SCFTDR (0x0C) 36 #define SCIF_SCFCR (0x18) 37 #define SCIF_SCFDR (0x1C) 38 39 #define SCSCR_TE BIT(5) 40 #define SCFSR_TDFE BIT(5) 41 #define SCFSR_TEND BIT(6) 42 43 #define SCFDR_T_SHIFT 8 44 45 #define SCIF_TX_FIFO_SIZE 16 46 47 static vaddr_t chip_to_base(struct serial_chip *chip) 48 { 49 struct scif_uart_data *pd = 50 container_of(chip, struct scif_uart_data, chip); 51 52 return io_pa_or_va(&pd->base); 53 } 54 55 static void scif_uart_flush(struct serial_chip *chip) 56 { 57 vaddr_t base = chip_to_base(chip); 58 59 while (!(read16(base + SCIF_SCFSR) & SCFSR_TEND)) 60 ; 61 } 62 63 static void scif_uart_putc(struct serial_chip *chip, int ch) 64 { 65 vaddr_t base = chip_to_base(chip); 66 67 /* Wait until there is space in the FIFO */ 68 while ((read16(base + SCIF_SCFDR) >> SCFDR_T_SHIFT) >= 69 SCIF_TX_FIFO_SIZE) 70 ; 71 write8(ch, base + SCIF_SCFTDR); 72 write16(read16(base + SCIF_SCFSR) & ~(SCFSR_TEND | SCFSR_TDFE), 73 base + SCIF_SCFSR); 74 } 75 76 static const struct serial_ops scif_uart_ops = { 77 .flush = scif_uart_flush, 78 .putc = scif_uart_putc, 79 }; 80 KEEP_PAGER(scif_uart_ops); 81 82 void scif_uart_init(struct scif_uart_data *pd, paddr_t base) 83 { 84 pd->base.pa = base; 85 pd->chip.ops = &scif_uart_ops; 86 87 /* Set Transmit Enable in Control register */ 88 write16(read16(base + SCIF_SCSCR) | SCSCR_TE, base + SCIF_SCSCR); 89 90 scif_uart_flush(&pd->chip); 91 } 92