1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2024, STMicroelectronics 4 */ 5 6 #include <arm.h> 7 #include <drivers/rstctrl.h> 8 #include <drivers/stm32_shared_io.h> 9 #include <drivers/stm32mp25_rcc.h> 10 #include <drivers/stm32mp_dt_bindings.h> 11 #include <io.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <stm32_util.h> 15 16 #include "stm32_rstctrl.h" 17 18 static TEE_Result stm32_reset_update(struct rstctrl *rstctrl, bool state, 19 unsigned int to_us) 20 { 21 unsigned int id = to_stm32_rstline(rstctrl)->id; 22 const struct stm32_reset_data *data = to_stm32_rstline(rstctrl)->data; 23 const struct stm32_reset_cfg *rst_line = NULL; 24 vaddr_t address = stm32_rcc_base(); 25 uint32_t bit_mask = 0; 26 uint32_t value = 0; 27 28 if (id >= data->nb_lines) 29 return TEE_ERROR_BAD_PARAMETERS; 30 31 rst_line = data->rst_lines[id]; 32 if (!rst_line) 33 return TEE_SUCCESS; 34 35 address += rst_line->offset; 36 bit_mask = BIT(rst_line->bit_index); 37 38 if (!state && rst_line->no_deassert) 39 return TEE_SUCCESS; 40 41 state = rst_line->inverted ^ state; 42 43 if (state) { 44 if (rst_line->set_clr) 45 io_write32(address, bit_mask); 46 else 47 io_setbits32_stm32shregs(address, bit_mask); 48 } else { 49 if (rst_line->set_clr) 50 io_write32(address + RCC_MP_ENCLRR_OFFSET, bit_mask); 51 else 52 io_clrbits32_stm32shregs(address, bit_mask); 53 } 54 55 if (to_us && !rst_line->no_timeout) { 56 if (IO_READ32_POLL_TIMEOUT(address, value, 57 ((value & bit_mask) == bit_mask) == 58 state, 0, to_us)) 59 return TEE_ERROR_GENERIC; 60 } else { 61 /* Make sure the above write is performed */ 62 dsb(); 63 } 64 65 return TEE_SUCCESS; 66 } 67 68 static TEE_Result stm32_reset_assert(struct rstctrl *rstctrl, 69 unsigned int to_us) 70 { 71 return stm32_reset_update(rstctrl, true, to_us); 72 } 73 74 static TEE_Result stm32_reset_deassert(struct rstctrl *rstctrl, 75 unsigned int to_us) 76 { 77 return stm32_reset_update(rstctrl, false, to_us); 78 } 79 80 static const struct rstctrl_ops stm32_rstctrl_ops = { 81 .assert_level = stm32_reset_assert, 82 .deassert_level = stm32_reset_deassert, 83 }; 84 85 #define STM32_RESET(id, _offset, _bit_index, _set_clr, _inverted, _no_deassert,\ 86 _no_timeout)\ 87 [(id)] = &(struct stm32_reset_cfg){\ 88 .offset = (_offset),\ 89 .bit_index = (_bit_index),\ 90 .set_clr = (_set_clr),\ 91 .inverted = (_inverted),\ 92 .no_deassert = (_no_deassert),\ 93 .no_timeout = (_no_timeout),\ 94 } 95 96 #define RST(id, _offset, _bit_index)\ 97 STM32_RESET((id), (_offset), (_bit_index), false, false, false, false) 98 99 #define RST_SETR(id, _offset, _bit_index)\ 100 STM32_RESET((id), (_offset), (_bit_index), true, false, false, false) 101 102 #define RST_INV(id, _offset, _bit_index)\ 103 STM32_RESET((id), (_offset), (_bit_index), false, true, false, false) 104 105 #define RST_SETR_NO_DEASSERT(id, _offset, _bit_index)\ 106 STM32_RESET((id), (_offset), (_bit_index), false, false, true, false) 107 108 #define RST_SETR_NO_DEASSERT_TIMEOUT(id, _offset, _bit_index)\ 109 STM32_RESET((id), (_offset), (_bit_index), false, false, true, true) 110 111 static 112 const struct stm32_reset_cfg *stm32mp25_reset_cfg[STM32MP25_LAST_RESET] = { 113 RST(TIM1_R, RCC_TIM1CFGR, 0), 114 RST(TIM2_R, RCC_TIM2CFGR, 0), 115 RST(TIM3_R, RCC_TIM3CFGR, 0), 116 RST(TIM4_R, RCC_TIM4CFGR, 0), 117 RST(TIM5_R, RCC_TIM5CFGR, 0), 118 RST(TIM6_R, RCC_TIM6CFGR, 0), 119 RST(TIM7_R, RCC_TIM7CFGR, 0), 120 RST(TIM8_R, RCC_TIM8CFGR, 0), 121 RST(TIM10_R, RCC_TIM10CFGR, 0), 122 RST(TIM11_R, RCC_TIM11CFGR, 0), 123 RST(TIM12_R, RCC_TIM12CFGR, 0), 124 RST(TIM13_R, RCC_TIM13CFGR, 0), 125 RST(TIM14_R, RCC_TIM14CFGR, 0), 126 RST(TIM15_R, RCC_TIM15CFGR, 0), 127 RST(TIM16_R, RCC_TIM16CFGR, 0), 128 RST(TIM17_R, RCC_TIM17CFGR, 0), 129 RST(TIM20_R, RCC_TIM20CFGR, 0), 130 RST(LPTIM1_R, RCC_LPTIM1CFGR, 0), 131 RST(LPTIM2_R, RCC_LPTIM2CFGR, 0), 132 RST(LPTIM3_R, RCC_LPTIM3CFGR, 0), 133 RST(LPTIM4_R, RCC_LPTIM4CFGR, 0), 134 RST(LPTIM5_R, RCC_LPTIM5CFGR, 0), 135 RST(SPI1_R, RCC_SPI1CFGR, 0), 136 RST(SPI2_R, RCC_SPI2CFGR, 0), 137 RST(SPI3_R, RCC_SPI3CFGR, 0), 138 RST(SPI4_R, RCC_SPI4CFGR, 0), 139 RST(SPI5_R, RCC_SPI5CFGR, 0), 140 RST(SPI6_R, RCC_SPI6CFGR, 0), 141 RST(SPI7_R, RCC_SPI7CFGR, 0), 142 RST(SPI8_R, RCC_SPI8CFGR, 0), 143 RST(SPDIFRX_R, RCC_SPDIFRXCFGR, 0), 144 RST(USART1_R, RCC_USART1CFGR, 0), 145 RST(USART2_R, RCC_USART2CFGR, 0), 146 RST(USART3_R, RCC_USART3CFGR, 0), 147 RST(UART4_R, RCC_UART4CFGR, 0), 148 RST(UART5_R, RCC_UART5CFGR, 0), 149 RST(USART6_R, RCC_USART6CFGR, 0), 150 RST(UART7_R, RCC_UART7CFGR, 0), 151 RST(UART8_R, RCC_UART8CFGR, 0), 152 RST(UART9_R, RCC_UART9CFGR, 0), 153 RST(LPUART1_R, RCC_LPUART1CFGR, 0), 154 RST(IS2M_R, RCC_IS2MCFGR, 0), 155 RST(I2C1_R, RCC_I2C1CFGR, 0), 156 RST(I2C2_R, RCC_I2C2CFGR, 0), 157 RST(I2C3_R, RCC_I2C3CFGR, 0), 158 RST(I2C4_R, RCC_I2C4CFGR, 0), 159 RST(I2C5_R, RCC_I2C5CFGR, 0), 160 RST(I2C6_R, RCC_I2C6CFGR, 0), 161 RST(I2C7_R, RCC_I2C7CFGR, 0), 162 RST(I2C8_R, RCC_I2C8CFGR, 0), 163 RST(SAI1_R, RCC_SAI1CFGR, 0), 164 RST(SAI2_R, RCC_SAI2CFGR, 0), 165 RST(SAI3_R, RCC_SAI3CFGR, 0), 166 RST(SAI4_R, RCC_SAI4CFGR, 0), 167 RST(MDF1_R, RCC_MDF1CFGR, 0), 168 RST(MDF2_R, RCC_ADF1CFGR, 0), 169 RST(FDCAN_R, RCC_FDCANCFGR, 0), 170 RST(HDP_R, RCC_HDPCFGR, 0), 171 RST(ADC12_R, RCC_ADC12CFGR, 0), 172 RST(ADC3_R, RCC_ADC3CFGR, 0), 173 RST(ETH1_R, RCC_ETH1CFGR, 0), 174 RST(ETH2_R, RCC_ETH2CFGR, 0), 175 RST(USB2_R, RCC_USB2CFGR, 0), 176 RST(USB2PHY1_R, RCC_USB2PHY1CFGR, 0), 177 RST(USB2PHY2_R, RCC_USB2PHY2CFGR, 0), 178 RST(USB3DR_R, RCC_USB3DRCFGR, 0), 179 RST(USB3PCIEPHY_R, RCC_USB3PCIEPHYCFGR, 0), 180 RST(USBTC_R, RCC_USBTCCFGR, 0), 181 RST(ETHSW_R, RCC_ETHSWCFGR, 0), 182 RST(SDMMC1_R, RCC_SDMMC1CFGR, 0), 183 RST(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16), 184 RST(SDMMC2_R, RCC_SDMMC2CFGR, 0), 185 RST(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16), 186 RST(SDMMC3_R, RCC_SDMMC3CFGR, 0), 187 RST(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16), 188 RST(GPU_R, RCC_GPUCFGR, 0), 189 RST(LTDC_R, RCC_LTDCCFGR, 0), 190 RST(DSI_R, RCC_DSICFGR, 0), 191 RST(LVDS_R, RCC_LVDSCFGR, 0), 192 RST(CSI_R, RCC_CSICFGR, 0), 193 RST(DCMIPP_R, RCC_DCMIPPCFGR, 0), 194 RST(CCI_R, RCC_CCICFGR, 0), 195 RST(VDEC_R, RCC_VDECCFGR, 0), 196 RST(VENC_R, RCC_VENCCFGR, 0), 197 RST(WWDG1_R, RCC_WWDG1CFGR, 0), 198 RST(WWDG2_R, RCC_WWDG2CFGR, 0), 199 RST(VREF_R, RCC_VREFCFGR, 0), 200 RST(DTS_R, RCC_DTSCFGR, 0), 201 RST(CRC_R, RCC_CRCCFGR, 0), 202 RST(SERC_R, RCC_SERCCFGR, 0), 203 RST(OSPIIOM_R, RCC_OSPIIOMCFGR, 0), 204 RST(I3C1_R, RCC_I3C1CFGR, 0), 205 RST(I3C2_R, RCC_I3C2CFGR, 0), 206 RST(I3C3_R, RCC_I3C3CFGR, 0), 207 RST(I3C4_R, RCC_I3C4CFGR, 0), 208 RST(RNG_R, RCC_RNGCFGR, 0), 209 RST(PKA_R, RCC_PKACFGR, 0), 210 RST(SAES_R, RCC_SAESCFGR, 0), 211 RST(HASH_R, RCC_HASHCFGR, 0), 212 RST(CRYP1_R, RCC_CRYP1CFGR, 0), 213 RST(CRYP2_R, RCC_CRYP2CFGR, 0), 214 RST(PCIE_R, RCC_PCIECFGR, 0), 215 RST(OSPI1_R, RCC_OSPI1CFGR, 0), 216 RST(OSPI1DLL_R, RCC_OSPI1CFGR, 16), 217 RST(OSPI2_R, RCC_OSPI2CFGR, 0), 218 RST(OSPI2DLL_R, RCC_OSPI2CFGR, 16), 219 RST(DBG_R, RCC_DBGCFGR, 12), 220 221 RST_SETR(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18), 222 RST_SETR(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18), 223 RST_SETR(IWDG1_SYS_R, RCC_IWDGC1CFGSETR, 0), 224 RST_SETR(IWDG2_SYS_R, RCC_IWDGC1CFGSETR, 2), 225 RST_SETR(IWDG3_SYS_R, RCC_IWDGC2CFGSETR, 0), 226 RST_SETR(IWDG4_SYS_R, RCC_IWDGC2CFGSETR, 2), 227 228 RST_INV(C2_HOLDBOOT_R, RCC_CPUBOOTCR, 0), 229 RST_INV(C1_HOLDBOOT_R, RCC_CPUBOOTCR, 1), 230 231 RST_SETR_NO_DEASSERT_TIMEOUT(C1_R, RCC_C1RSTCSETR, 0), 232 RST_SETR_NO_DEASSERT_TIMEOUT(C1P1POR_R, RCC_C1P1RSTCSETR, 0), 233 RST_SETR_NO_DEASSERT_TIMEOUT(C1P1_R, RCC_C1P1RSTCSETR, 1), 234 RST_SETR_NO_DEASSERT_TIMEOUT(C2_R, RCC_C2RSTCSETR, 0), 235 RST_SETR_NO_DEASSERT_TIMEOUT(SYS_R, RCC_GRSTCSETR, 0), 236 237 /* 238 * Don't manage reset lines of RIF aware resources 239 * DDRCP_R, DDRCAPB_R, DDRPHYCAPB_R, DDRCFG_R, DDR_R, 240 * IPCC1_R, IPCC2_R, 241 * HPDMA1_R, HPDMA2_R, HPDMA3_R, LPDMA_R, 242 * GPIOA_R, GPIOB_R, GPIOC_R, GPIOD_R, 243 * GPIOE_R, GPIOF_R, GPIOG_R, GPIOH_R, 244 * GPIOI_R, GPIOJ_R, GPIOK_R, GPIOZ_R, 245 * HSEM_R, 246 * FMC_R, 247 */ 248 }; 249 250 static const struct rstctrl_ops *stm32_reset_get_ops(unsigned int id __unused) 251 { 252 return &stm32_rstctrl_ops; 253 } 254 255 static const struct stm32_reset_data stm32mp25_reset_data = { 256 .nb_lines = ARRAY_SIZE(stm32mp25_reset_cfg), 257 .rst_lines = stm32mp25_reset_cfg, 258 .get_rstctrl_ops = stm32_reset_get_ops, 259 }; 260 261 static const struct dt_device_match stm32_rstctrl_match_table[] = { 262 { 263 .compatible = "st,stm32mp25-rcc", 264 .compat_data = &stm32mp25_reset_data, 265 }, 266 { } 267 }; 268 269 DEFINE_DT_DRIVER(stm32_rstctrl_dt_driver) = { 270 .name = "stm32_rstctrl", 271 .type = DT_DRIVER_RSTCTRL, 272 .match_table = stm32_rstctrl_match_table, 273 .probe = stm32_rstctrl_provider_probe, 274 }; 275