1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2022, Linaro Limited 4 * Copyright (c) 2018-2022, STMicroelectronics 5 */ 6 7 #include <drivers/rstctrl.h> 8 #include <drivers/stm32mp1_rcc.h> 9 #include <dt-bindings/reset/stm32mp1-resets.h> 10 #include <io.h> 11 #include <kernel/delay.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <kernel/panic.h> 15 #include <mm/core_memprot.h> 16 #include <stm32_util.h> 17 18 #define RESET_ID_MASK GENMASK_32(31, 5) 19 #define RESET_ID_SHIFT 5 20 #define RESET_BIT_POS_MASK GENMASK_32(4, 0) 21 #define RESET_OFFSET_MAX 1024 22 23 /* Exposed rstctrl instance */ 24 struct stm32_rstline { 25 unsigned int id; 26 struct rstctrl rstctrl; 27 SLIST_ENTRY(stm32_rstline) link; 28 }; 29 30 static SLIST_HEAD(, stm32_rstline) stm32_rst_list = 31 SLIST_HEAD_INITIALIZER(stm32_rst_list); 32 33 static size_t reset_id2reg_offset(unsigned int id) 34 { 35 size_t offset = (id & RESET_ID_MASK) >> RESET_ID_SHIFT; 36 37 assert(offset < RESET_OFFSET_MAX); 38 return offset * sizeof(uint32_t); 39 } 40 41 static uint8_t reset_id2reg_bit_pos(unsigned int reset_id) 42 { 43 uint8_t pos = reset_id & RESET_BIT_POS_MASK; 44 45 assert(pos < 32); 46 return pos; 47 } 48 49 static struct stm32_rstline *to_rstline(struct rstctrl *rstctrl) 50 { 51 assert(rstctrl); 52 53 return container_of(rstctrl, struct stm32_rstline, rstctrl); 54 } 55 56 static TEE_Result reset_assert(struct rstctrl *rstctrl, unsigned int to_us) 57 { 58 unsigned int id = to_rstline(rstctrl)->id; 59 vaddr_t rcc_base = stm32_rcc_base(); 60 uint32_t bit_mask = 0; 61 size_t offset = 0; 62 63 switch (id) { 64 case MCU_HOLD_BOOT_R: 65 /* 66 * The RCC_MP_GCR is a read/write register. 67 * Assert the MCU HOLD_BOOT means clear the BOOT_MCU bit 68 */ 69 io_clrbits32(rcc_base + RCC_MP_GCR, RCC_MP_GCR_BOOT_MCU); 70 71 return TEE_SUCCESS; 72 case MCU_R: 73 /* MCU reset can only be written */ 74 to_us = 0; 75 break; 76 default: 77 break; 78 } 79 80 offset = reset_id2reg_offset(id); 81 bit_mask = BIT(reset_id2reg_bit_pos(id)); 82 83 io_write32(rcc_base + offset, bit_mask); 84 85 if (to_us) { 86 uint64_t timeout_ref = timeout_init_us(to_us); 87 88 while (!(io_read32(rcc_base + offset) & bit_mask)) 89 if (timeout_elapsed(timeout_ref)) 90 break; 91 92 if (!(io_read32(rcc_base + offset) & bit_mask)) 93 return TEE_ERROR_SECURITY; 94 } 95 96 return TEE_SUCCESS; 97 } 98 99 static TEE_Result reset_deassert(struct rstctrl *rstctrl, unsigned int to_us) 100 { 101 unsigned int id = to_rstline(rstctrl)->id; 102 vaddr_t rcc_base = stm32_rcc_base(); 103 uint32_t bit_mask = 0; 104 size_t offset = 0; 105 106 switch (id) { 107 case MCU_HOLD_BOOT_R: 108 /* 109 * The RCC_MP_GCR is a read/write register. 110 * Deassert the MCU HOLD_BOOT means set the BOOT_MCU the bit 111 */ 112 io_setbits32(rcc_base + RCC_MP_GCR, RCC_MP_GCR_BOOT_MCU); 113 114 return TEE_SUCCESS; 115 case MCU_R: 116 /* MCU reset deasserts by its own */ 117 return TEE_SUCCESS; 118 default: 119 break; 120 } 121 122 offset = reset_id2reg_offset(id) + RCC_MP_RSTCLRR_OFFSET; 123 bit_mask = BIT(reset_id2reg_bit_pos(id)); 124 125 io_write32(rcc_base + offset, bit_mask); 126 127 if (to_us) { 128 uint64_t timeout_ref = timeout_init_us(to_us); 129 130 while ((io_read32(rcc_base + offset) & bit_mask)) 131 if (timeout_elapsed(timeout_ref)) 132 break; 133 134 if (io_read32(rcc_base + offset) & bit_mask) 135 return TEE_ERROR_SECURITY; 136 } 137 138 return TEE_SUCCESS; 139 } 140 141 static struct rstctrl_ops stm32_rstctrl_ops = { 142 .assert_level = reset_assert, 143 .deassert_level = reset_deassert, 144 }; 145 146 static struct stm32_rstline *find_rstctrl_device(unsigned int control_id) 147 { 148 struct stm32_rstline *stm32_rstline = NULL; 149 150 SLIST_FOREACH(stm32_rstline, &stm32_rst_list, link) 151 if (stm32_rstline->id == control_id) 152 break; 153 154 return stm32_rstline; 155 } 156 157 static struct stm32_rstline *find_or_allocate_rstline(unsigned int binding_id) 158 { 159 struct stm32_rstline *stm32_rstline = find_rstctrl_device(binding_id); 160 161 if (stm32_rstline) 162 return stm32_rstline; 163 164 stm32_rstline = calloc(1, sizeof(*stm32_rstline)); 165 if (stm32_rstline) { 166 stm32_rstline->rstctrl.ops = &stm32_rstctrl_ops; 167 stm32_rstline->id = binding_id; 168 SLIST_INSERT_HEAD(&stm32_rst_list, stm32_rstline, link); 169 } 170 171 return stm32_rstline; 172 } 173 174 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id) 175 { 176 struct stm32_rstline *rstline = find_or_allocate_rstline(binding_id); 177 178 assert(rstline); 179 return &rstline->rstctrl; 180 } 181 182 static struct rstctrl *stm32_rstctrl_get_dev(struct dt_pargs *arg, 183 void *priv_data __unused, 184 TEE_Result *res) 185 { 186 struct stm32_rstline *stm32_rstline = NULL; 187 uintptr_t control_id = 0; 188 189 if (arg->args_count != 1) { 190 *res = TEE_ERROR_BAD_PARAMETERS; 191 return NULL; 192 } 193 control_id = arg->args[0]; 194 195 stm32_rstline = find_or_allocate_rstline(control_id); 196 if (!stm32_rstline) { 197 *res = TEE_ERROR_OUT_OF_MEMORY; 198 return NULL; 199 } 200 201 *res = TEE_SUCCESS; 202 return &stm32_rstline->rstctrl; 203 } 204 205 static TEE_Result stm32_rstctrl_provider_probe(const void *fdt, int offs, 206 const void *compat_data __unused) 207 { 208 struct dt_node_info info = { }; 209 210 assert(rstctrl_ops_is_valid(&stm32_rstctrl_ops)); 211 212 fdt_fill_device_info(fdt, &info, offs); 213 214 assert(info.reg == RCC_BASE && 215 info.reg_size != DT_INFO_INVALID_REG_SIZE); 216 217 return rstctrl_register_provider(fdt, offs, stm32_rstctrl_get_dev, 218 NULL); 219 } 220 221 static const struct dt_device_match stm32_rstctrl_match_table[] = { 222 { .compatible = "st,stm32mp1-rcc" }, 223 { .compatible = "st,stm32mp1-rcc-secure" }, 224 { } 225 }; 226 227 DEFINE_DT_DRIVER(stm32_rstctrl_dt_driver) = { 228 .name = "stm32_rstctrl", 229 .type = DT_DRIVER_RSTCTRL, 230 .match_table = stm32_rstctrl_match_table, 231 .probe = stm32_rstctrl_provider_probe, 232 }; 233