1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2019, 2023 NXP 4 */ 5 6 #include <imx.h> 7 #include <io.h> 8 #include <mm/core_mmu.h> 9 #include <mm/core_memprot.h> 10 11 #include "local.h" 12 13 #define SRC_SCR 0x000 14 #define SRC_A7RCR0 0x004 15 #define SRC_A7RCR1 0x008 16 #if defined(CFG_MX7) 17 #define SRC_GPR1 0x074 18 #else 19 #define SRC_GPR1 0x020 20 #endif 21 22 #define SRC_SCR_CORE1_RST_BIT(_cpu) BIT32(14 + (_cpu) - 1) 23 #define SRC_SCR_CORE1_ENABLE_BIT(_cpu) BIT32(22 + (_cpu) - 1) 24 #define SRC_A7RCR0_A7_CORE_RESET0_BIT(_cpu) BIT32((_cpu) - 1) 25 #define SRC_A7RCR1_A7_CORE1_ENABLE_BIT(_cpu) BIT32(1 + (_cpu) - 1) 26 27 #define ENTRY_OFFSET(_cpu) ((_cpu) * 8) 28 #define ARG_OFFSET(_cpu) (ENTRY_OFFSET(_cpu) + 4) 29 30 register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, SRC_SIZE); 31 32 uint32_t imx_get_src_gpr_arg(unsigned int cpu) 33 { 34 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); 35 36 return io_read32(va + SRC_GPR1 + ARG_OFFSET(cpu)); 37 } 38 39 void imx_set_src_gpr_arg(unsigned int cpu, uint32_t val) 40 { 41 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); 42 43 io_write32(va + SRC_GPR1 + ARG_OFFSET(cpu), val); 44 } 45 46 uint32_t imx_get_src_gpr_entry(unsigned int cpu) 47 { 48 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); 49 50 return io_read32(va + SRC_GPR1 + ENTRY_OFFSET(cpu)); 51 } 52 53 void imx_set_src_gpr_entry(unsigned int cpu, uint32_t val) 54 { 55 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); 56 57 io_write32(va + SRC_GPR1 + ENTRY_OFFSET(cpu), val); 58 } 59 60 void imx_src_release_secondary_core(unsigned int cpu) 61 { 62 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); 63 64 if (soc_is_imx7ds()) 65 io_setbits32(va + SRC_A7RCR1, 66 SRC_A7RCR1_A7_CORE1_ENABLE_BIT(cpu)); 67 else 68 io_setbits32(va + SRC_SCR, SRC_SCR_CORE1_ENABLE_BIT(cpu) | 69 SRC_SCR_CORE1_RST_BIT(cpu)); 70 } 71 72 void imx_src_shutdown_core(unsigned int cpu) 73 { 74 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); 75 76 if (soc_is_imx7ds()) { 77 io_clrbits32(va + SRC_A7RCR1, 78 SRC_A7RCR1_A7_CORE1_ENABLE_BIT(cpu)); 79 } else { 80 uint32_t mask = io_read32(va + SRC_SCR); 81 82 mask &= ~SRC_SCR_CORE1_ENABLE_BIT(cpu); 83 mask |= SRC_SCR_CORE1_RST_BIT(cpu); 84 io_write32(va + SRC_SCR, mask); 85 } 86 } 87