1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <assert.h> 30 #include <drivers/pl022_spi.h> 31 #include <initcall.h> 32 #include <io.h> 33 #include <kernel/panic.h> 34 #include <kernel/tee_time.h> 35 #include <platform_config.h> 36 #include <trace.h> 37 #include <util.h> 38 39 /* SPI register offsets */ 40 #define SSPCR0 0x000 41 #define SSPCR1 0x004 42 #define SSPDR 0x008 43 #define SSPSR 0x00C 44 #define SSPCPSR 0x010 45 #define SSPIMSC 0x014 46 #define SSPRIS 0x018 47 #define SSPMIS 0x01C 48 #define SSPICR 0x020 49 #define SSPDMACR 0x024 50 51 #ifdef PLATFORM_hikey 52 /* HiKey extensions */ 53 #define SSPTXFIFOCR 0x028 54 #define SSPRXFIFOCR 0x02C 55 #define SSPB2BTRANS 0x030 56 #endif 57 58 /* test registers */ 59 #define SSPTCR 0x080 60 #define SSPITIP 0x084 61 #define SSPITOP 0x088 62 #define SSPTDR 0x08C 63 64 #define SSPPeriphID0 0xFE0 65 #define SSPPeriphID1 0xFE4 66 #define SSPPeriphID2 0xFE8 67 #define SSPPeriphID3 0xFEC 68 69 #define SSPPCellID0 0xFF0 70 #define SSPPCellID1 0xFF4 71 #define SSPPCellID2 0xFF8 72 #define SSPPCellID3 0xFFC 73 74 /* SPI register masks */ 75 #define SSPCR0_SCR SHIFT_U32(0xFF, 8) 76 #define SSPCR0_SPH SHIFT_U32(1, 7) 77 #define SSPCR0_SPH1 SHIFT_U32(1, 7) 78 #define SSPCR0_SPH0 SHIFT_U32(0, 7) 79 #define SSPCR0_SPO SHIFT_U32(1, 6) 80 #define SSPCR0_SPO1 SHIFT_U32(1, 6) 81 #define SSPCR0_SPO0 SHIFT_U32(0, 6) 82 #define SSPCR0_FRF SHIFT_U32(3, 4) 83 #define SSPCR0_FRF_SPI SHIFT_U32(0, 4) 84 #define SSPCR0_DSS SHIFT_U32(0xFF, 0) 85 #define SSPCR0_DSS_16BIT SHIFT_U32(0xF, 0) 86 #define SSPCR0_DSS_8BIT SHIFT_U32(7, 0) 87 88 #define SSPCR1_SOD SHIFT_U32(1, 3) 89 #define SSPCR1_SOD_ENABLE SHIFT_U32(1, 3) 90 #define SSPCR1_SOD_DISABLE SHIFT_U32(0, 3) 91 #define SSPCR1_MS SHIFT_U32(1, 2) 92 #define SSPCR1_MS_SLAVE SHIFT_U32(1, 2) 93 #define SSPCR1_MS_MASTER SHIFT_U32(0, 2) 94 #define SSPCR1_SSE SHIFT_U32(1, 1) 95 #define SSPCR1_SSE_ENABLE SHIFT_U32(1, 1) 96 #define SSPCR1_SSE_DISABLE SHIFT_U32(0, 1) 97 #define SSPCR1_LBM SHIFT_U32(1, 0) 98 #define SSPCR1_LBM_YES SHIFT_U32(1, 0) 99 #define SSPCR1_LBM_NO SHIFT_U32(0, 0) 100 101 #define SSPDR_DATA SHIFT_U32(0xFFFF, 0) 102 103 #define SSPSR_BSY SHIFT_U32(1, 4) 104 #define SSPSR_RNF SHIFT_U32(1, 3) 105 #define SSPSR_RNE SHIFT_U32(1, 2) 106 #define SSPSR_TNF SHIFT_U32(1, 1) 107 #define SSPSR_TFE SHIFT_U32(1, 0) 108 109 #define SSPCPSR_CPSDVR SHIFT_U32(0xFF, 0) 110 111 #define SSPIMSC_TXIM SHIFT_U32(1, 3) 112 #define SSPIMSC_RXIM SHIFT_U32(1, 2) 113 #define SSPIMSC_RTIM SHIFT_U32(1, 1) 114 #define SSPIMSC_RORIM SHIFT_U32(1, 0) 115 116 #define SSPRIS_TXRIS SHIFT_U32(1, 3) 117 #define SSPRIS_RXRIS SHIFT_U32(1, 2) 118 #define SSPRIS_RTRIS SHIFT_U32(1, 1) 119 #define SSPRIS_RORRIS SHIFT_U32(1, 0) 120 121 #define SSPMIS_TXMIS SHIFT_U32(1, 3) 122 #define SSPMIS_RXMIS SHIFT_U32(1, 2) 123 #define SSPMIS_RTMIS SHIFT_U32(1, 1) 124 #define SSPMIS_RORMIS SHIFT_U32(1, 0) 125 126 #define SSPICR_RTIC SHIFT_U32(1, 1) 127 #define SSPICR_RORIC SHIFT_U32(1, 0) 128 129 #define SSPDMACR_TXDMAE SHIFT_U32(1, 1) 130 #define SSPDMACR_RXDMAE SHIFT_U32(1, 0) 131 132 #define SSPPeriphID0_PartNumber0 SHIFT_U32(0xFF, 0) /* 0x22 */ 133 #define SSPPeriphID1_Designer0 SHIFT_U32(0xF, 4) /* 0x1 */ 134 #define SSPPeriphID1_PartNumber1 SHIFT_U32(0xF, 0) /* 0x0 */ 135 #define SSPPeriphID2_Revision SHIFT_U32(0xF, 4) 136 #define SSPPeriphID2_Designer1 SHIFT_U32(0xF, 0) /* 0x4 */ 137 #define SSPPeriphID3_Configuration SHIFT_U32(0xFF, 0) /* 0x00 */ 138 139 #define SSPPCellID_0 SHIFT_U32(0xFF, 0) /* 0x0D */ 140 #define SSPPCellID_1 SHIFT_U32(0xFF, 0) /* 0xF0 */ 141 #define SSPPPCellID_2 SHIFT_U32(0xFF, 0) /* 0x05 */ 142 #define SSPPPCellID_3 SHIFT_U32(0xFF, 0) /* 0xB1 */ 143 144 #define MASK_32 0xFFFFFFFF 145 #define MASK_28 0xFFFFFFF 146 #define MASK_24 0xFFFFFF 147 #define MASK_20 0xFFFFF 148 #define MASK_16 0xFFFF 149 #define MASK_12 0xFFF 150 #define MASK_8 0xFF 151 #define MASK_4 0xF 152 /* SPI register masks */ 153 154 #define SSP_CPSDVR_MAX 254 155 #define SSP_CPSDVR_MIN 2 156 #define SSP_SCR_MAX 255 157 #define SSP_SCR_MIN 0 158 #define SSP_DATASIZE_MAX 16 159 160 static enum spi_result pl022_txrx8(struct spi_chip *chip, uint8_t *wdat, 161 uint8_t *rdat, size_t num_pkts) 162 { 163 size_t i = 0; 164 size_t j = 0; 165 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 166 167 168 if (pd->data_size_bits != 8) { 169 EMSG("data_size_bits should be 8, not %u", 170 pd->data_size_bits); 171 return SPI_ERR_CFG; 172 } 173 174 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_LOW); 175 176 if (wdat) 177 while (i < num_pkts) 178 if (read8(pd->base + SSPSR) & SSPSR_TNF) { 179 /* tx 1 packet */ 180 write8(wdat[i++], pd->base + SSPDR); 181 } 182 183 if (rdat) { 184 while ((j < num_pkts) && 185 (read8(pd->base + SSPSR) & SSPSR_BSY)) 186 if (read8(pd->base + SSPSR) & SSPSR_RNE) { 187 /* rx 1 packet */ 188 rdat[j++] = read8(pd->base + SSPDR); 189 } 190 191 if (j < num_pkts) { 192 EMSG("Packets requested %zu, received %zu", 193 num_pkts, j); 194 return SPI_ERR_PKTCNT; 195 } 196 } 197 198 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_HIGH); 199 200 return SPI_OK; 201 } 202 203 static enum spi_result pl022_txrx16(struct spi_chip *chip, uint16_t *wdat, 204 uint16_t *rdat, size_t num_pkts) 205 { 206 size_t i = 0; 207 size_t j = 0; 208 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 209 210 if (pd->data_size_bits != 16) { 211 EMSG("data_size_bits should be 16, not %u", 212 pd->data_size_bits); 213 return SPI_ERR_CFG; 214 } 215 216 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_LOW); 217 218 if (wdat) 219 while (i < num_pkts) 220 if (read8(pd->base + SSPSR) & SSPSR_TNF) { 221 /* tx 1 packet */ 222 write16(wdat[i++], pd->base + SSPDR); 223 } 224 225 if (rdat) { 226 while ((j < num_pkts) && 227 (read8(pd->base + SSPSR) & SSPSR_BSY)) 228 if (read8(pd->base + SSPSR) & SSPSR_RNE) { 229 /* rx 1 packet */ 230 rdat[j++] = read16(pd->base + SSPDR); 231 } 232 233 if (j < num_pkts) { 234 EMSG("Packets requested %zu, received %zu", 235 num_pkts, j); 236 return SPI_ERR_PKTCNT; 237 } 238 } 239 240 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_HIGH); 241 242 return SPI_OK; 243 } 244 245 static void pl022_print_peri_id(struct pl022_data *pd __maybe_unused) 246 { 247 DMSG("Expected: 0x 22 10 ?4 00"); 248 DMSG("Read: 0x %02x %02x %02x %02x", 249 read32(pd->base + SSPPeriphID0), 250 read32(pd->base + SSPPeriphID1), 251 read32(pd->base + SSPPeriphID2), 252 read32(pd->base + SSPPeriphID3)); 253 } 254 255 static void pl022_print_cell_id(struct pl022_data *pd __maybe_unused) 256 { 257 DMSG("Expected: 0x 0d f0 05 b1"); 258 DMSG("Read: 0x %02x %02x %02x %02x", 259 read32(pd->base + SSPPCellID0), 260 read32(pd->base + SSPPCellID1), 261 read32(pd->base + SSPPCellID2), 262 read32(pd->base + SSPPCellID3)); 263 } 264 265 static void pl022_sanity_check(struct pl022_data *pd) 266 { 267 assert(pd); 268 assert(pd->chip.ops); 269 assert(pd->gpio); 270 assert(pd->gpio->ops); 271 assert(pd->base); 272 assert(pd->cs_gpio_base); 273 assert(pd->clk_hz); 274 assert(pd->speed_hz && pd->speed_hz <= pd->clk_hz/2); 275 assert(pd->mode <= SPI_MODE3); 276 assert(pd->data_size_bits == 8 || pd->data_size_bits == 16); 277 278 #ifdef PLATFORM_hikey 279 DMSG("SSPB2BTRANS: Expected: 0x2. Read: 0x%x", 280 read32(pd->base + SSPB2BTRANS)); 281 #endif 282 pl022_print_peri_id(pd); 283 pl022_print_cell_id(pd); 284 } 285 286 static inline uint32_t pl022_calc_freq(struct pl022_data *pd, 287 uint8_t cpsdvr, uint8_t scr) 288 { 289 return pd->clk_hz / (cpsdvr * (1 + scr)); 290 } 291 292 static void pl022_calc_clk_divisors(struct pl022_data *pd, 293 uint8_t *cpsdvr, uint8_t *scr) 294 { 295 unsigned int freq1 = 0; 296 unsigned int freq2 = 0; 297 uint8_t tmp_cpsdvr1; 298 uint8_t tmp_scr1; 299 uint8_t tmp_cpsdvr2 = 0; 300 uint8_t tmp_scr2 = 0; 301 302 for (tmp_scr1 = SSP_SCR_MIN; tmp_scr1 < SSP_SCR_MAX; tmp_scr1++) { 303 for (tmp_cpsdvr1 = SSP_CPSDVR_MIN; tmp_cpsdvr1 < SSP_CPSDVR_MAX; 304 tmp_cpsdvr1++) { 305 freq1 = pl022_calc_freq(pd, tmp_cpsdvr1, tmp_scr1); 306 if (freq1 == pd->speed_hz) 307 goto done; 308 else if (freq1 < pd->speed_hz) 309 goto stage2; 310 } 311 } 312 313 stage2: 314 for (tmp_cpsdvr2 = SSP_CPSDVR_MIN; tmp_cpsdvr2 < SSP_CPSDVR_MAX; 315 tmp_cpsdvr2++) { 316 for (tmp_scr2 = SSP_SCR_MIN; tmp_scr2 < SSP_SCR_MAX; 317 tmp_scr2++) { 318 freq2 = pl022_calc_freq(pd, tmp_cpsdvr2, tmp_scr2); 319 if (freq2 <= pd->speed_hz) 320 goto done; 321 } 322 } 323 324 done: 325 if (freq1 >= freq2) { 326 *cpsdvr = tmp_cpsdvr1; 327 *scr = tmp_scr1; 328 DMSG("speed: requested: %u, closest1: %u", 329 pd->speed_hz, freq1); 330 } else { 331 *cpsdvr = tmp_cpsdvr2; 332 *scr = tmp_scr2; 333 DMSG("speed: requested: %u, closest2: %u", 334 pd->speed_hz, freq2); 335 } 336 DMSG("CPSDVR: %u (0x%x), SCR: %u (0x%x)", 337 *cpsdvr, *cpsdvr, *scr, *scr); 338 } 339 340 static void pl022_flush_fifo(struct pl022_data *pd) 341 { 342 uint32_t __maybe_unused rdat; 343 344 do { 345 while (read32(pd->base + SSPSR) & SSPSR_RNE) { 346 rdat = read32(pd->base + SSPDR); 347 DMSG("rdat: 0x%x", rdat); 348 } 349 } while (read32(pd->base + SSPSR) & SSPSR_BSY); 350 } 351 352 static const struct spi_ops pl022_ops = { 353 .txrx8 = pl022_txrx8, 354 .txrx16 = pl022_txrx16, 355 }; 356 357 void pl022_configure(struct pl022_data *pd) 358 { 359 uint16_t mode; 360 uint16_t data_size; 361 uint8_t cpsdvr; 362 uint8_t scr; 363 uint8_t lbm; 364 365 pd->chip.ops = &pl022_ops; 366 pl022_sanity_check(pd); 367 pl022_calc_clk_divisors(pd, &cpsdvr, &scr); 368 369 /* configure ssp based on platform settings */ 370 switch (pd->mode) { 371 case SPI_MODE0: 372 DMSG("SPI mode 0"); 373 mode = SSPCR0_SPO0 | SSPCR0_SPH0; 374 break; 375 case SPI_MODE1: 376 DMSG("SPI mode 1"); 377 mode = SSPCR0_SPO0 | SSPCR0_SPH1; 378 break; 379 case SPI_MODE2: 380 DMSG("SPI mode 2"); 381 mode = SSPCR0_SPO1 | SSPCR0_SPH0; 382 break; 383 case SPI_MODE3: 384 DMSG("SPI mode 3"); 385 mode = SSPCR0_SPO1 | SSPCR0_SPH1; 386 break; 387 default: 388 EMSG("Invalid SPI mode: %u", pd->mode); 389 panic(); 390 } 391 392 switch (pd->data_size_bits) { 393 case 8: 394 DMSG("Data size: 8"); 395 data_size = SSPCR0_DSS_8BIT; 396 break; 397 case 16: 398 DMSG("Data size: 16"); 399 data_size = SSPCR0_DSS_16BIT; 400 break; 401 default: 402 EMSG("Unsupported data size: %u bits", pd->data_size_bits); 403 panic(); 404 } 405 406 if (pd->loopback) { 407 DMSG("Starting in loopback mode!"); 408 lbm = SSPCR1_LBM_YES; 409 } else { 410 DMSG("Starting in regular (non-loopback) mode!"); 411 lbm = SSPCR1_LBM_NO; 412 } 413 414 DMSG("set Serial Clock Rate (SCR), SPI mode (phase and clock)"); 415 DMSG("set frame format (SPI) and data size (8- or 16-bit)"); 416 io_mask16(pd->base + SSPCR0, SHIFT_U32(scr, 8) | mode | SSPCR0_FRF_SPI | 417 data_size, MASK_16); 418 419 DMSG("set master mode, disable SSP, set loopback mode"); 420 io_mask8(pd->base + SSPCR1, SSPCR1_SOD_DISABLE | SSPCR1_MS_MASTER | 421 SSPCR1_SSE_DISABLE | lbm, MASK_4); 422 423 DMSG("set clock prescale"); 424 io_mask8(pd->base + SSPCPSR, cpsdvr, SSPCPSR_CPSDVR); 425 426 DMSG("disable interrupts"); 427 io_mask8(pd->base + SSPIMSC, 0, MASK_4); 428 429 DMSG("clear interrupts"); 430 io_mask8(pd->base + SSPICR, SSPICR_RORIC | SSPICR_RTIC, 431 SSPICR_RORIC | SSPICR_RTIC); 432 433 DMSG("set CS GPIO dir to out"); 434 pd->gpio->ops->set_direction(pd->cs_gpio_pin, GPIO_DIR_OUT); 435 436 DMSG("pull CS high"); 437 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_HIGH); 438 } 439 440 void pl022_start(struct pl022_data *pd) 441 { 442 DMSG("empty FIFO before starting"); 443 pl022_flush_fifo(pd); 444 445 DMSG("enable SSP"); 446 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_ENABLE, SSPCR1_SSE); 447 } 448 449 void pl022_end(struct pl022_data *pd) 450 { 451 DMSG("disable SSP"); 452 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_DISABLE, SSPCR1_SSE); 453 } 454 455