1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <assert.h> 30 #include <drivers/pl022_spi.h> 31 #include <initcall.h> 32 #include <io.h> 33 #include <kernel/panic.h> 34 #include <kernel/tee_time.h> 35 #include <platform_config.h> 36 #include <trace.h> 37 #include <util.h> 38 39 /* SPI register offsets */ 40 #define SSPCR0 0x000 41 #define SSPCR1 0x004 42 #define SSPDR 0x008 43 #define SSPSR 0x00C 44 #define SSPCPSR 0x010 45 #define SSPIMSC 0x014 46 #define SSPRIS 0x018 47 #define SSPMIS 0x01C 48 #define SSPICR 0x020 49 #define SSPDMACR 0x024 50 51 #ifdef PLATFORM_hikey 52 /* HiKey extensions */ 53 #define SSPTXFIFOCR 0x028 54 #define SSPRXFIFOCR 0x02C 55 #define SSPB2BTRANS 0x030 56 #endif 57 58 /* test registers */ 59 #define SSPTCR 0x080 60 #define SSPITIP 0x084 61 #define SSPITOP 0x088 62 #define SSPTDR 0x08C 63 64 #define SSPPeriphID0 0xFE0 65 #define SSPPeriphID1 0xFE4 66 #define SSPPeriphID2 0xFE8 67 #define SSPPeriphID3 0xFEC 68 69 #define SSPPCellID0 0xFF0 70 #define SSPPCellID1 0xFF4 71 #define SSPPCellID2 0xFF8 72 #define SSPPCellID3 0xFFC 73 74 /* SPI register masks */ 75 #define SSPCR0_SCR SHIFT_U32(0xFF, 8) 76 #define SSPCR0_SPH SHIFT_U32(1, 7) 77 #define SSPCR0_SPH1 SHIFT_U32(1, 7) 78 #define SSPCR0_SPH0 SHIFT_U32(0, 7) 79 #define SSPCR0_SPO SHIFT_U32(1, 6) 80 #define SSPCR0_SPO1 SHIFT_U32(1, 6) 81 #define SSPCR0_SPO0 SHIFT_U32(0, 6) 82 #define SSPCR0_FRF SHIFT_U32(3, 4) 83 #define SSPCR0_FRF_SPI SHIFT_U32(0, 4) 84 #define SSPCR0_DSS SHIFT_U32(0xFF, 0) 85 #define SSPCR0_DSS_16BIT SHIFT_U32(0xF, 0) 86 #define SSPCR0_DSS_8BIT SHIFT_U32(7, 0) 87 88 #define SSPCR1_SOD SHIFT_U32(1, 3) 89 #define SSPCR1_SOD_ENABLE SHIFT_U32(1, 3) 90 #define SSPCR1_SOD_DISABLE SHIFT_U32(0, 3) 91 #define SSPCR1_MS SHIFT_U32(1, 2) 92 #define SSPCR1_MS_SLAVE SHIFT_U32(1, 2) 93 #define SSPCR1_MS_MASTER SHIFT_U32(0, 2) 94 #define SSPCR1_SSE SHIFT_U32(1, 1) 95 #define SSPCR1_SSE_ENABLE SHIFT_U32(1, 1) 96 #define SSPCR1_SSE_DISABLE SHIFT_U32(0, 1) 97 #define SSPCR1_LBM SHIFT_U32(1, 0) 98 #define SSPCR1_LBM_YES SHIFT_U32(1, 0) 99 #define SSPCR1_LBM_NO SHIFT_U32(0, 0) 100 101 #define SSPDR_DATA SHIFT_U32(0xFFFF, 0) 102 103 #define SSPSR_BSY SHIFT_U32(1, 4) 104 #define SSPSR_RNF SHIFT_U32(1, 3) 105 #define SSPSR_RNE SHIFT_U32(1, 2) 106 #define SSPSR_TNF SHIFT_U32(1, 1) 107 #define SSPSR_TFE SHIFT_U32(1, 0) 108 109 #define SSPCPSR_CPSDVR SHIFT_U32(0xFF, 0) 110 111 #define SSPIMSC_TXIM SHIFT_U32(1, 3) 112 #define SSPIMSC_RXIM SHIFT_U32(1, 2) 113 #define SSPIMSC_RTIM SHIFT_U32(1, 1) 114 #define SSPIMSC_RORIM SHIFT_U32(1, 0) 115 116 #define SSPRIS_TXRIS SHIFT_U32(1, 3) 117 #define SSPRIS_RXRIS SHIFT_U32(1, 2) 118 #define SSPRIS_RTRIS SHIFT_U32(1, 1) 119 #define SSPRIS_RORRIS SHIFT_U32(1, 0) 120 121 #define SSPMIS_TXMIS SHIFT_U32(1, 3) 122 #define SSPMIS_RXMIS SHIFT_U32(1, 2) 123 #define SSPMIS_RTMIS SHIFT_U32(1, 1) 124 #define SSPMIS_RORMIS SHIFT_U32(1, 0) 125 126 #define SSPICR_RTIC SHIFT_U32(1, 1) 127 #define SSPICR_RORIC SHIFT_U32(1, 0) 128 129 #define SSPDMACR_TXDMAE SHIFT_U32(1, 1) 130 #define SSPDMACR_RXDMAE SHIFT_U32(1, 0) 131 132 #define SSPPeriphID0_PartNumber0 SHIFT_U32(0xFF, 0) /* 0x22 */ 133 #define SSPPeriphID1_Designer0 SHIFT_U32(0xF, 4) /* 0x1 */ 134 #define SSPPeriphID1_PartNumber1 SHIFT_U32(0xF, 0) /* 0x0 */ 135 #define SSPPeriphID2_Revision SHIFT_U32(0xF, 4) 136 #define SSPPeriphID2_Designer1 SHIFT_U32(0xF, 0) /* 0x4 */ 137 #define SSPPeriphID3_Configuration SHIFT_U32(0xFF, 0) /* 0x00 */ 138 139 #define SSPPCellID_0 SHIFT_U32(0xFF, 0) /* 0x0D */ 140 #define SSPPCellID_1 SHIFT_U32(0xFF, 0) /* 0xF0 */ 141 #define SSPPPCellID_2 SHIFT_U32(0xFF, 0) /* 0x05 */ 142 #define SSPPPCellID_3 SHIFT_U32(0xFF, 0) /* 0xB1 */ 143 144 #define MASK_32 0xFFFFFFFF 145 #define MASK_28 0xFFFFFFF 146 #define MASK_24 0xFFFFFF 147 #define MASK_20 0xFFFFF 148 #define MASK_16 0xFFFF 149 #define MASK_12 0xFFF 150 #define MASK_8 0xFF 151 #define MASK_4 0xF 152 /* SPI register masks */ 153 154 #define SSP_CPSDVR_MAX 254 155 #define SSP_CPSDVR_MIN 2 156 #define SSP_SCR_MAX 255 157 #define SSP_SCR_MIN 0 158 #define SSP_DATASIZE_MAX 16 159 160 static void pl022_txrx8(struct spi_chip *chip, uint8_t *wdat, uint8_t *rdat, 161 size_t num_pkts) 162 { 163 size_t i = 0; 164 size_t j = 0; 165 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 166 167 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_LOW); 168 169 if (wdat) 170 while (i < num_pkts) 171 if (read8(pd->base + SSPSR) & SSPSR_TNF) { 172 /* tx 1 packet */ 173 write8(wdat[i++], pd->base + SSPDR); 174 } 175 176 if (rdat) 177 while (j < num_pkts) 178 if (read8(pd->base + SSPSR) & SSPSR_RNE) { 179 /* rx 1 packet */ 180 rdat[j++] = read8(pd->base + SSPDR); 181 } 182 183 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_HIGH); 184 } 185 186 static void pl022_txrx16(struct spi_chip *chip, uint16_t *wdat, uint16_t *rdat, 187 size_t num_pkts) 188 { 189 size_t i = 0; 190 size_t j = 0; 191 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 192 193 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_LOW); 194 195 if (wdat) 196 while (i < num_pkts) 197 if (read8(pd->base + SSPSR) & SSPSR_TNF) { 198 /* tx 1 packet */ 199 write16(wdat[i++], pd->base + SSPDR); 200 } 201 202 if (rdat) 203 while (j < num_pkts) 204 if (read8(pd->base + SSPSR) & SSPSR_RNE) { 205 /* rx 1 packet */ 206 rdat[j++] = read16(pd->base + SSPDR); 207 } 208 209 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_HIGH); 210 } 211 212 static void pl022_print_peri_id(struct pl022_data *pd __maybe_unused) 213 { 214 DMSG("Expected: 0x 22 10 ?4 00"); 215 DMSG("Read: 0x %02x %02x %02x %02x", 216 read32(pd->base + SSPPeriphID0), 217 read32(pd->base + SSPPeriphID1), 218 read32(pd->base + SSPPeriphID2), 219 read32(pd->base + SSPPeriphID3)); 220 } 221 222 static void pl022_print_cell_id(struct pl022_data *pd __maybe_unused) 223 { 224 DMSG("Expected: 0x 0d f0 05 b1"); 225 DMSG("Read: 0x %02x %02x %02x %02x", 226 read32(pd->base + SSPPCellID0), 227 read32(pd->base + SSPPCellID1), 228 read32(pd->base + SSPPCellID2), 229 read32(pd->base + SSPPCellID3)); 230 } 231 232 static void pl022_sanity_check(struct pl022_data *pd) 233 { 234 assert(pd); 235 assert(pd->chip.ops); 236 assert(pd->gpio); 237 assert(pd->gpio->ops); 238 assert(pd->base); 239 assert(pd->cs_gpio_base); 240 assert(pd->clk_hz); 241 assert(pd->speed_hz && pd->speed_hz <= pd->clk_hz/2); 242 assert(pd->mode <= SPI_MODE3); 243 assert(pd->data_size_bits == 8 || pd->data_size_bits == 16); 244 245 #ifdef PLATFORM_hikey 246 DMSG("SSPB2BTRANS: Expected: 0x2. Read: 0x%x", 247 read32(pd->base + SSPB2BTRANS)); 248 #endif 249 pl022_print_peri_id(pd); 250 pl022_print_cell_id(pd); 251 } 252 253 static inline uint32_t pl022_calc_freq(struct pl022_data *pd, 254 uint8_t cpsdvr, uint8_t scr) 255 { 256 return pd->clk_hz / (cpsdvr * (1 + scr)); 257 } 258 259 static void pl022_calc_clk_divisors(struct pl022_data *pd, 260 uint8_t *cpsdvr, uint8_t *scr) 261 { 262 unsigned int freq1 = 0; 263 unsigned int freq2 = 0; 264 uint8_t tmp_cpsdvr1; 265 uint8_t tmp_scr1; 266 uint8_t tmp_cpsdvr2 = 0; 267 uint8_t tmp_scr2 = 0; 268 269 for (tmp_scr1 = SSP_SCR_MIN; tmp_scr1 < SSP_SCR_MAX; tmp_scr1++) { 270 for (tmp_cpsdvr1 = SSP_CPSDVR_MIN; tmp_cpsdvr1 < SSP_CPSDVR_MAX; 271 tmp_cpsdvr1++) { 272 freq1 = pl022_calc_freq(pd, tmp_cpsdvr1, tmp_scr1); 273 if (freq1 == pd->speed_hz) 274 goto done; 275 else if (freq1 < pd->speed_hz) 276 goto stage2; 277 } 278 } 279 280 stage2: 281 for (tmp_cpsdvr2 = SSP_CPSDVR_MIN; tmp_cpsdvr2 < SSP_CPSDVR_MAX; 282 tmp_cpsdvr2++) { 283 for (tmp_scr2 = SSP_SCR_MIN; tmp_scr2 < SSP_SCR_MAX; 284 tmp_scr2++) { 285 freq2 = pl022_calc_freq(pd, tmp_cpsdvr2, tmp_scr2); 286 if (freq2 <= pd->speed_hz) 287 goto done; 288 } 289 } 290 291 done: 292 if (freq1 >= freq2) { 293 *cpsdvr = tmp_cpsdvr1; 294 *scr = tmp_scr1; 295 DMSG("speed: requested: %u, closest1: %u", 296 pd->speed_hz, freq1); 297 } else { 298 *cpsdvr = tmp_cpsdvr2; 299 *scr = tmp_scr2; 300 DMSG("speed: requested: %u, closest2: %u", 301 pd->speed_hz, freq2); 302 } 303 DMSG("CPSDVR: %u (0x%x), SCR: %u (0x%x)", 304 *cpsdvr, *cpsdvr, *scr, *scr); 305 } 306 307 static void pl022_flush_fifo(struct pl022_data *pd) 308 { 309 uint32_t __maybe_unused rdat; 310 311 do { 312 while (read32(pd->base + SSPSR) & SSPSR_RNE) { 313 rdat = read32(pd->base + SSPDR); 314 DMSG("rdat: 0x%x", rdat); 315 } 316 } while (read32(pd->base + SSPSR) & SSPSR_BSY); 317 } 318 319 static const struct spi_ops pl022_ops = { 320 .txrx8 = pl022_txrx8, 321 .txrx16 = pl022_txrx16, 322 }; 323 324 void pl022_configure(struct pl022_data *pd) 325 { 326 uint16_t mode; 327 uint16_t data_size; 328 uint8_t cpsdvr; 329 uint8_t scr; 330 uint8_t lbm; 331 332 pd->chip.ops = &pl022_ops; 333 pl022_sanity_check(pd); 334 pl022_calc_clk_divisors(pd, &cpsdvr, &scr); 335 336 /* configure ssp based on platform settings */ 337 switch (pd->mode) { 338 case SPI_MODE0: 339 DMSG("SPI mode 0"); 340 mode = SSPCR0_SPO0 | SSPCR0_SPH0; 341 break; 342 case SPI_MODE1: 343 DMSG("SPI mode 1"); 344 mode = SSPCR0_SPO0 | SSPCR0_SPH1; 345 break; 346 case SPI_MODE2: 347 DMSG("SPI mode 2"); 348 mode = SSPCR0_SPO1 | SSPCR0_SPH0; 349 break; 350 case SPI_MODE3: 351 DMSG("SPI mode 3"); 352 mode = SSPCR0_SPO1 | SSPCR0_SPH1; 353 break; 354 default: 355 EMSG("Invalid SPI mode: %u", pd->mode); 356 panic(); 357 } 358 359 switch (pd->data_size_bits) { 360 case 8: 361 DMSG("Data size: 8"); 362 data_size = SSPCR0_DSS_8BIT; 363 break; 364 case 16: 365 DMSG("Data size: 16"); 366 data_size = SSPCR0_DSS_16BIT; 367 break; 368 default: 369 EMSG("Unsupported data size: %u bits", pd->data_size_bits); 370 panic(); 371 } 372 373 if (pd->loopback) { 374 DMSG("Starting in loopback mode!"); 375 lbm = SSPCR1_LBM_YES; 376 } else { 377 DMSG("Starting in regular (non-loopback) mode!"); 378 lbm = SSPCR1_LBM_NO; 379 } 380 381 DMSG("set Serial Clock Rate (SCR), SPI mode (phase and clock)"); 382 DMSG("set frame format (SPI) and data size (8- or 16-bit)"); 383 io_mask16(pd->base + SSPCR0, SHIFT_U32(scr, 8) | mode | SSPCR0_FRF_SPI | 384 data_size, MASK_16); 385 386 DMSG("set master mode, disable SSP, set loopback mode"); 387 io_mask8(pd->base + SSPCR1, SSPCR1_SOD_DISABLE | SSPCR1_MS_MASTER | 388 SSPCR1_SSE_DISABLE | lbm, MASK_4); 389 390 DMSG("set clock prescale"); 391 io_mask8(pd->base + SSPCPSR, cpsdvr, SSPCPSR_CPSDVR); 392 393 DMSG("disable interrupts"); 394 io_mask8(pd->base + SSPIMSC, 0, MASK_4); 395 396 DMSG("set CS GPIO dir to out"); 397 pd->gpio->ops->set_direction(pd->cs_gpio_pin, GPIO_DIR_OUT); 398 399 DMSG("pull CS high"); 400 pd->gpio->ops->set_value(pd->cs_gpio_pin, GPIO_LEVEL_HIGH); 401 } 402 403 void pl022_start(struct pl022_data *pd) 404 { 405 DMSG("empty FIFO before starting"); 406 pl022_flush_fifo(pd); 407 408 DMSG("enable SSP"); 409 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_ENABLE, SSPCR1_SSE); 410 } 411 412 void pl022_end(struct pl022_data *pd) 413 { 414 DMSG("disable SSP"); 415 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_DISABLE, SSPCR1_SSE); 416 } 417 418