1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <assert.h> 30 #include <drivers/pl022_spi.h> 31 #include <initcall.h> 32 #include <io.h> 33 #include <kernel/panic.h> 34 #include <kernel/tee_time.h> 35 #include <platform_config.h> 36 #include <trace.h> 37 #include <util.h> 38 39 /* SPI register offsets */ 40 #define SSPCR0 0x000 41 #define SSPCR1 0x004 42 #define SSPDR 0x008 43 #define SSPSR 0x00C 44 #define SSPCPSR 0x010 45 #define SSPIMSC 0x014 46 #define SSPRIS 0x018 47 #define SSPMIS 0x01C 48 #define SSPICR 0x020 49 #define SSPDMACR 0x024 50 51 #ifdef PLATFORM_hikey 52 /* HiKey extensions */ 53 #define SSPTXFIFOCR 0x028 54 #define SSPRXFIFOCR 0x02C 55 #define SSPB2BTRANS 0x030 56 #endif 57 58 /* test registers */ 59 #define SSPTCR 0x080 60 #define SSPITIP 0x084 61 #define SSPITOP 0x088 62 #define SSPTDR 0x08C 63 64 #define SSPPeriphID0 0xFE0 65 #define SSPPeriphID1 0xFE4 66 #define SSPPeriphID2 0xFE8 67 #define SSPPeriphID3 0xFEC 68 69 #define SSPPCellID0 0xFF0 70 #define SSPPCellID1 0xFF4 71 #define SSPPCellID2 0xFF8 72 #define SSPPCellID3 0xFFC 73 74 /* SPI register masks */ 75 #define SSPCR0_SCR SHIFT_U32(0xFF, 8) 76 #define SSPCR0_SPH SHIFT_U32(1, 7) 77 #define SSPCR0_SPH1 SHIFT_U32(1, 7) 78 #define SSPCR0_SPH0 SHIFT_U32(0, 7) 79 #define SSPCR0_SPO SHIFT_U32(1, 6) 80 #define SSPCR0_SPO1 SHIFT_U32(1, 6) 81 #define SSPCR0_SPO0 SHIFT_U32(0, 6) 82 #define SSPCR0_FRF SHIFT_U32(3, 4) 83 #define SSPCR0_FRF_SPI SHIFT_U32(0, 4) 84 #define SSPCR0_DSS SHIFT_U32(0xFF, 0) 85 #define SSPCR0_DSS_16BIT SHIFT_U32(0xF, 0) 86 #define SSPCR0_DSS_8BIT SHIFT_U32(7, 0) 87 88 #define SSPCR1_SOD SHIFT_U32(1, 3) 89 #define SSPCR1_SOD_ENABLE SHIFT_U32(1, 3) 90 #define SSPCR1_SOD_DISABLE SHIFT_U32(0, 3) 91 #define SSPCR1_MS SHIFT_U32(1, 2) 92 #define SSPCR1_MS_SLAVE SHIFT_U32(1, 2) 93 #define SSPCR1_MS_MASTER SHIFT_U32(0, 2) 94 #define SSPCR1_SSE SHIFT_U32(1, 1) 95 #define SSPCR1_SSE_ENABLE SHIFT_U32(1, 1) 96 #define SSPCR1_SSE_DISABLE SHIFT_U32(0, 1) 97 #define SSPCR1_LBM SHIFT_U32(1, 0) 98 #define SSPCR1_LBM_YES SHIFT_U32(1, 0) 99 #define SSPCR1_LBM_NO SHIFT_U32(0, 0) 100 101 #define SSPDR_DATA SHIFT_U32(0xFFFF, 0) 102 103 #define SSPSR_BSY SHIFT_U32(1, 4) 104 #define SSPSR_RNF SHIFT_U32(1, 3) 105 #define SSPSR_RNE SHIFT_U32(1, 2) 106 #define SSPSR_TNF SHIFT_U32(1, 1) 107 #define SSPSR_TFE SHIFT_U32(1, 0) 108 109 #define SSPCPSR_CPSDVR SHIFT_U32(0xFF, 0) 110 111 #define SSPIMSC_TXIM SHIFT_U32(1, 3) 112 #define SSPIMSC_RXIM SHIFT_U32(1, 2) 113 #define SSPIMSC_RTIM SHIFT_U32(1, 1) 114 #define SSPIMSC_RORIM SHIFT_U32(1, 0) 115 116 #define SSPRIS_TXRIS SHIFT_U32(1, 3) 117 #define SSPRIS_RXRIS SHIFT_U32(1, 2) 118 #define SSPRIS_RTRIS SHIFT_U32(1, 1) 119 #define SSPRIS_RORRIS SHIFT_U32(1, 0) 120 121 #define SSPMIS_TXMIS SHIFT_U32(1, 3) 122 #define SSPMIS_RXMIS SHIFT_U32(1, 2) 123 #define SSPMIS_RTMIS SHIFT_U32(1, 1) 124 #define SSPMIS_RORMIS SHIFT_U32(1, 0) 125 126 #define SSPICR_RTIC SHIFT_U32(1, 1) 127 #define SSPICR_RORIC SHIFT_U32(1, 0) 128 129 #define SSPDMACR_TXDMAE SHIFT_U32(1, 1) 130 #define SSPDMACR_RXDMAE SHIFT_U32(1, 0) 131 132 #define SSPPeriphID0_PartNumber0 SHIFT_U32(0xFF, 0) /* 0x22 */ 133 #define SSPPeriphID1_Designer0 SHIFT_U32(0xF, 4) /* 0x1 */ 134 #define SSPPeriphID1_PartNumber1 SHIFT_U32(0xF, 0) /* 0x0 */ 135 #define SSPPeriphID2_Revision SHIFT_U32(0xF, 4) 136 #define SSPPeriphID2_Designer1 SHIFT_U32(0xF, 0) /* 0x4 */ 137 #define SSPPeriphID3_Configuration SHIFT_U32(0xFF, 0) /* 0x00 */ 138 139 #define SSPPCellID_0 SHIFT_U32(0xFF, 0) /* 0x0D */ 140 #define SSPPCellID_1 SHIFT_U32(0xFF, 0) /* 0xF0 */ 141 #define SSPPPCellID_2 SHIFT_U32(0xFF, 0) /* 0x05 */ 142 #define SSPPPCellID_3 SHIFT_U32(0xFF, 0) /* 0xB1 */ 143 144 #define MASK_32 0xFFFFFFFF 145 #define MASK_28 0xFFFFFFF 146 #define MASK_24 0xFFFFFF 147 #define MASK_20 0xFFFFF 148 #define MASK_16 0xFFFF 149 #define MASK_12 0xFFF 150 #define MASK_8 0xFF 151 #define MASK_4 0xF 152 /* SPI register masks */ 153 154 #define SSP_CPSDVR_MAX 254 155 #define SSP_CPSDVR_MIN 2 156 #define SSP_SCR_MAX 255 157 #define SSP_SCR_MIN 0 158 #define SSP_DATASIZE_MAX 16 159 160 static enum spi_result pl022_txrx8(struct spi_chip *chip, uint8_t *wdat, 161 uint8_t *rdat, size_t num_pkts) 162 { 163 size_t i = 0; 164 size_t j = 0; 165 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 166 167 168 if (pd->data_size_bits != 8) { 169 EMSG("data_size_bits should be 8, not %u", 170 pd->data_size_bits); 171 return SPI_ERR_CFG; 172 } 173 174 if (wdat) 175 while (i < num_pkts) 176 if (read8(pd->base + SSPSR) & SSPSR_TNF) { 177 /* tx 1 packet */ 178 write8(wdat[i++], pd->base + SSPDR); 179 } 180 181 if (rdat) { 182 while ((j < num_pkts) && 183 (read8(pd->base + SSPSR) & SSPSR_BSY)) 184 if (read8(pd->base + SSPSR) & SSPSR_RNE) { 185 /* rx 1 packet */ 186 rdat[j++] = read8(pd->base + SSPDR); 187 } 188 189 if (j < num_pkts) { 190 EMSG("Packets requested %zu, received %zu", 191 num_pkts, j); 192 return SPI_ERR_PKTCNT; 193 } 194 } 195 196 return SPI_OK; 197 } 198 199 static enum spi_result pl022_txrx16(struct spi_chip *chip, uint16_t *wdat, 200 uint16_t *rdat, size_t num_pkts) 201 { 202 size_t i = 0; 203 size_t j = 0; 204 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 205 206 if (pd->data_size_bits != 16) { 207 EMSG("data_size_bits should be 16, not %u", 208 pd->data_size_bits); 209 return SPI_ERR_CFG; 210 } 211 212 if (wdat) 213 while (i < num_pkts) 214 if (read8(pd->base + SSPSR) & SSPSR_TNF) { 215 /* tx 1 packet */ 216 write16(wdat[i++], pd->base + SSPDR); 217 } 218 219 if (rdat) { 220 while ((j < num_pkts) && 221 (read8(pd->base + SSPSR) & SSPSR_BSY)) 222 if (read8(pd->base + SSPSR) & SSPSR_RNE) { 223 /* rx 1 packet */ 224 rdat[j++] = read16(pd->base + SSPDR); 225 } 226 227 if (j < num_pkts) { 228 EMSG("Packets requested %zu, received %zu", 229 num_pkts, j); 230 return SPI_ERR_PKTCNT; 231 } 232 } 233 234 return SPI_OK; 235 } 236 237 static void pl022_print_peri_id(struct pl022_data *pd __maybe_unused) 238 { 239 DMSG("Expected: 0x 22 10 ?4 00"); 240 DMSG("Read: 0x %02x %02x %02x %02x", 241 read32(pd->base + SSPPeriphID0), 242 read32(pd->base + SSPPeriphID1), 243 read32(pd->base + SSPPeriphID2), 244 read32(pd->base + SSPPeriphID3)); 245 } 246 247 static void pl022_print_cell_id(struct pl022_data *pd __maybe_unused) 248 { 249 DMSG("Expected: 0x 0d f0 05 b1"); 250 DMSG("Read: 0x %02x %02x %02x %02x", 251 read32(pd->base + SSPPCellID0), 252 read32(pd->base + SSPPCellID1), 253 read32(pd->base + SSPPCellID2), 254 read32(pd->base + SSPPCellID3)); 255 } 256 257 static void pl022_sanity_check(struct pl022_data *pd) 258 { 259 assert(pd); 260 assert(pd->chip.ops); 261 assert(pd->cs_control <= PL022_CS_CTRL_MANUAL); 262 switch (pd->cs_control) { 263 case PL022_CS_CTRL_AUTO_GPIO: 264 assert(pd->cs_data.gpio_data.chip); 265 assert(pd->cs_data.gpio_data.chip->ops); 266 break; 267 case PL022_CS_CTRL_CB: 268 assert(pd->cs_data.cs_cb); 269 break; 270 default: 271 break; 272 } 273 assert(pd->clk_hz); 274 assert(pd->speed_hz && pd->speed_hz <= pd->clk_hz/2); 275 assert(pd->mode <= SPI_MODE3); 276 assert(pd->data_size_bits == 8 || pd->data_size_bits == 16); 277 278 #ifdef PLATFORM_hikey 279 DMSG("SSPB2BTRANS: Expected: 0x2. Read: 0x%x", 280 read32(pd->base + SSPB2BTRANS)); 281 #endif 282 pl022_print_peri_id(pd); 283 pl022_print_cell_id(pd); 284 } 285 286 static inline uint32_t pl022_calc_freq(struct pl022_data *pd, 287 uint8_t cpsdvr, uint8_t scr) 288 { 289 return pd->clk_hz / (cpsdvr * (1 + scr)); 290 } 291 292 static void pl022_control_cs(struct spi_chip *chip, enum gpio_level value) 293 { 294 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 295 296 switch (pd->cs_control) { 297 case PL022_CS_CTRL_AUTO_GPIO: 298 if (read8(pd->base + SSPSR) & SSPSR_BSY) 299 DMSG("pl022 busy - do NOT set CS!"); 300 while (read8(pd->base + SSPSR) & SSPSR_BSY) 301 ; 302 DMSG("pl022 done - set CS!"); 303 304 pd->cs_data.gpio_data.chip->ops->set_value( 305 pd->cs_data.gpio_data.pin_num, value); 306 break; 307 case PL022_CS_CTRL_CB: 308 pd->cs_data.cs_cb(value); 309 break; 310 default: 311 break; 312 } 313 } 314 315 static void pl022_calc_clk_divisors(struct pl022_data *pd, 316 uint8_t *cpsdvr, uint8_t *scr) 317 { 318 unsigned int freq1 = 0; 319 unsigned int freq2 = 0; 320 uint8_t tmp_cpsdvr1; 321 uint8_t tmp_scr1; 322 uint8_t tmp_cpsdvr2 = 0; 323 uint8_t tmp_scr2 = 0; 324 325 for (tmp_scr1 = SSP_SCR_MIN; tmp_scr1 < SSP_SCR_MAX; tmp_scr1++) { 326 for (tmp_cpsdvr1 = SSP_CPSDVR_MIN; tmp_cpsdvr1 < SSP_CPSDVR_MAX; 327 tmp_cpsdvr1++) { 328 freq1 = pl022_calc_freq(pd, tmp_cpsdvr1, tmp_scr1); 329 if (freq1 == pd->speed_hz) 330 goto done; 331 else if (freq1 < pd->speed_hz) 332 goto stage2; 333 } 334 } 335 336 stage2: 337 for (tmp_cpsdvr2 = SSP_CPSDVR_MIN; tmp_cpsdvr2 < SSP_CPSDVR_MAX; 338 tmp_cpsdvr2++) { 339 for (tmp_scr2 = SSP_SCR_MIN; tmp_scr2 < SSP_SCR_MAX; 340 tmp_scr2++) { 341 freq2 = pl022_calc_freq(pd, tmp_cpsdvr2, tmp_scr2); 342 if (freq2 <= pd->speed_hz) 343 goto done; 344 } 345 } 346 347 done: 348 if (freq1 >= freq2) { 349 *cpsdvr = tmp_cpsdvr1; 350 *scr = tmp_scr1; 351 DMSG("speed: requested: %u, closest1: %u", 352 pd->speed_hz, freq1); 353 } else { 354 *cpsdvr = tmp_cpsdvr2; 355 *scr = tmp_scr2; 356 DMSG("speed: requested: %u, closest2: %u", 357 pd->speed_hz, freq2); 358 } 359 DMSG("CPSDVR: %u (0x%x), SCR: %u (0x%x)", 360 *cpsdvr, *cpsdvr, *scr, *scr); 361 } 362 363 static void pl022_flush_fifo(struct pl022_data *pd) 364 { 365 uint32_t __maybe_unused rdat; 366 367 do { 368 while (read32(pd->base + SSPSR) & SSPSR_RNE) { 369 rdat = read32(pd->base + SSPDR); 370 DMSG("rdat: 0x%x", rdat); 371 } 372 } while (read32(pd->base + SSPSR) & SSPSR_BSY); 373 } 374 375 static void pl022_configure(struct spi_chip *chip) 376 { 377 uint16_t mode; 378 uint16_t data_size; 379 uint8_t cpsdvr; 380 uint8_t scr; 381 uint8_t lbm; 382 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 383 384 pl022_sanity_check(pd); 385 386 switch (pd->cs_control) { 387 case PL022_CS_CTRL_AUTO_GPIO: 388 DMSG("Use auto GPIO CS control"); 389 DMSG("Mask/disable interrupt for CS GPIO"); 390 pd->cs_data.gpio_data.chip->ops->set_interrupt( 391 pd->cs_data.gpio_data.pin_num, 392 GPIO_INTERRUPT_DISABLE); 393 DMSG("Set CS GPIO dir to out"); 394 pd->cs_data.gpio_data.chip->ops->set_direction( 395 pd->cs_data.gpio_data.pin_num, 396 GPIO_DIR_OUT); 397 break; 398 case PL022_CS_CTRL_CB: 399 DMSG("Use registered CS callback"); 400 break; 401 case PL022_CS_CTRL_MANUAL: 402 DMSG("Use manual CS control"); 403 break; 404 default: 405 EMSG("Invalid CS control type: %d", pd->cs_control); 406 panic(); 407 } 408 409 DMSG("Pull CS high"); 410 pl022_control_cs(chip, GPIO_LEVEL_HIGH); 411 412 pl022_calc_clk_divisors(pd, &cpsdvr, &scr); 413 414 /* configure ssp based on platform settings */ 415 switch (pd->mode) { 416 case SPI_MODE0: 417 DMSG("SPI mode 0"); 418 mode = SSPCR0_SPO0 | SSPCR0_SPH0; 419 break; 420 case SPI_MODE1: 421 DMSG("SPI mode 1"); 422 mode = SSPCR0_SPO0 | SSPCR0_SPH1; 423 break; 424 case SPI_MODE2: 425 DMSG("SPI mode 2"); 426 mode = SSPCR0_SPO1 | SSPCR0_SPH0; 427 break; 428 case SPI_MODE3: 429 DMSG("SPI mode 3"); 430 mode = SSPCR0_SPO1 | SSPCR0_SPH1; 431 break; 432 default: 433 EMSG("Invalid SPI mode: %u", pd->mode); 434 panic(); 435 } 436 437 switch (pd->data_size_bits) { 438 case 8: 439 DMSG("Data size: 8"); 440 data_size = SSPCR0_DSS_8BIT; 441 break; 442 case 16: 443 DMSG("Data size: 16"); 444 data_size = SSPCR0_DSS_16BIT; 445 break; 446 default: 447 EMSG("Unsupported data size: %u bits", pd->data_size_bits); 448 panic(); 449 } 450 451 if (pd->loopback) { 452 DMSG("Starting in loopback mode!"); 453 lbm = SSPCR1_LBM_YES; 454 } else { 455 DMSG("Starting in regular (non-loopback) mode!"); 456 lbm = SSPCR1_LBM_NO; 457 } 458 459 DMSG("Set Serial Clock Rate (SCR), SPI mode (phase and clock)"); 460 DMSG("Set frame format (SPI) and data size (8- or 16-bit)"); 461 io_mask16(pd->base + SSPCR0, SHIFT_U32(scr, 8) | mode | SSPCR0_FRF_SPI | 462 data_size, MASK_16); 463 464 DMSG("Set master mode, disable SSP, set loopback mode"); 465 io_mask8(pd->base + SSPCR1, SSPCR1_SOD_DISABLE | SSPCR1_MS_MASTER | 466 SSPCR1_SSE_DISABLE | lbm, MASK_4); 467 468 DMSG("Set clock prescale"); 469 io_mask8(pd->base + SSPCPSR, cpsdvr, SSPCPSR_CPSDVR); 470 471 DMSG("Disable interrupts"); 472 io_mask8(pd->base + SSPIMSC, 0, MASK_4); 473 474 DMSG("Clear interrupts"); 475 io_mask8(pd->base + SSPICR, SSPICR_RORIC | SSPICR_RTIC, 476 SSPICR_RORIC | SSPICR_RTIC); 477 478 DMSG("Empty FIFO before starting"); 479 pl022_flush_fifo(pd); 480 } 481 482 static void pl022_start(struct spi_chip *chip) 483 { 484 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 485 486 DMSG("Enable SSP"); 487 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_ENABLE, SSPCR1_SSE); 488 489 pl022_control_cs(chip, GPIO_LEVEL_LOW); 490 } 491 492 static void pl022_end(struct spi_chip *chip) 493 { 494 struct pl022_data *pd = container_of(chip, struct pl022_data, chip); 495 496 pl022_control_cs(chip, GPIO_LEVEL_HIGH); 497 498 DMSG("Disable SSP"); 499 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_DISABLE, SSPCR1_SSE); 500 } 501 502 static const struct spi_ops pl022_ops = { 503 .configure = pl022_configure, 504 .start = pl022_start, 505 .txrx8 = pl022_txrx8, 506 .txrx16 = pl022_txrx16, 507 .end = pl022_end, 508 }; 509 510 void pl022_init(struct pl022_data *pd) 511 { 512 assert(pd); 513 pd->chip.ops = &pl022_ops; 514 } 515