1 /* 2 * Copyright (c) 2014, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <assert.h> 28 #include <drivers/pl011.h> 29 #include <io.h> 30 #include <keep.h> 31 #include <kernel/dt.h> 32 #include <stdlib.h> 33 #include <trace.h> 34 #include <types_ext.h> 35 #include <util.h> 36 37 #define UART_DR 0x00 /* data register */ 38 #define UART_RSR_ECR 0x04 /* receive status or error clear */ 39 #define UART_DMAWM 0x08 /* DMA watermark configure */ 40 #define UART_TIMEOUT 0x0C /* Timeout period */ 41 /* reserved space */ 42 #define UART_FR 0x18 /* flag register */ 43 #define UART_ILPR 0x20 /* IrDA low-poer */ 44 #define UART_IBRD 0x24 /* integer baud register */ 45 #define UART_FBRD 0x28 /* fractional baud register */ 46 #define UART_LCR_H 0x2C /* line control register */ 47 #define UART_CR 0x30 /* control register */ 48 #define UART_IFLS 0x34 /* interrupt FIFO level select */ 49 #define UART_IMSC 0x38 /* interrupt mask set/clear */ 50 #define UART_RIS 0x3C /* raw interrupt register */ 51 #define UART_MIS 0x40 /* masked interrupt register */ 52 #define UART_ICR 0x44 /* interrupt clear register */ 53 #define UART_DMACR 0x48 /* DMA control register */ 54 55 /* flag register bits */ 56 #define UART_FR_RTXDIS (1 << 13) 57 #define UART_FR_TERI (1 << 12) 58 #define UART_FR_DDCD (1 << 11) 59 #define UART_FR_DDSR (1 << 10) 60 #define UART_FR_DCTS (1 << 9) 61 #define UART_FR_RI (1 << 8) 62 #define UART_FR_TXFE (1 << 7) 63 #define UART_FR_RXFF (1 << 6) 64 #define UART_FR_TXFF (1 << 5) 65 #define UART_FR_RXFE (1 << 4) 66 #define UART_FR_BUSY (1 << 3) 67 #define UART_FR_DCD (1 << 2) 68 #define UART_FR_DSR (1 << 1) 69 #define UART_FR_CTS (1 << 0) 70 71 /* transmit/receive line register bits */ 72 #define UART_LCRH_SPS (1 << 7) 73 #define UART_LCRH_WLEN_8 (3 << 5) 74 #define UART_LCRH_WLEN_7 (2 << 5) 75 #define UART_LCRH_WLEN_6 (1 << 5) 76 #define UART_LCRH_WLEN_5 (0 << 5) 77 #define UART_LCRH_FEN (1 << 4) 78 #define UART_LCRH_STP2 (1 << 3) 79 #define UART_LCRH_EPS (1 << 2) 80 #define UART_LCRH_PEN (1 << 1) 81 #define UART_LCRH_BRK (1 << 0) 82 83 /* control register bits */ 84 #define UART_CR_CTSEN (1 << 15) 85 #define UART_CR_RTSEN (1 << 14) 86 #define UART_CR_OUT2 (1 << 13) 87 #define UART_CR_OUT1 (1 << 12) 88 #define UART_CR_RTS (1 << 11) 89 #define UART_CR_DTR (1 << 10) 90 #define UART_CR_RXE (1 << 9) 91 #define UART_CR_TXE (1 << 8) 92 #define UART_CR_LPE (1 << 7) 93 #define UART_CR_OVSFACT (1 << 3) 94 #define UART_CR_UARTEN (1 << 0) 95 96 #define UART_IMSC_RTIM (1 << 6) 97 #define UART_IMSC_RXIM (1 << 4) 98 99 static vaddr_t chip_to_base(struct serial_chip *chip) 100 { 101 struct pl011_data *pd = 102 container_of(chip, struct pl011_data, chip); 103 104 return io_pa_or_va(&pd->base); 105 } 106 107 static void pl011_flush(struct serial_chip *chip) 108 { 109 vaddr_t base = chip_to_base(chip); 110 111 while (!(read32(base + UART_FR) & UART_FR_TXFE)) 112 ; 113 } 114 115 static bool pl011_have_rx_data(struct serial_chip *chip) 116 { 117 vaddr_t base = chip_to_base(chip); 118 119 return !(read32(base + UART_FR) & UART_FR_RXFE); 120 } 121 122 static int pl011_getchar(struct serial_chip *chip) 123 { 124 vaddr_t base = chip_to_base(chip); 125 126 while (!pl011_have_rx_data(chip)) 127 ; 128 return read32(base + UART_DR) & 0xff; 129 } 130 131 static void pl011_putc(struct serial_chip *chip, int ch) 132 { 133 vaddr_t base = chip_to_base(chip); 134 135 /* Wait until there is space in the FIFO */ 136 while (read32(base + UART_FR) & UART_FR_TXFF) 137 ; 138 139 /* Send the character */ 140 write32(ch, base + UART_DR); 141 } 142 143 static const struct serial_ops pl011_ops = { 144 .flush = pl011_flush, 145 .getchar = pl011_getchar, 146 .have_rx_data = pl011_have_rx_data, 147 .putc = pl011_putc, 148 }; 149 KEEP_PAGER(pl011_ops); 150 151 void pl011_init(struct pl011_data *pd, paddr_t pbase, uint32_t uart_clk, 152 uint32_t baud_rate) 153 { 154 vaddr_t base; 155 156 pd->base.pa = pbase; 157 pd->chip.ops = &pl011_ops; 158 159 base = io_pa_or_va(&pd->base); 160 161 /* Clear all errors */ 162 write32(0, base + UART_RSR_ECR); 163 /* Disable everything */ 164 write32(0, base + UART_CR); 165 166 if (baud_rate) { 167 uint32_t divisor = (uart_clk * 4) / baud_rate; 168 169 write32(divisor >> 6, base + UART_IBRD); 170 write32(divisor & 0x3f, base + UART_FBRD); 171 } 172 173 /* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */ 174 write32(UART_LCRH_WLEN_8, base + UART_LCR_H); 175 176 /* Enable interrupts for receive and receive timeout */ 177 write32(UART_IMSC_RXIM | UART_IMSC_RTIM, base + UART_IMSC); 178 179 /* Enable UART and RX/TX */ 180 write32(UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE, base + UART_CR); 181 182 pl011_flush(&pd->chip); 183 } 184 185 #ifdef CFG_DT 186 187 static struct serial_chip *pl011_dev_alloc(void) 188 { 189 struct pl011_data *pd = malloc(sizeof(*pd)); 190 191 if (!pd) 192 return NULL; 193 return &pd->chip; 194 } 195 196 static int pl011_dev_init(struct serial_chip *chip, const void *fdt, int offs, 197 const char *parms) 198 { 199 struct pl011_data *pd = container_of(chip, struct pl011_data, chip); 200 vaddr_t vbase; 201 paddr_t pbase; 202 size_t size; 203 204 if (parms && parms[0]) 205 IMSG("pl011: device parameters ignored (%s)", parms); 206 207 if (dt_map_dev(fdt, offs, &vbase, &size) < 0) 208 return -1; 209 210 if (size != 0x1000) { 211 EMSG("pl011: unexpected register size: %zx", size); 212 return -1; 213 } 214 215 pbase = virt_to_phys((void *)vbase); 216 pl011_init(pd, pbase, 0, 0); 217 218 return 0; 219 } 220 221 static void pl011_dev_free(struct serial_chip *chip) 222 { 223 struct pl011_data *pd = container_of(chip, struct pl011_data, chip); 224 225 free(pd); 226 } 227 228 static const struct serial_driver pl011_driver = { 229 .dev_alloc = pl011_dev_alloc, 230 .dev_init = pl011_dev_init, 231 .dev_free = pl011_dev_free, 232 }; 233 234 static const struct dt_device_match pl011_match_table[] = { 235 { .compatible = "arm,pl011" }, 236 { 0 } 237 }; 238 239 const struct dt_driver pl011_dt_driver __dt_driver = { 240 .name = "pl011", 241 .match_table = pl011_match_table, 242 .driver = &pl011_driver, 243 }; 244 245 #endif /* CFG_DT */ 246