1 /* 2 * Copyright (c) 2014, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <drivers/pl011.h> 28 #include <io.h> 29 30 #define UART_DR 0x00 /* data register */ 31 #define UART_RSR_ECR 0x04 /* receive status or error clear */ 32 #define UART_DMAWM 0x08 /* DMA watermark configure */ 33 #define UART_TIMEOUT 0x0C /* Timeout period */ 34 /* reserved space */ 35 #define UART_FR 0x18 /* flag register */ 36 #define UART_ILPR 0x20 /* IrDA low-poer */ 37 #define UART_IBRD 0x24 /* integer baud register */ 38 #define UART_FBRD 0x28 /* fractional baud register */ 39 #define UART_LCR_H 0x2C /* line control register */ 40 #define UART_CR 0x30 /* control register */ 41 #define UART_IFLS 0x34 /* interrupt FIFO level select */ 42 #define UART_IMSC 0x38 /* interrupt mask set/clear */ 43 #define UART_RIS 0x3C /* raw interrupt register */ 44 #define UART_MIS 0x40 /* masked interrupt register */ 45 #define UART_ICR 0x44 /* interrupt clear register */ 46 #define UART_DMACR 0x48 /* DMA control register */ 47 48 /* flag register bits */ 49 #define UART_FR_RTXDIS (1 << 13) 50 #define UART_FR_TERI (1 << 12) 51 #define UART_FR_DDCD (1 << 11) 52 #define UART_FR_DDSR (1 << 10) 53 #define UART_FR_DCTS (1 << 9) 54 #define UART_FR_RI (1 << 8) 55 #define UART_FR_TXFE (1 << 7) 56 #define UART_FR_RXFF (1 << 6) 57 #define UART_FR_TXFF (1 << 5) 58 #define UART_FR_RXFE (1 << 4) 59 #define UART_FR_BUSY (1 << 3) 60 #define UART_FR_DCD (1 << 2) 61 #define UART_FR_DSR (1 << 1) 62 #define UART_FR_CTS (1 << 0) 63 64 /* transmit/receive line register bits */ 65 #define UART_LCRH_SPS (1 << 7) 66 #define UART_LCRH_WLEN_8 (3 << 5) 67 #define UART_LCRH_WLEN_7 (2 << 5) 68 #define UART_LCRH_WLEN_6 (1 << 5) 69 #define UART_LCRH_WLEN_5 (0 << 5) 70 #define UART_LCRH_FEN (1 << 4) 71 #define UART_LCRH_STP2 (1 << 3) 72 #define UART_LCRH_EPS (1 << 2) 73 #define UART_LCRH_PEN (1 << 1) 74 #define UART_LCRH_BRK (1 << 0) 75 76 /* control register bits */ 77 #define UART_CR_CTSEN (1 << 15) 78 #define UART_CR_RTSEN (1 << 14) 79 #define UART_CR_OUT2 (1 << 13) 80 #define UART_CR_OUT1 (1 << 12) 81 #define UART_CR_RTS (1 << 11) 82 #define UART_CR_DTR (1 << 10) 83 #define UART_CR_RXE (1 << 9) 84 #define UART_CR_TXE (1 << 8) 85 #define UART_CR_LPE (1 << 7) 86 #define UART_CR_OVSFACT (1 << 3) 87 #define UART_CR_UARTEN (1 << 0) 88 89 #define UART_IMSC_RXIM (1 << 4) 90 91 void pl011_flush(vaddr_t base) 92 { 93 while (!(read32(base + UART_FR) & UART_FR_TXFE)) 94 ; 95 } 96 97 void pl011_init(vaddr_t base, uint32_t uart_clk, uint32_t baud_rate) 98 { 99 if (baud_rate) { 100 uint32_t divisor = (uart_clk * 4) / baud_rate; 101 102 write32(divisor >> 6, base + UART_IBRD); 103 write32(divisor & 0x3f, base + UART_FBRD); 104 } 105 106 write32(0, base + UART_RSR_ECR); 107 108 /* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */ 109 write32(UART_LCRH_WLEN_8, base + UART_LCR_H); 110 111 write32(UART_IMSC_RXIM, base + UART_IMSC); 112 113 /* Enable UART and TX */ 114 write32(UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE, base + UART_CR); 115 116 pl011_flush(base); 117 } 118 119 void pl011_putc(int ch, vaddr_t base) 120 { 121 /* 122 * Wait until there is space in the FIFO 123 */ 124 while (read32(base + UART_FR) & UART_FR_TXFF) 125 ; 126 127 /* Send the character */ 128 write32(ch, base + UART_DR); 129 } 130 131 bool pl011_have_rx_data(vaddr_t base) 132 { 133 return !(read32(base + UART_FR) & UART_FR_RXFE); 134 } 135 136 int pl011_getchar(vaddr_t base) 137 { 138 while (!pl011_have_rx_data(base)) 139 ; 140 return read32(base + UART_DR) & 0xff; 141 } 142 143