1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014, Linaro Limited 4 */ 5 #include <assert.h> 6 #include <drivers/pl011.h> 7 #include <io.h> 8 #include <keep.h> 9 #include <kernel/dt.h> 10 #include <stdlib.h> 11 #include <trace.h> 12 #include <types_ext.h> 13 #include <util.h> 14 15 #define UART_DR 0x00 /* data register */ 16 #define UART_RSR_ECR 0x04 /* receive status or error clear */ 17 #define UART_DMAWM 0x08 /* DMA watermark configure */ 18 #define UART_TIMEOUT 0x0C /* Timeout period */ 19 /* reserved space */ 20 #define UART_FR 0x18 /* flag register */ 21 #define UART_ILPR 0x20 /* IrDA low-poer */ 22 #define UART_IBRD 0x24 /* integer baud register */ 23 #define UART_FBRD 0x28 /* fractional baud register */ 24 #define UART_LCR_H 0x2C /* line control register */ 25 #define UART_CR 0x30 /* control register */ 26 #define UART_IFLS 0x34 /* interrupt FIFO level select */ 27 #define UART_IMSC 0x38 /* interrupt mask set/clear */ 28 #define UART_RIS 0x3C /* raw interrupt register */ 29 #define UART_MIS 0x40 /* masked interrupt register */ 30 #define UART_ICR 0x44 /* interrupt clear register */ 31 #define UART_DMACR 0x48 /* DMA control register */ 32 33 /* flag register bits */ 34 #define UART_FR_RTXDIS (1 << 13) 35 #define UART_FR_TERI (1 << 12) 36 #define UART_FR_DDCD (1 << 11) 37 #define UART_FR_DDSR (1 << 10) 38 #define UART_FR_DCTS (1 << 9) 39 #define UART_FR_RI (1 << 8) 40 #define UART_FR_TXFE (1 << 7) 41 #define UART_FR_RXFF (1 << 6) 42 #define UART_FR_TXFF (1 << 5) 43 #define UART_FR_RXFE (1 << 4) 44 #define UART_FR_BUSY (1 << 3) 45 #define UART_FR_DCD (1 << 2) 46 #define UART_FR_DSR (1 << 1) 47 #define UART_FR_CTS (1 << 0) 48 49 /* transmit/receive line register bits */ 50 #define UART_LCRH_SPS (1 << 7) 51 #define UART_LCRH_WLEN_8 (3 << 5) 52 #define UART_LCRH_WLEN_7 (2 << 5) 53 #define UART_LCRH_WLEN_6 (1 << 5) 54 #define UART_LCRH_WLEN_5 (0 << 5) 55 #define UART_LCRH_FEN (1 << 4) 56 #define UART_LCRH_STP2 (1 << 3) 57 #define UART_LCRH_EPS (1 << 2) 58 #define UART_LCRH_PEN (1 << 1) 59 #define UART_LCRH_BRK (1 << 0) 60 61 /* control register bits */ 62 #define UART_CR_CTSEN (1 << 15) 63 #define UART_CR_RTSEN (1 << 14) 64 #define UART_CR_OUT2 (1 << 13) 65 #define UART_CR_OUT1 (1 << 12) 66 #define UART_CR_RTS (1 << 11) 67 #define UART_CR_DTR (1 << 10) 68 #define UART_CR_RXE (1 << 9) 69 #define UART_CR_TXE (1 << 8) 70 #define UART_CR_LPE (1 << 7) 71 #define UART_CR_OVSFACT (1 << 3) 72 #define UART_CR_UARTEN (1 << 0) 73 74 #define UART_IMSC_RTIM (1 << 6) 75 #define UART_IMSC_RXIM (1 << 4) 76 77 static vaddr_t chip_to_base(struct serial_chip *chip) 78 { 79 struct pl011_data *pd = 80 container_of(chip, struct pl011_data, chip); 81 82 return io_pa_or_va(&pd->base); 83 } 84 85 static void pl011_flush(struct serial_chip *chip) 86 { 87 vaddr_t base = chip_to_base(chip); 88 89 /* 90 * Wait for the transmit FIFO to be empty. 91 * It can happen that Linux initializes the OP-TEE driver with the 92 * console UART disabled; avoid an infinite loop by checking the UART 93 * enabled flag. Checking it in the loop makes the code safe against 94 * asynchronous disable. 95 */ 96 while ((io_read32(base + UART_CR) & UART_CR_UARTEN) && 97 !(io_read32(base + UART_FR) & UART_FR_TXFE)) 98 ; 99 } 100 101 static bool pl011_have_rx_data(struct serial_chip *chip) 102 { 103 vaddr_t base = chip_to_base(chip); 104 105 return !(io_read32(base + UART_FR) & UART_FR_RXFE); 106 } 107 108 static int pl011_getchar(struct serial_chip *chip) 109 { 110 vaddr_t base = chip_to_base(chip); 111 112 while (!pl011_have_rx_data(chip)) 113 ; 114 return io_read32(base + UART_DR) & 0xff; 115 } 116 117 static void pl011_putc(struct serial_chip *chip, int ch) 118 { 119 vaddr_t base = chip_to_base(chip); 120 121 /* Wait until there is space in the FIFO or device is disabled */ 122 while (io_read32(base + UART_FR) & UART_FR_TXFF) 123 ; 124 125 /* Send the character */ 126 io_write32(base + UART_DR, ch); 127 } 128 129 static const struct serial_ops pl011_ops = { 130 .flush = pl011_flush, 131 .getchar = pl011_getchar, 132 .have_rx_data = pl011_have_rx_data, 133 .putc = pl011_putc, 134 }; 135 KEEP_PAGER(pl011_ops); 136 137 void pl011_init(struct pl011_data *pd, paddr_t pbase, uint32_t uart_clk, 138 uint32_t baud_rate) 139 { 140 vaddr_t base; 141 142 pd->base.pa = pbase; 143 pd->chip.ops = &pl011_ops; 144 145 base = io_pa_or_va(&pd->base); 146 147 /* Clear all errors */ 148 io_write32(base + UART_RSR_ECR, 0); 149 /* Disable everything */ 150 io_write32(base + UART_CR, 0); 151 152 if (baud_rate) { 153 uint32_t divisor = (uart_clk * 4) / baud_rate; 154 155 io_write32(base + UART_IBRD, divisor >> 6); 156 io_write32(base + UART_FBRD, divisor & 0x3f); 157 } 158 159 /* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */ 160 io_write32(base + UART_LCR_H, UART_LCRH_WLEN_8); 161 162 /* Enable interrupts for receive and receive timeout */ 163 io_write32(base + UART_IMSC, UART_IMSC_RXIM | UART_IMSC_RTIM); 164 165 /* Enable UART and RX/TX */ 166 io_write32(base + UART_CR, UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE); 167 168 pl011_flush(&pd->chip); 169 } 170 171 #ifdef CFG_DT 172 173 static struct serial_chip *pl011_dev_alloc(void) 174 { 175 struct pl011_data *pd = nex_calloc(1, sizeof(*pd)); 176 177 if (!pd) 178 return NULL; 179 return &pd->chip; 180 } 181 182 static int pl011_dev_init(struct serial_chip *chip, const void *fdt, int offs, 183 const char *parms) 184 { 185 struct pl011_data *pd = container_of(chip, struct pl011_data, chip); 186 vaddr_t vbase; 187 paddr_t pbase; 188 size_t size; 189 190 if (parms && parms[0]) 191 IMSG("pl011: device parameters ignored (%s)", parms); 192 193 if (dt_map_dev(fdt, offs, &vbase, &size) < 0) 194 return -1; 195 196 if (size != 0x1000) { 197 EMSG("pl011: unexpected register size: %zx", size); 198 return -1; 199 } 200 201 pbase = virt_to_phys((void *)vbase); 202 pl011_init(pd, pbase, 0, 0); 203 204 return 0; 205 } 206 207 static void pl011_dev_free(struct serial_chip *chip) 208 { 209 struct pl011_data *pd = container_of(chip, struct pl011_data, chip); 210 211 nex_free(pd); 212 } 213 214 static const struct serial_driver pl011_driver = { 215 .dev_alloc = pl011_dev_alloc, 216 .dev_init = pl011_dev_init, 217 .dev_free = pl011_dev_free, 218 }; 219 220 static const struct dt_device_match pl011_match_table[] = { 221 { .compatible = "arm,pl011" }, 222 { 0 } 223 }; 224 225 const struct dt_driver pl011_dt_driver __dt_driver = { 226 .name = "pl011", 227 .match_table = pl011_match_table, 228 .driver = &pl011_driver, 229 }; 230 231 #endif /* CFG_DT */ 232