1 /* 2 * Copyright (c) 2014, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <assert.h> 28 #include <drivers/pl011.h> 29 #include <io.h> 30 #include <keep.h> 31 #include <util.h> 32 33 #define UART_DR 0x00 /* data register */ 34 #define UART_RSR_ECR 0x04 /* receive status or error clear */ 35 #define UART_DMAWM 0x08 /* DMA watermark configure */ 36 #define UART_TIMEOUT 0x0C /* Timeout period */ 37 /* reserved space */ 38 #define UART_FR 0x18 /* flag register */ 39 #define UART_ILPR 0x20 /* IrDA low-poer */ 40 #define UART_IBRD 0x24 /* integer baud register */ 41 #define UART_FBRD 0x28 /* fractional baud register */ 42 #define UART_LCR_H 0x2C /* line control register */ 43 #define UART_CR 0x30 /* control register */ 44 #define UART_IFLS 0x34 /* interrupt FIFO level select */ 45 #define UART_IMSC 0x38 /* interrupt mask set/clear */ 46 #define UART_RIS 0x3C /* raw interrupt register */ 47 #define UART_MIS 0x40 /* masked interrupt register */ 48 #define UART_ICR 0x44 /* interrupt clear register */ 49 #define UART_DMACR 0x48 /* DMA control register */ 50 51 /* flag register bits */ 52 #define UART_FR_RTXDIS (1 << 13) 53 #define UART_FR_TERI (1 << 12) 54 #define UART_FR_DDCD (1 << 11) 55 #define UART_FR_DDSR (1 << 10) 56 #define UART_FR_DCTS (1 << 9) 57 #define UART_FR_RI (1 << 8) 58 #define UART_FR_TXFE (1 << 7) 59 #define UART_FR_RXFF (1 << 6) 60 #define UART_FR_TXFF (1 << 5) 61 #define UART_FR_RXFE (1 << 4) 62 #define UART_FR_BUSY (1 << 3) 63 #define UART_FR_DCD (1 << 2) 64 #define UART_FR_DSR (1 << 1) 65 #define UART_FR_CTS (1 << 0) 66 67 /* transmit/receive line register bits */ 68 #define UART_LCRH_SPS (1 << 7) 69 #define UART_LCRH_WLEN_8 (3 << 5) 70 #define UART_LCRH_WLEN_7 (2 << 5) 71 #define UART_LCRH_WLEN_6 (1 << 5) 72 #define UART_LCRH_WLEN_5 (0 << 5) 73 #define UART_LCRH_FEN (1 << 4) 74 #define UART_LCRH_STP2 (1 << 3) 75 #define UART_LCRH_EPS (1 << 2) 76 #define UART_LCRH_PEN (1 << 1) 77 #define UART_LCRH_BRK (1 << 0) 78 79 /* control register bits */ 80 #define UART_CR_CTSEN (1 << 15) 81 #define UART_CR_RTSEN (1 << 14) 82 #define UART_CR_OUT2 (1 << 13) 83 #define UART_CR_OUT1 (1 << 12) 84 #define UART_CR_RTS (1 << 11) 85 #define UART_CR_DTR (1 << 10) 86 #define UART_CR_RXE (1 << 9) 87 #define UART_CR_TXE (1 << 8) 88 #define UART_CR_LPE (1 << 7) 89 #define UART_CR_OVSFACT (1 << 3) 90 #define UART_CR_UARTEN (1 << 0) 91 92 #define UART_IMSC_RTIM (1 << 6) 93 #define UART_IMSC_RXIM (1 << 4) 94 95 static vaddr_t chip_to_base(struct serial_chip *chip) 96 { 97 struct pl011_data *pd = 98 container_of(chip, struct pl011_data, chip); 99 100 return io_pa_or_va(&pd->base); 101 } 102 103 static void pl011_flush(struct serial_chip *chip) 104 { 105 vaddr_t base = chip_to_base(chip); 106 107 while (!(read32(base + UART_FR) & UART_FR_TXFE)) 108 ; 109 } 110 111 static bool pl011_have_rx_data(struct serial_chip *chip) 112 { 113 vaddr_t base = chip_to_base(chip); 114 115 return !(read32(base + UART_FR) & UART_FR_RXFE); 116 } 117 118 static int pl011_getchar(struct serial_chip *chip) 119 { 120 vaddr_t base = chip_to_base(chip); 121 122 while (!pl011_have_rx_data(chip)) 123 ; 124 return read32(base + UART_DR) & 0xff; 125 } 126 127 static void pl011_putc(struct serial_chip *chip, int ch) 128 { 129 vaddr_t base = chip_to_base(chip); 130 131 /* Wait until there is space in the FIFO */ 132 while (read32(base + UART_FR) & UART_FR_TXFF) 133 ; 134 135 /* Send the character */ 136 write32(ch, base + UART_DR); 137 } 138 139 static const struct serial_ops pl011_ops = { 140 .flush = pl011_flush, 141 .getchar = pl011_getchar, 142 .have_rx_data = pl011_have_rx_data, 143 .putc = pl011_putc, 144 }; 145 KEEP_PAGER(pl011_ops); 146 147 void pl011_init(struct pl011_data *pd, paddr_t base, uint32_t uart_clk, 148 uint32_t baud_rate) 149 { 150 pd->base.pa = base; 151 pd->chip.ops = &pl011_ops; 152 153 /* Clear all errors */ 154 write32(0, base + UART_RSR_ECR); 155 /* Disable everything */ 156 write32(0, base + UART_CR); 157 158 if (baud_rate) { 159 uint32_t divisor = (uart_clk * 4) / baud_rate; 160 161 write32(divisor >> 6, base + UART_IBRD); 162 write32(divisor & 0x3f, base + UART_FBRD); 163 } 164 165 /* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */ 166 write32(UART_LCRH_WLEN_8, base + UART_LCR_H); 167 168 /* Enable interrupts for receive and receive timeout */ 169 write32(UART_IMSC_RXIM | UART_IMSC_RTIM, base + UART_IMSC); 170 171 /* Enable UART and RX/TX */ 172 write32(UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE, base + UART_CR); 173 174 pl011_flush(&pd->chip); 175 } 176 177