1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014, Linaro Limited 4 */ 5 #include <assert.h> 6 #include <drivers/pl011.h> 7 #include <io.h> 8 #include <keep.h> 9 #include <kernel/dt.h> 10 #include <kernel/dt_driver.h> 11 #include <stdlib.h> 12 #include <trace.h> 13 #include <types_ext.h> 14 #include <util.h> 15 16 #define UART_DR 0x00 /* data register */ 17 #define UART_RSR_ECR 0x04 /* receive status or error clear */ 18 #define UART_DMAWM 0x08 /* DMA watermark configure */ 19 #define UART_TIMEOUT 0x0C /* Timeout period */ 20 /* reserved space */ 21 #define UART_FR 0x18 /* flag register */ 22 #define UART_ILPR 0x20 /* IrDA low-poer */ 23 #define UART_IBRD 0x24 /* integer baud register */ 24 #define UART_FBRD 0x28 /* fractional baud register */ 25 #define UART_LCR_H 0x2C /* line control register */ 26 #define UART_CR 0x30 /* control register */ 27 #define UART_IFLS 0x34 /* interrupt FIFO level select */ 28 #define UART_IMSC 0x38 /* interrupt mask set/clear */ 29 #define UART_RIS 0x3C /* raw interrupt register */ 30 #define UART_MIS 0x40 /* masked interrupt register */ 31 #define UART_ICR 0x44 /* interrupt clear register */ 32 #define UART_DMACR 0x48 /* DMA control register */ 33 34 /* flag register bits */ 35 #define UART_FR_RTXDIS (1 << 13) 36 #define UART_FR_TERI (1 << 12) 37 #define UART_FR_DDCD (1 << 11) 38 #define UART_FR_DDSR (1 << 10) 39 #define UART_FR_DCTS (1 << 9) 40 #define UART_FR_RI (1 << 8) 41 #define UART_FR_TXFE (1 << 7) 42 #define UART_FR_RXFF (1 << 6) 43 #define UART_FR_TXFF (1 << 5) 44 #define UART_FR_RXFE (1 << 4) 45 #define UART_FR_BUSY (1 << 3) 46 #define UART_FR_DCD (1 << 2) 47 #define UART_FR_DSR (1 << 1) 48 #define UART_FR_CTS (1 << 0) 49 50 /* transmit/receive line register bits */ 51 #define UART_LCRH_SPS (1 << 7) 52 #define UART_LCRH_WLEN_8 (3 << 5) 53 #define UART_LCRH_WLEN_7 (2 << 5) 54 #define UART_LCRH_WLEN_6 (1 << 5) 55 #define UART_LCRH_WLEN_5 (0 << 5) 56 #define UART_LCRH_FEN (1 << 4) 57 #define UART_LCRH_STP2 (1 << 3) 58 #define UART_LCRH_EPS (1 << 2) 59 #define UART_LCRH_PEN (1 << 1) 60 #define UART_LCRH_BRK (1 << 0) 61 62 /* control register bits */ 63 #define UART_CR_CTSEN (1 << 15) 64 #define UART_CR_RTSEN (1 << 14) 65 #define UART_CR_OUT2 (1 << 13) 66 #define UART_CR_OUT1 (1 << 12) 67 #define UART_CR_RTS (1 << 11) 68 #define UART_CR_DTR (1 << 10) 69 #define UART_CR_RXE (1 << 9) 70 #define UART_CR_TXE (1 << 8) 71 #define UART_CR_LPE (1 << 7) 72 #define UART_CR_OVSFACT (1 << 3) 73 #define UART_CR_UARTEN (1 << 0) 74 75 #define UART_IMSC_RTIM (1 << 6) 76 #define UART_IMSC_RXIM (1 << 4) 77 78 static vaddr_t chip_to_base(struct serial_chip *chip) 79 { 80 struct pl011_data *pd = 81 container_of(chip, struct pl011_data, chip); 82 83 return io_pa_or_va(&pd->base, PL011_REG_SIZE); 84 } 85 86 static void pl011_flush(struct serial_chip *chip) 87 { 88 vaddr_t base = chip_to_base(chip); 89 90 /* 91 * Wait for the transmit FIFO to be empty. 92 * It can happen that Linux initializes the OP-TEE driver with the 93 * console UART disabled; avoid an infinite loop by checking the UART 94 * enabled flag. Checking it in the loop makes the code safe against 95 * asynchronous disable. 96 */ 97 while ((io_read32(base + UART_CR) & UART_CR_UARTEN) && 98 !(io_read32(base + UART_FR) & UART_FR_TXFE)) 99 ; 100 } 101 102 static bool pl011_have_rx_data(struct serial_chip *chip) 103 { 104 vaddr_t base = chip_to_base(chip); 105 106 return !(io_read32(base + UART_FR) & UART_FR_RXFE); 107 } 108 109 static int pl011_getchar(struct serial_chip *chip) 110 { 111 vaddr_t base = chip_to_base(chip); 112 113 while (!pl011_have_rx_data(chip)) 114 ; 115 return io_read32(base + UART_DR) & 0xff; 116 } 117 118 static void pl011_putc(struct serial_chip *chip, int ch) 119 { 120 vaddr_t base = chip_to_base(chip); 121 122 /* Wait until there is space in the FIFO or device is disabled */ 123 while (io_read32(base + UART_FR) & UART_FR_TXFF) 124 ; 125 126 /* Send the character */ 127 io_write32(base + UART_DR, ch); 128 } 129 130 static const struct serial_ops pl011_ops = { 131 .flush = pl011_flush, 132 .getchar = pl011_getchar, 133 .have_rx_data = pl011_have_rx_data, 134 .putc = pl011_putc, 135 }; 136 DECLARE_KEEP_PAGER(pl011_ops); 137 138 void pl011_init(struct pl011_data *pd, paddr_t pbase, uint32_t uart_clk, 139 uint32_t baud_rate) 140 { 141 vaddr_t base; 142 143 pd->base.pa = pbase; 144 pd->chip.ops = &pl011_ops; 145 146 base = io_pa_or_va(&pd->base, PL011_REG_SIZE); 147 148 /* Clear all errors */ 149 io_write32(base + UART_RSR_ECR, 0); 150 /* Disable everything */ 151 io_write32(base + UART_CR, 0); 152 153 if (baud_rate) { 154 uint32_t divisor = (uart_clk * 4) / baud_rate; 155 156 io_write32(base + UART_IBRD, divisor >> 6); 157 io_write32(base + UART_FBRD, divisor & 0x3f); 158 } 159 160 /* Configure TX to 8 bits, 1 stop bit, no parity, fifo disabled. */ 161 io_write32(base + UART_LCR_H, UART_LCRH_WLEN_8); 162 163 /* Enable interrupts for receive and receive timeout */ 164 io_write32(base + UART_IMSC, UART_IMSC_RXIM | UART_IMSC_RTIM); 165 166 /* Enable UART and RX/TX */ 167 io_write32(base + UART_CR, UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE); 168 169 pl011_flush(&pd->chip); 170 } 171 172 #ifdef CFG_DT 173 174 static struct serial_chip *pl011_dev_alloc(void) 175 { 176 struct pl011_data *pd = nex_calloc(1, sizeof(*pd)); 177 178 if (!pd) 179 return NULL; 180 return &pd->chip; 181 } 182 183 static int pl011_dev_init(struct serial_chip *chip, const void *fdt, int offs, 184 const char *parms) 185 { 186 struct pl011_data *pd = container_of(chip, struct pl011_data, chip); 187 vaddr_t vbase; 188 paddr_t pbase; 189 size_t size; 190 191 if (parms && parms[0]) 192 IMSG("pl011: device parameters ignored (%s)", parms); 193 194 if (dt_map_dev(fdt, offs, &vbase, &size, DT_MAP_AUTO) < 0) 195 return -1; 196 197 if (size != 0x1000) { 198 EMSG("pl011: unexpected register size: %zx", size); 199 return -1; 200 } 201 202 pbase = virt_to_phys((void *)vbase); 203 pl011_init(pd, pbase, 0, 0); 204 205 return 0; 206 } 207 208 static void pl011_dev_free(struct serial_chip *chip) 209 { 210 struct pl011_data *pd = container_of(chip, struct pl011_data, chip); 211 212 nex_free(pd); 213 } 214 215 static const struct serial_driver pl011_driver = { 216 .dev_alloc = pl011_dev_alloc, 217 .dev_init = pl011_dev_init, 218 .dev_free = pl011_dev_free, 219 }; 220 221 static const struct dt_device_match pl011_match_table[] = { 222 { .compatible = "arm,pl011" }, 223 { 0 } 224 }; 225 226 DEFINE_DT_DRIVER(pl011_dt_driver) = { 227 .name = "pl011", 228 .type = DT_DRIVER_UART, 229 .match_table = pl011_match_table, 230 .driver = &pl011_driver, 231 }; 232 233 #endif /* CFG_DT */ 234