1*85278139SSumit Garg /* 2*85278139SSumit Garg * Copyright (C) 2015 Freescale Semiconductor, Inc. 3*85278139SSumit Garg * All rights reserved. 4*85278139SSumit Garg * 5*85278139SSumit Garg * Redistribution and use in source and binary forms, with or without 6*85278139SSumit Garg * modification, are permitted provided that the following conditions are met: 7*85278139SSumit Garg * 8*85278139SSumit Garg * 1. Redistributions of source code must retain the above copyright notice, 9*85278139SSumit Garg * this list of conditions and the following disclaimer. 10*85278139SSumit Garg * 11*85278139SSumit Garg * 2. Redistributions in binary form must reproduce the above copyright notice, 12*85278139SSumit Garg * this list of conditions and the following disclaimer in the documentation 13*85278139SSumit Garg * and/or other materials provided with the distribution. 14*85278139SSumit Garg * 15*85278139SSumit Garg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16*85278139SSumit Garg * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*85278139SSumit Garg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*85278139SSumit Garg * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19*85278139SSumit Garg * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20*85278139SSumit Garg * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21*85278139SSumit Garg * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22*85278139SSumit Garg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23*85278139SSumit Garg * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24*85278139SSumit Garg * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25*85278139SSumit Garg * POSSIBILITY OF SUCH DAMAGE. 26*85278139SSumit Garg */ 27*85278139SSumit Garg 28*85278139SSumit Garg #include <drivers/ns16550.h> 29*85278139SSumit Garg #include <io.h> 30*85278139SSumit Garg 31*85278139SSumit Garg /* uart register defines */ 32*85278139SSumit Garg #define UART_RBR 0x0 33*85278139SSumit Garg #define UART_THR 0x0 34*85278139SSumit Garg #define UART_IER 0x1 35*85278139SSumit Garg #define UART_FCR 0x2 36*85278139SSumit Garg #define UART_LCR 0x3 37*85278139SSumit Garg #define UART_MCR 0x4 38*85278139SSumit Garg #define UART_LSR 0x5 39*85278139SSumit Garg #define UART_MSR 0x6 40*85278139SSumit Garg #define UART_SPR 0x7 41*85278139SSumit Garg 42*85278139SSumit Garg /* uart status register bits */ 43*85278139SSumit Garg #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 44*85278139SSumit Garg 45*85278139SSumit Garg void ns16550_flush(vaddr_t base) 46*85278139SSumit Garg { 47*85278139SSumit Garg while ((read8(base + UART_LSR) & UART_LSR_THRE) == 0) 48*85278139SSumit Garg ; 49*85278139SSumit Garg } 50*85278139SSumit Garg 51*85278139SSumit Garg void ns16550_putc(int ch, vaddr_t base) 52*85278139SSumit Garg { 53*85278139SSumit Garg ns16550_flush(base); 54*85278139SSumit Garg 55*85278139SSumit Garg /* write out charset to Transmit-hold-register */ 56*85278139SSumit Garg write8(ch, base + UART_THR); 57*85278139SSumit Garg } 58