xref: /optee_os/core/drivers/ns16550.c (revision 2e5aa31ba0454b74d619671061093ebfcf913aec)
185278139SSumit Garg /*
285278139SSumit Garg  * Copyright (C) 2015 Freescale Semiconductor, Inc.
3*2e5aa31bSJerome Forissier  * Copyright (c) 2017, Linaro Limited
485278139SSumit Garg  * All rights reserved.
585278139SSumit Garg  *
685278139SSumit Garg  * Redistribution and use in source and binary forms, with or without
785278139SSumit Garg  * modification, are permitted provided that the following conditions are met:
885278139SSumit Garg  *
985278139SSumit Garg  * 1. Redistributions of source code must retain the above copyright notice,
1085278139SSumit Garg  * this list of conditions and the following disclaimer.
1185278139SSumit Garg  *
1285278139SSumit Garg  * 2. Redistributions in binary form must reproduce the above copyright notice,
1385278139SSumit Garg  * this list of conditions and the following disclaimer in the documentation
1485278139SSumit Garg  * and/or other materials provided with the distribution.
1585278139SSumit Garg  *
1685278139SSumit Garg  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1785278139SSumit Garg  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1885278139SSumit Garg  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1985278139SSumit Garg  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
2085278139SSumit Garg  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2185278139SSumit Garg  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2285278139SSumit Garg  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2385278139SSumit Garg  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2485278139SSumit Garg  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2585278139SSumit Garg  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2685278139SSumit Garg  * POSSIBILITY OF SUCH DAMAGE.
2785278139SSumit Garg  */
2885278139SSumit Garg 
2985278139SSumit Garg #include <drivers/ns16550.h>
3085278139SSumit Garg #include <io.h>
31*2e5aa31bSJerome Forissier #include <util.h>
3285278139SSumit Garg 
3385278139SSumit Garg /* uart register defines */
3485278139SSumit Garg #define UART_RBR	0x0
3585278139SSumit Garg #define UART_THR	0x0
3685278139SSumit Garg #define UART_IER	0x1
3785278139SSumit Garg #define UART_FCR	0x2
3885278139SSumit Garg #define UART_LCR	0x3
3985278139SSumit Garg #define UART_MCR	0x4
4085278139SSumit Garg #define UART_LSR	0x5
4185278139SSumit Garg #define UART_MSR	0x6
4285278139SSumit Garg #define UART_SPR	0x7
4385278139SSumit Garg 
4485278139SSumit Garg /* uart status register bits */
4585278139SSumit Garg #define UART_LSR_THRE	0x20 /* Transmit-hold-register empty */
4685278139SSumit Garg 
47*2e5aa31bSJerome Forissier static vaddr_t chip_to_base(struct serial_chip *chip)
4885278139SSumit Garg {
49*2e5aa31bSJerome Forissier 	struct ns16550_data *pd =
50*2e5aa31bSJerome Forissier 		container_of(chip, struct ns16550_data, chip);
51*2e5aa31bSJerome Forissier 
52*2e5aa31bSJerome Forissier 	return io_pa_or_va(&pd->base);
53*2e5aa31bSJerome Forissier }
54*2e5aa31bSJerome Forissier 
55*2e5aa31bSJerome Forissier static void ns16550_flush(struct serial_chip *chip)
56*2e5aa31bSJerome Forissier {
57*2e5aa31bSJerome Forissier 	vaddr_t base = chip_to_base(chip);
58*2e5aa31bSJerome Forissier 
5985278139SSumit Garg 	while ((read8(base + UART_LSR) & UART_LSR_THRE) == 0)
6085278139SSumit Garg 		;
6185278139SSumit Garg }
6285278139SSumit Garg 
63*2e5aa31bSJerome Forissier static void ns16550_putc(struct serial_chip *chip, int ch)
6485278139SSumit Garg {
65*2e5aa31bSJerome Forissier 	vaddr_t base = chip_to_base(chip);
66*2e5aa31bSJerome Forissier 
67*2e5aa31bSJerome Forissier 	ns16550_flush(chip);
6885278139SSumit Garg 
6985278139SSumit Garg 	/* write out charset to Transmit-hold-register */
7085278139SSumit Garg 	write8(ch, base + UART_THR);
7185278139SSumit Garg }
72*2e5aa31bSJerome Forissier 
73*2e5aa31bSJerome Forissier static const struct serial_ops ns16550_ops = {
74*2e5aa31bSJerome Forissier 	.flush = ns16550_flush,
75*2e5aa31bSJerome Forissier 	.putc = ns16550_putc,
76*2e5aa31bSJerome Forissier };
77*2e5aa31bSJerome Forissier 
78*2e5aa31bSJerome Forissier void ns16550_init(struct ns16550_data *pd, paddr_t base)
79*2e5aa31bSJerome Forissier {
80*2e5aa31bSJerome Forissier 	pd->base.pa = base;
81*2e5aa31bSJerome Forissier 	pd->chip.ops = &ns16550_ops;
82*2e5aa31bSJerome Forissier 
83*2e5aa31bSJerome Forissier 	/*
84*2e5aa31bSJerome Forissier 	 * Do nothing, uart driver shared with normal world,
85*2e5aa31bSJerome Forissier 	 * everything for uart driver initialization is done in bootloader.
86*2e5aa31bSJerome Forissier 	 */
87*2e5aa31bSJerome Forissier }
88