1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2021 NXP 4 * 5 * I2C driver for I2C Controller 6 * 7 */ 8 #include <assert.h> 9 #include <drivers/ls_i2c.h> 10 #include <io.h> 11 #include <kernel/boot.h> 12 #include <kernel/dt.h> 13 #include <kernel/delay.h> 14 #include <libfdt.h> 15 #include <mm/core_memprot.h> 16 #include <string.h> 17 18 static const char * const i2c_controller_map[] = { 19 "/soc/i2c@2000000", "/soc/i2c@2010000", "/soc/i2c@2020000", 20 "/soc/i2c@2030000", "/soc/i2c@2040000", "/soc/i2c@2050000", 21 "/soc/i2c@2060000", "/soc/i2c@2070000" 22 }; 23 24 /* 25 * I2C divisor and ibfd register values when glitch filter is enabled 26 * In case of duplicate SCL divisor value, the ibfd value with high MUL value 27 * has been selected. A higher MUL value results in a lower sampling rate of 28 * the I2C signals. This gives the I2C module greater immunity against glitches 29 * in the I2C signals. 30 */ 31 static const struct i2c_clock_divisor_pair clk_div_glitch_enabled[] = { 32 { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 }, 33 { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA }, 34 { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 }, 35 { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 }, 36 { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A }, 37 { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 }, 38 { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 }, 39 { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A }, 40 { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 }, 41 { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 }, 42 { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 }, 43 { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D }, 44 { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 }, 45 { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 }, 46 { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC }, 47 { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF }, 48 { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 }, 49 { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC }, 50 { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF } 51 }; 52 53 /* 54 * I2C divisor and ibfd register values when glitch filter is disabled. 55 * In case of duplicate SCL divisor value, the ibfd value with high MUL value 56 * has been selected. A higher MUL value results in a lower sampling rate of 57 * the I2C signals. This gives the I2C module greater immunity against glitches 58 * in the I2C signals. 59 */ 60 static const struct i2c_clock_divisor_pair clk_div_glitch_disabled[] = { 61 { 20, 0x0 }, { 22, 0x1 }, { 24, 0x2 }, { 26, 0x3 }, 62 { 28, 0x8 }, { 30, 0x5 }, { 32, 0x9 }, { 34, 0x6 }, 63 { 36, 0x0A }, { 40, 0x40 }, { 44, 0x41 }, { 48, 0x42 }, 64 { 52, 0x43 }, { 56, 0x48 }, { 60, 0x45 }, { 64, 0x49 }, 65 { 68, 0x46 }, { 72, 0x4A }, { 80, 0x80 }, { 88, 0x81 }, 66 { 96, 0x82 }, { 104, 0x83 }, { 112, 0x88 }, { 120, 0x85 }, 67 { 128, 0x89 }, { 136, 0x86 }, { 144, 0x8A }, { 160, 0x8B }, 68 { 176, 0x8C }, { 192, 0x90 }, { 208, 0x56 }, { 224, 0x91 }, 69 { 240, 0x1F }, { 256, 0x92 }, { 272, 0x8F }, { 288, 0x93 }, 70 { 320, 0x98 }, { 352, 0x95 }, { 384, 0x99 }, { 416, 0x96 }, 71 { 448, 0x9A }, { 480, 0x5F }, { 512, 0x9B }, { 576, 0x9C }, 72 { 640, 0xA0 }, { 768, 0xA1 }, { 896, 0xA2 }, { 960, 0x9F }, 73 { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 }, 74 { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC }, 75 { 2560, 0xAD }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF }, 76 { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 }, 77 { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC }, 78 { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF } 79 }; 80 81 void i2c_reset(vaddr_t base) 82 { 83 struct i2c_regs *regs = (struct i2c_regs *)base; 84 85 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_MDIS); 86 io_setbits8((vaddr_t)®s->ibsr, I2C_IBSR_IBAL | I2C_IBSR_IBIF); 87 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_IBIE | I2C_IBCR_DMAEN); 88 io_clrbits8((vaddr_t)®s->ibic, I2C_IBIC_BIIE); 89 } 90 91 /* 92 * Get I2c Bus Frequency Divider Register value based on clock_divisor 93 * and if the glitch is enabled or not in I2c controller. 94 * base Base address of I2C controller 95 * clock_divisor Clock Divisor 96 */ 97 static uint8_t i2c_get_ibfd(vaddr_t base, uint16_t clock_divisor) 98 { 99 struct i2c_regs *regs = (struct i2c_regs *)base; 100 const struct i2c_clock_divisor_pair *dpair = NULL; 101 size_t dpair_sz = 0; 102 unsigned int n = 0; 103 104 if (io_read8((vaddr_t)®s->ibdbg) & I2C_IBDBG_GLFLT_EN) { 105 dpair = clk_div_glitch_enabled; 106 dpair_sz = ARRAY_SIZE(clk_div_glitch_enabled); 107 } else { 108 dpair = clk_div_glitch_disabled; 109 dpair_sz = ARRAY_SIZE(clk_div_glitch_disabled); 110 } 111 112 for (n = 0; n < dpair_sz - 1; n++) 113 if (clock_divisor < dpair[n].divisor) 114 break; 115 116 return dpair[n].ibfd; 117 } 118 119 TEE_Result i2c_init(struct ls_i2c_data *i2c_data) 120 { 121 struct i2c_regs *regs = NULL; 122 uint16_t clock_divisor = 0; 123 uint8_t ibfd = 0; /* I2c Bus Frequency Divider Register */ 124 size_t size = 0; 125 int node = 0; 126 vaddr_t ctrl_base = 0; 127 void *fdt = NULL; 128 129 /* 130 * First get the I2C Controller base address from the DTB 131 * if DTB present and if the I2C Controller defined in it. 132 */ 133 fdt = get_embedded_dt(); 134 if (!fdt) { 135 EMSG("Unable to get the Embedded DTB, I2C init failed\n"); 136 return TEE_ERROR_GENERIC; 137 } 138 139 node = fdt_path_offset(fdt, 140 i2c_controller_map[i2c_data->i2c_controller]); 141 if (node > 0) { 142 if (dt_map_dev(fdt, node, &ctrl_base, &size, 143 DT_MAP_AUTO) < 0) { 144 EMSG("Unable to get virtual address"); 145 return TEE_ERROR_GENERIC; 146 } 147 } else { 148 EMSG("Unable to get I2C offset node"); 149 return TEE_ERROR_ITEM_NOT_FOUND; 150 } 151 152 i2c_data->base = ctrl_base; 153 154 regs = (struct i2c_regs *)ctrl_base; 155 156 clock_divisor = (i2c_data->i2c_bus_clock + i2c_data->speed - 1) / 157 i2c_data->speed; 158 ibfd = i2c_get_ibfd(ctrl_base, clock_divisor); 159 160 io_write8((vaddr_t)®s->ibfd, ibfd); 161 162 i2c_reset(ctrl_base); 163 164 return TEE_SUCCESS; 165 } 166 167 /* 168 * Check if I2C bus is busy with previous transaction or not. 169 * regs pointer to I2c controller registers 170 * test_busy this flag tells if we need to check the busy bit in IBSR reg 171 */ 172 static TEE_Result i2c_bus_test_bus_busy(struct i2c_regs *regs, bool test_busy) 173 { 174 unsigned int n = 0; 175 uint8_t reg = 0; 176 177 for (n = 0; n < I2C_NUM_RETRIES; n++) { 178 reg = io_read8((vaddr_t)®s->ibsr); 179 180 if (reg & I2C_IBSR_IBAL) { 181 io_write8((vaddr_t)®s->ibsr, reg); 182 return TEE_ERROR_BUSY; 183 } 184 185 if (test_busy && (reg & I2C_IBSR_IBB)) 186 break; 187 188 if (!test_busy && !(reg & I2C_IBSR_IBB)) 189 break; 190 191 mdelay(1); 192 } 193 194 if (n == I2C_NUM_RETRIES) 195 return TEE_ERROR_BUSY; 196 197 return TEE_SUCCESS; 198 } 199 200 /* 201 * Check if data transfer to/from i2c controller is complete. 202 * regs pointer to I2c controller registers 203 * test_rx_ack this flag tells if we need to check RXAK bit in IBSR reg 204 */ 205 static TEE_Result i2c_transfer_complete(struct i2c_regs *regs, bool test_rx_ack) 206 { 207 unsigned int n = 0; 208 uint8_t reg = 0; 209 210 for (n = 0; n < I2C_NUM_RETRIES; n++) { 211 reg = io_read8((vaddr_t)®s->ibsr); 212 213 if (reg & I2C_IBSR_IBIF) { 214 /* Write 1 to clear the IBIF field */ 215 io_write8((vaddr_t)®s->ibsr, reg); 216 break; 217 } 218 mdelay(1); 219 } 220 221 if (n == I2C_NUM_RETRIES) 222 return TEE_ERROR_BUSY; 223 224 if (test_rx_ack && (reg & I2C_IBSR_RXAK)) 225 return TEE_ERROR_NO_DATA; 226 227 if (reg & I2C_IBSR_TCF) 228 return TEE_SUCCESS; 229 230 return TEE_ERROR_GENERIC; 231 } 232 233 /* 234 * Read data from I2c controller. 235 * regs pointer to I2c controller registers 236 * slave_address slave address from which to read 237 * operation pointer to i2c_operation struct 238 * is_last_operation if current operation is last operation 239 */ 240 static TEE_Result i2c_read(struct i2c_regs *regs, unsigned int slave_address, 241 struct i2c_operation *operation, 242 bool is_last_operation) 243 { 244 TEE_Result res = TEE_ERROR_GENERIC; 245 unsigned int n = 0; 246 247 /* Write Slave Address */ 248 io_write8((vaddr_t)®s->ibdr, (slave_address << 0x1) | BIT(0)); 249 res = i2c_transfer_complete(regs, I2C_BUS_TEST_RX_ACK); 250 if (res) 251 return res; 252 253 /* select Receive mode. */ 254 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_TXRX); 255 if (operation->length_in_bytes > 1) { 256 /* Set No ACK = 0 */ 257 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_NOACK); 258 } 259 260 /* Perform a dummy read to initiate the receive operation. */ 261 io_read8((vaddr_t)®s->ibdr); 262 263 for (n = 0; n < operation->length_in_bytes; n++) { 264 res = i2c_transfer_complete(regs, I2C_BUS_NO_TEST_RX_ACK); 265 if (res) 266 return res; 267 if (n == (operation->length_in_bytes - 2)) { 268 /* Set No ACK = 1 */ 269 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_NOACK); 270 } else if (n == (operation->length_in_bytes - 1)) { 271 if (!is_last_operation) { 272 /* select Transmit mode (for repeat start) */ 273 io_setbits8((vaddr_t)®s->ibcr, 274 I2C_IBCR_TXRX); 275 } else { 276 /* Generate Stop Signal */ 277 io_clrbits8((vaddr_t)®s->ibcr, 278 (I2C_IBCR_MSSL | I2C_IBCR_TXRX)); 279 res = i2c_bus_test_bus_busy(regs, 280 I2C_BUS_TEST_IDLE); 281 if (res) 282 return res; 283 } 284 } 285 operation->buffer[n] = io_read8((vaddr_t)®s->ibdr); 286 } 287 288 return TEE_SUCCESS; 289 } 290 291 /* 292 * Write data to I2c controller 293 * regs pointer to I2c controller registers 294 * slave_address slave address from which to read 295 * operation pointer to i2c_operation struct 296 */ 297 static TEE_Result i2c_write(struct i2c_regs *regs, unsigned int slave_address, 298 struct i2c_operation *operation) 299 { 300 TEE_Result res = TEE_ERROR_GENERIC; 301 unsigned int n = 0; 302 303 /* Write Slave Address */ 304 io_write8((vaddr_t)®s->ibdr, 305 (slave_address << 0x1) & ~(BIT(0))); 306 res = i2c_transfer_complete(regs, I2C_BUS_TEST_RX_ACK); 307 if (res) 308 return res; 309 310 /* Write Data */ 311 for (n = 0; n < operation->length_in_bytes; n++) { 312 io_write8((vaddr_t)®s->ibdr, operation->buffer[n]); 313 res = i2c_transfer_complete(regs, I2C_BUS_TEST_RX_ACK); 314 if (res) 315 return res; 316 } 317 318 return TEE_SUCCESS; 319 } 320 321 /* 322 * Generate Stop Signal and disable I2C controller. 323 * regs pointer to I2c controller registers 324 */ 325 static TEE_Result i2c_stop(struct i2c_regs *regs) 326 { 327 TEE_Result res = TEE_SUCCESS; 328 uint8_t reg = 0; 329 330 reg = io_read8((vaddr_t)®s->ibsr); 331 if (reg & I2C_IBSR_IBB) { 332 /* Generate Stop Signal */ 333 io_clrbits8((vaddr_t)®s->ibcr, 334 I2C_IBCR_MSSL | I2C_IBCR_TXRX); 335 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_IDLE); 336 if (res) 337 return res; 338 } 339 340 /* Disable I2c Controller */ 341 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_MDIS); 342 343 return TEE_SUCCESS; 344 } 345 346 /* 347 * Generate Start Signal and set I2C controller in transmit mode. 348 * regs pointer to I2c controller registers 349 */ 350 static TEE_Result i2c_start(struct i2c_regs *regs) 351 { 352 TEE_Result res = TEE_ERROR_GENERIC; 353 354 io_setbits8((vaddr_t)®s->ibsr, I2C_IBSR_IBAL | I2C_IBSR_IBIF); 355 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_MDIS); 356 357 /* Wait controller to be stable */ 358 mdelay(1); 359 360 /* Generate Start Signal */ 361 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_MSSL); 362 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_BUSY); 363 if (res) 364 return res; 365 366 /* Select Transmit Mode. set No ACK = 1 */ 367 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_TXRX | I2C_IBCR_NOACK); 368 369 return TEE_SUCCESS; 370 } 371 372 TEE_Result i2c_bus_xfer(vaddr_t base, unsigned int slave_address, 373 struct i2c_operation *i2c_operation, 374 unsigned int operation_count) 375 { 376 unsigned int n = 0; 377 struct i2c_regs *regs = (struct i2c_regs *)base; 378 struct i2c_operation *operation = NULL; 379 TEE_Result res = TEE_ERROR_GENERIC; 380 bool is_last_operation = false; 381 382 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_IDLE); 383 if (res) 384 goto out; 385 386 res = i2c_start(regs); 387 if (res) 388 goto out; 389 390 for (n = 0, operation = i2c_operation; 391 n < operation_count; n++, operation++) { 392 if (n == (operation_count - 1)) 393 is_last_operation = true; 394 395 /* Send repeat start after first transmit/receive */ 396 if (n) { 397 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_RSTA); 398 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_BUSY); 399 if (res) 400 goto out; 401 } 402 403 /* Read/write data */ 404 if (operation->flags & I2C_FLAG_READ) 405 res = i2c_read(regs, slave_address, operation, 406 is_last_operation); 407 else 408 res = i2c_write(regs, slave_address, operation); 409 if (res) 410 goto out; 411 } 412 413 out: 414 i2c_stop(regs); 415 416 return res; 417 } 418