1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2021 NXP 4 * 5 * I2C driver for I2C Controller 6 * 7 */ 8 #include <assert.h> 9 #include <drivers/ls_i2c.h> 10 #include <io.h> 11 #include <kernel/boot.h> 12 #include <kernel/dt.h> 13 #include <kernel/delay.h> 14 #include <libfdt.h> 15 #include <mm/core_memprot.h> 16 #include <string.h> 17 18 static const char * const i2c_controller_map[] = { 19 "/soc/i2c@2000000", "/soc/i2c@2010000", "/soc/i2c@2020000", 20 "/soc/i2c@2030000", "/soc/i2c@2040000", "/soc/i2c@2050000", 21 "/soc/i2c@2060000", "/soc/i2c@2070000" 22 }; 23 24 /* 25 * I2C divisor and ibfd register values when glitch filter is enabled 26 * In case of duplicate SCL divisor value, the ibfd value with high MUL value 27 * has been selected. A higher MUL value results in a lower sampling rate of 28 * the I2C signals. This gives the I2C module greater immunity against glitches 29 * in the I2C signals. 30 */ 31 static const struct i2c_clock_divisor_pair clk_div_glitch_enabled[] = { 32 { 34, 0x0 }, { 36, 0x1 }, { 38, 0x2 }, { 40, 0x3 }, 33 { 42, 0x4 }, { 44, 0x8 }, { 48, 0x9 }, { 52, 0xA }, 34 { 54, 0x7 }, { 56, 0xB }, { 60, 0xC }, { 64, 0x10 }, 35 { 68, 0x40 }, { 72, 0x41 }, { 76, 0x42 }, { 80, 0x43 }, 36 { 84, 0x44 }, { 88, 0x48 }, { 96, 0x49 }, { 104, 0x4A }, 37 { 108, 0x47 }, { 112, 0x4B }, { 120, 0x4C }, { 128, 0x50 }, 38 { 136, 0x80 }, { 144, 0x81 }, { 152, 0x82 }, { 160, 0x83 }, 39 { 168, 0x84 }, { 176, 0x88 }, { 192, 0x89 }, { 208, 0x8A }, 40 { 216, 0x87 }, { 224, 0x8B }, { 240, 0x8C }, { 256, 0x90 }, 41 { 288, 0x91 }, { 320, 0x92 }, { 336, 0x8F }, { 352, 0x93 }, 42 { 384, 0x98 }, { 416, 0x95 }, { 448, 0x99 }, { 480, 0x96 }, 43 { 512, 0x9A }, { 576, 0x9B }, { 640, 0xA0 }, { 704, 0x9D }, 44 { 768, 0xA1 }, { 832, 0x9E }, { 896, 0xA2 }, { 960, 0x67 }, 45 { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 }, 46 { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC }, 47 { 2560, 0xB0 }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF }, 48 { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 }, 49 { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC }, 50 { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF } 51 }; 52 53 /* 54 * I2C divisor and ibfd register values when glitch filter is disabled. 55 * In case of duplicate SCL divisor value, the ibfd value with high MUL value 56 * has been selected. A higher MUL value results in a lower sampling rate of 57 * the I2C signals. This gives the I2C module greater immunity against glitches 58 * in the I2C signals. 59 */ 60 static const struct i2c_clock_divisor_pair clk_div_glitch_disabled[] = { 61 { 20, 0x0 }, { 22, 0x1 }, { 24, 0x2 }, { 26, 0x3 }, 62 { 28, 0x8 }, { 30, 0x5 }, { 32, 0x9 }, { 34, 0x6 }, 63 { 36, 0x0A }, { 40, 0x40 }, { 44, 0x41 }, { 48, 0x42 }, 64 { 52, 0x43 }, { 56, 0x48 }, { 60, 0x45 }, { 64, 0x49 }, 65 { 68, 0x46 }, { 72, 0x4A }, { 80, 0x80 }, { 88, 0x81 }, 66 { 96, 0x82 }, { 104, 0x83 }, { 112, 0x88 }, { 120, 0x85 }, 67 { 128, 0x89 }, { 136, 0x86 }, { 144, 0x8A }, { 160, 0x8B }, 68 { 176, 0x8C }, { 192, 0x90 }, { 208, 0x56 }, { 224, 0x91 }, 69 { 240, 0x1F }, { 256, 0x92 }, { 272, 0x8F }, { 288, 0x93 }, 70 { 320, 0x98 }, { 352, 0x95 }, { 384, 0x99 }, { 416, 0x96 }, 71 { 448, 0x9A }, { 480, 0x5F }, { 512, 0x9B }, { 576, 0x9C }, 72 { 640, 0xA0 }, { 768, 0xA1 }, { 896, 0xA2 }, { 960, 0x9F }, 73 { 1024, 0xA3 }, { 1152, 0xA4 }, { 1280, 0xA8 }, { 1536, 0xA9 }, 74 { 1792, 0xAA }, { 1920, 0xA7 }, { 2048, 0xAB }, { 2304, 0xAC }, 75 { 2560, 0xAD }, { 3072, 0xB1 }, { 3584, 0xB2 }, { 3840, 0xAF }, 76 { 4096, 0xB3 }, { 4608, 0xB4 }, { 5120, 0xB8 }, { 6144, 0xB9 }, 77 { 7168, 0xBA }, { 7680, 0xB7 }, { 8192, 0xBB }, { 9216, 0xBC }, 78 { 10240, 0xBD }, { 12288, 0xBE }, { 15360, 0xBF } 79 }; 80 81 void i2c_reset(vaddr_t base) 82 { 83 struct i2c_regs *regs = (struct i2c_regs *)base; 84 85 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_MDIS); 86 io_setbits8((vaddr_t)®s->ibsr, I2C_IBSR_IBAL | I2C_IBSR_IBIF); 87 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_IBIE | I2C_IBCR_DMAEN); 88 io_clrbits8((vaddr_t)®s->ibic, I2C_IBIC_BIIE); 89 } 90 91 /* 92 * Get I2c Bus Frequency Divider Register value based on clock_divisor 93 * and if the glitch is enabled or not in I2c controller. 94 * base Base address of I2C controller 95 * clock_divisor Clock Divisor 96 */ 97 static uint8_t i2c_get_ibfd(vaddr_t base, uint16_t clock_divisor) 98 { 99 struct i2c_regs *regs = (struct i2c_regs *)base; 100 const struct i2c_clock_divisor_pair *dpair = NULL; 101 size_t dpair_sz = 0; 102 unsigned int n = 0; 103 104 if (io_read8((vaddr_t)®s->ibdbg) & I2C_IBDBG_GLFLT_EN) { 105 dpair = clk_div_glitch_enabled; 106 dpair_sz = ARRAY_SIZE(clk_div_glitch_enabled); 107 } else { 108 dpair = clk_div_glitch_disabled; 109 dpair_sz = ARRAY_SIZE(clk_div_glitch_disabled); 110 } 111 112 for (n = 0; n < dpair_sz - 1; n++) 113 if (clock_divisor < dpair[n].divisor) 114 break; 115 116 return dpair[n].ibfd; 117 } 118 119 TEE_Result i2c_init(struct ls_i2c_data *i2c_data) 120 { 121 struct i2c_regs *regs = NULL; 122 uint16_t clock_divisor = 0; 123 uint8_t ibfd = 0; /* I2c Bus Frequency Divider Register */ 124 size_t size = 0; 125 int node = 0; 126 vaddr_t ctrl_base = 0; 127 void *fdt = NULL; 128 129 /* 130 * First get the I2C Controller base address from the DTB 131 * if DTB present and if the I2C Controller defined in it. 132 */ 133 fdt = get_embedded_dt(); 134 if (!fdt) { 135 EMSG("Unable to get the Embedded DTB, I2C init failed\n"); 136 return TEE_ERROR_GENERIC; 137 } 138 139 node = fdt_path_offset(fdt, 140 i2c_controller_map[i2c_data->i2c_controller]); 141 if (node > 0) { 142 if (dt_map_dev(fdt, node, &ctrl_base, &size) < 0) { 143 EMSG("Unable to get virtual address"); 144 return TEE_ERROR_GENERIC; 145 } 146 } else { 147 EMSG("Unable to get I2C offset node"); 148 return TEE_ERROR_ITEM_NOT_FOUND; 149 } 150 151 i2c_data->base = ctrl_base; 152 153 regs = (struct i2c_regs *)ctrl_base; 154 155 clock_divisor = (i2c_data->i2c_bus_clock + i2c_data->speed - 1) / 156 i2c_data->speed; 157 ibfd = i2c_get_ibfd(ctrl_base, clock_divisor); 158 159 io_write8((vaddr_t)®s->ibfd, ibfd); 160 161 i2c_reset(ctrl_base); 162 163 return TEE_SUCCESS; 164 } 165 166 /* 167 * Check if I2C bus is busy with previous transaction or not. 168 * regs pointer to I2c controller registers 169 * test_busy this flag tells if we need to check the busy bit in IBSR reg 170 */ 171 static TEE_Result i2c_bus_test_bus_busy(struct i2c_regs *regs, bool test_busy) 172 { 173 unsigned int n = 0; 174 uint8_t reg = 0; 175 176 for (n = 0; n < I2C_NUM_RETRIES; n++) { 177 reg = io_read8((vaddr_t)®s->ibsr); 178 179 if (reg & I2C_IBSR_IBAL) { 180 io_write8((vaddr_t)®s->ibsr, reg); 181 return TEE_ERROR_BUSY; 182 } 183 184 if (test_busy && (reg & I2C_IBSR_IBB)) 185 break; 186 187 if (!test_busy && !(reg & I2C_IBSR_IBB)) 188 break; 189 190 mdelay(1); 191 } 192 193 if (n == I2C_NUM_RETRIES) 194 return TEE_ERROR_BUSY; 195 196 return TEE_SUCCESS; 197 } 198 199 /* 200 * Check if data transfer to/from i2c controller is complete. 201 * regs pointer to I2c controller registers 202 * test_rx_ack this flag tells if we need to check RXAK bit in IBSR reg 203 */ 204 static TEE_Result i2c_transfer_complete(struct i2c_regs *regs, bool test_rx_ack) 205 { 206 unsigned int n = 0; 207 uint8_t reg = 0; 208 209 for (n = 0; n < I2C_NUM_RETRIES; n++) { 210 reg = io_read8((vaddr_t)®s->ibsr); 211 212 if (reg & I2C_IBSR_IBIF) { 213 /* Write 1 to clear the IBIF field */ 214 io_write8((vaddr_t)®s->ibsr, reg); 215 break; 216 } 217 mdelay(1); 218 } 219 220 if (n == I2C_NUM_RETRIES) 221 return TEE_ERROR_BUSY; 222 223 if (test_rx_ack && (reg & I2C_IBSR_RXAK)) 224 return TEE_ERROR_NO_DATA; 225 226 if (reg & I2C_IBSR_TCF) 227 return TEE_SUCCESS; 228 229 return TEE_ERROR_GENERIC; 230 } 231 232 /* 233 * Read data from I2c controller. 234 * regs pointer to I2c controller registers 235 * slave_address slave address from which to read 236 * operation pointer to i2c_operation struct 237 * is_last_operation if current operation is last operation 238 */ 239 static TEE_Result i2c_read(struct i2c_regs *regs, unsigned int slave_address, 240 struct i2c_operation *operation, 241 bool is_last_operation) 242 { 243 TEE_Result res = TEE_ERROR_GENERIC; 244 unsigned int n = 0; 245 246 /* Write Slave Address */ 247 io_write8((vaddr_t)®s->ibdr, (slave_address << 0x1) | BIT(0)); 248 res = i2c_transfer_complete(regs, I2C_BUS_TEST_RX_ACK); 249 if (res) 250 return res; 251 252 /* select Receive mode. */ 253 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_TXRX); 254 if (operation->length_in_bytes > 1) { 255 /* Set No ACK = 0 */ 256 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_NOACK); 257 } 258 259 /* Perform a dummy read to initiate the receive operation. */ 260 io_read8((vaddr_t)®s->ibdr); 261 262 for (n = 0; n < operation->length_in_bytes; n++) { 263 res = i2c_transfer_complete(regs, I2C_BUS_NO_TEST_RX_ACK); 264 if (res) 265 return res; 266 if (n == (operation->length_in_bytes - 2)) { 267 /* Set No ACK = 1 */ 268 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_NOACK); 269 } else if (n == (operation->length_in_bytes - 1)) { 270 if (!is_last_operation) { 271 /* select Transmit mode (for repeat start) */ 272 io_setbits8((vaddr_t)®s->ibcr, 273 I2C_IBCR_TXRX); 274 } else { 275 /* Generate Stop Signal */ 276 io_clrbits8((vaddr_t)®s->ibcr, 277 (I2C_IBCR_MSSL | I2C_IBCR_TXRX)); 278 res = i2c_bus_test_bus_busy(regs, 279 I2C_BUS_TEST_IDLE); 280 if (res) 281 return res; 282 } 283 } 284 operation->buffer[n] = io_read8((vaddr_t)®s->ibdr); 285 } 286 287 return TEE_SUCCESS; 288 } 289 290 /* 291 * Write data to I2c controller 292 * regs pointer to I2c controller registers 293 * slave_address slave address from which to read 294 * operation pointer to i2c_operation struct 295 */ 296 static TEE_Result i2c_write(struct i2c_regs *regs, unsigned int slave_address, 297 struct i2c_operation *operation) 298 { 299 TEE_Result res = TEE_ERROR_GENERIC; 300 unsigned int n = 0; 301 302 /* Write Slave Address */ 303 io_write8((vaddr_t)®s->ibdr, 304 (slave_address << 0x1) & ~(BIT(0))); 305 res = i2c_transfer_complete(regs, I2C_BUS_TEST_RX_ACK); 306 if (res) 307 return res; 308 309 /* Write Data */ 310 for (n = 0; n < operation->length_in_bytes; n++) { 311 io_write8((vaddr_t)®s->ibdr, operation->buffer[n]); 312 res = i2c_transfer_complete(regs, I2C_BUS_TEST_RX_ACK); 313 if (res) 314 return res; 315 } 316 317 return TEE_SUCCESS; 318 } 319 320 /* 321 * Generate Stop Signal and disable I2C controller. 322 * regs pointer to I2c controller registers 323 */ 324 static TEE_Result i2c_stop(struct i2c_regs *regs) 325 { 326 TEE_Result res = TEE_SUCCESS; 327 uint8_t reg = 0; 328 329 reg = io_read8((vaddr_t)®s->ibsr); 330 if (reg & I2C_IBSR_IBB) { 331 /* Generate Stop Signal */ 332 io_clrbits8((vaddr_t)®s->ibcr, 333 I2C_IBCR_MSSL | I2C_IBCR_TXRX); 334 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_IDLE); 335 if (res) 336 return res; 337 } 338 339 /* Disable I2c Controller */ 340 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_MDIS); 341 342 return TEE_SUCCESS; 343 } 344 345 /* 346 * Generate Start Signal and set I2C controller in transmit mode. 347 * regs pointer to I2c controller registers 348 */ 349 static TEE_Result i2c_start(struct i2c_regs *regs) 350 { 351 TEE_Result res = TEE_ERROR_GENERIC; 352 353 io_setbits8((vaddr_t)®s->ibsr, I2C_IBSR_IBAL | I2C_IBSR_IBIF); 354 io_clrbits8((vaddr_t)®s->ibcr, I2C_IBCR_MDIS); 355 356 /* Wait controller to be stable */ 357 mdelay(1); 358 359 /* Generate Start Signal */ 360 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_MSSL); 361 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_BUSY); 362 if (res) 363 return res; 364 365 /* Select Transmit Mode. set No ACK = 1 */ 366 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_TXRX | I2C_IBCR_NOACK); 367 368 return TEE_SUCCESS; 369 } 370 371 TEE_Result i2c_bus_xfer(vaddr_t base, unsigned int slave_address, 372 struct i2c_operation *i2c_operation, 373 unsigned int operation_count) 374 { 375 unsigned int n = 0; 376 struct i2c_regs *regs = (struct i2c_regs *)base; 377 struct i2c_operation *operation = NULL; 378 TEE_Result res = TEE_ERROR_GENERIC; 379 bool is_last_operation = false; 380 381 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_IDLE); 382 if (res) 383 goto out; 384 385 res = i2c_start(regs); 386 if (res) 387 goto out; 388 389 for (n = 0, operation = i2c_operation; 390 n < operation_count; n++, operation++) { 391 if (n == (operation_count - 1)) 392 is_last_operation = true; 393 394 /* Send repeat start after first transmit/receive */ 395 if (n) { 396 io_setbits8((vaddr_t)®s->ibcr, I2C_IBCR_RSTA); 397 res = i2c_bus_test_bus_busy(regs, I2C_BUS_TEST_BUSY); 398 if (res) 399 goto out; 400 } 401 402 /* Read/write data */ 403 if (operation->flags & I2C_FLAG_READ) 404 res = i2c_read(regs, slave_address, operation, 405 is_last_operation); 406 else 407 res = i2c_write(regs, slave_address, operation); 408 if (res) 409 goto out; 410 } 411 412 out: 413 i2c_stop(regs); 414 415 return res; 416 } 417