1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <assert.h> 30 #include <drivers/imx_uart.h> 31 #include <io.h> 32 #include <keep.h> 33 #include <util.h> 34 35 /* Register definitions */ 36 #define URXD 0x0 /* Receiver Register */ 37 #define UTXD 0x40 /* Transmitter Register */ 38 #define UCR1 0x80 /* Control Register 1 */ 39 #define UCR2 0x84 /* Control Register 2 */ 40 #define UCR3 0x88 /* Control Register 3 */ 41 #define UCR4 0x8c /* Control Register 4 */ 42 #define UFCR 0x90 /* FIFO Control Register */ 43 #define USR1 0x94 /* Status Register 1 */ 44 #define USR2 0x98 /* Status Register 2 */ 45 #define UESC 0x9c /* Escape Character Register */ 46 #define UTIM 0xa0 /* Escape Timer Register */ 47 #define UBIR 0xa4 /* BRM Incremental Register */ 48 #define UBMR 0xa8 /* BRM Modulator Register */ 49 #define UBRC 0xac /* Baud Rate Count Register */ 50 #define UTS 0xb4 /* UART Test Register (mx31) */ 51 52 /* UART Control Register Bit Fields.*/ 53 #define URXD_CHARRDY (1<<15) 54 #define URXD_ERR (1<<14) 55 #define URXD_OVRRUN (1<<13) 56 #define URXD_FRMERR (1<<12) 57 #define URXD_BRK (1<<11) 58 #define URXD_PRERR (1<<10) 59 #define URXD_RX_DATA (0xFF) 60 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 61 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 62 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 63 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 64 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 65 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 66 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 67 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 68 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 69 #define UCR1_SNDBRK (1<<4) /* Send break */ 70 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 71 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 72 #define UCR1_DOZE (1<<1) /* Doze */ 73 #define UCR1_UARTEN (1<<0) /* UART enabled */ 74 75 #define UTS_FRCPERR (1<<13) /* Force parity error */ 76 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 77 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 78 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 79 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 80 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 81 #define UTS_SOFTRST (1<<0) /* Software reset */ 82 83 static vaddr_t chip_to_base(struct serial_chip *chip) 84 { 85 struct imx_uart_data *pd = 86 container_of(chip, struct imx_uart_data, chip); 87 88 return io_pa_or_va(&pd->base); 89 } 90 91 static void imx_uart_flush(struct serial_chip *chip) 92 { 93 vaddr_t base = chip_to_base(chip); 94 95 while (!(read32(base + UTS) & UTS_TXEMPTY)) 96 ; 97 } 98 99 static int imx_uart_getchar(struct serial_chip *chip) 100 { 101 vaddr_t base = chip_to_base(chip); 102 103 while (read32(base + UTS) & UTS_RXEMPTY) 104 ; 105 106 return (read32(base + URXD) & URXD_RX_DATA); 107 } 108 109 static void imx_uart_putc(struct serial_chip *chip, int ch) 110 { 111 vaddr_t base = chip_to_base(chip); 112 113 write32(ch, base + UTXD); 114 115 /* Wait until sent */ 116 while (!(read32(base + UTS) & UTS_TXEMPTY)) 117 ; 118 } 119 120 static const struct serial_ops imx_uart_ops = { 121 .flush = imx_uart_flush, 122 .getchar = imx_uart_getchar, 123 .putc = imx_uart_putc, 124 }; 125 KEEP_PAGER(imx_uart_ops); 126 127 void imx_uart_init(struct imx_uart_data *pd, paddr_t base) 128 { 129 pd->base.pa = base; 130 pd->chip.ops = &imx_uart_ops; 131 132 /* 133 * Do nothing, debug uart(uart0) share with normal world, 134 * everything for uart0 initialization is done in bootloader. 135 */ 136 } 137