1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * All rights reserved. 5 * Copyright 2018-2019 NXP. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <assert.h> 31 #include <drivers/imx_uart.h> 32 #include <io.h> 33 #include <keep.h> 34 #include <kernel/dt.h> 35 #include <util.h> 36 37 /* Register definitions */ 38 #define URXD 0x0 /* Receiver Register */ 39 #define UTXD 0x40 /* Transmitter Register */ 40 #define UCR1 0x80 /* Control Register 1 */ 41 #define UCR2 0x84 /* Control Register 2 */ 42 #define UCR3 0x88 /* Control Register 3 */ 43 #define UCR4 0x8c /* Control Register 4 */ 44 #define UFCR 0x90 /* FIFO Control Register */ 45 #define USR1 0x94 /* Status Register 1 */ 46 #define USR2 0x98 /* Status Register 2 */ 47 #define UESC 0x9c /* Escape Character Register */ 48 #define UTIM 0xa0 /* Escape Timer Register */ 49 #define UBIR 0xa4 /* BRM Incremental Register */ 50 #define UBMR 0xa8 /* BRM Modulator Register */ 51 #define UBRC 0xac /* Baud Rate Count Register */ 52 #define UTS 0xb4 /* UART Test Register (mx31) */ 53 54 /* UART Control Register Bit Fields.*/ 55 #define URXD_CHARRDY (1<<15) 56 #define URXD_ERR (1<<14) 57 #define URXD_OVRRUN (1<<13) 58 #define URXD_FRMERR (1<<12) 59 #define URXD_BRK (1<<11) 60 #define URXD_PRERR (1<<10) 61 #define URXD_RX_DATA (0xFF) 62 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ 63 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ 64 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ 65 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ 66 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ 67 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ 68 #define UCR1_IREN (1<<7) /* Infrared interface enable */ 69 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ 70 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ 71 #define UCR1_SNDBRK (1<<4) /* Send break */ 72 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ 73 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ 74 #define UCR1_DOZE (1<<1) /* Doze */ 75 #define UCR1_UARTEN (1<<0) /* UART enabled */ 76 77 #define UTS_FRCPERR (1<<13) /* Force parity error */ 78 #define UTS_LOOP (1<<12) /* Loop tx and rx */ 79 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ 80 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ 81 #define UTS_TXFULL (1<<4) /* TxFIFO full */ 82 #define UTS_RXFULL (1<<3) /* RxFIFO full */ 83 #define UTS_SOFTRST (1<<0) /* Software reset */ 84 85 static vaddr_t chip_to_base(struct serial_chip *chip) 86 { 87 struct imx_uart_data *pd = 88 container_of(chip, struct imx_uart_data, chip); 89 90 return io_pa_or_va(&pd->base); 91 } 92 93 static void imx_uart_flush(struct serial_chip *chip) 94 { 95 vaddr_t base = chip_to_base(chip); 96 97 98 while (!(io_read32(base + UTS) & UTS_TXEMPTY)) 99 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) 100 return; 101 } 102 103 static int imx_uart_getchar(struct serial_chip *chip) 104 { 105 vaddr_t base = chip_to_base(chip); 106 107 while (io_read32(base + UTS) & UTS_RXEMPTY) 108 ; 109 110 return (io_read32(base + URXD) & URXD_RX_DATA); 111 } 112 113 static void imx_uart_putc(struct serial_chip *chip, int ch) 114 { 115 vaddr_t base = chip_to_base(chip); 116 117 /* Wait until there's space in the TX FIFO */ 118 while (io_read32(base + UTS) & UTS_TXFULL) 119 if (!(io_read32(base + UCR1) & UCR1_UARTEN)) 120 return; 121 122 io_write32(base + UTXD, ch); 123 } 124 125 static const struct serial_ops imx_uart_ops = { 126 .flush = imx_uart_flush, 127 .getchar = imx_uart_getchar, 128 .putc = imx_uart_putc, 129 }; 130 KEEP_PAGER(imx_uart_ops); 131 132 void imx_uart_init(struct imx_uart_data *pd, paddr_t base) 133 { 134 pd->base.pa = base; 135 pd->chip.ops = &imx_uart_ops; 136 137 /* 138 * Do nothing, debug uart(uart0) share with normal world, 139 * everything for uart0 initialization is done in bootloader. 140 */ 141 } 142 143 #ifdef CFG_DT 144 static struct serial_chip *imx_uart_dev_alloc(void) 145 { 146 struct imx_uart_data *pd = calloc(1, sizeof(*pd)); 147 148 if (!pd) 149 return NULL; 150 151 return &pd->chip; 152 } 153 154 static int imx_uart_dev_init(struct serial_chip *chip, const void *fdt, 155 int offs, const char *parms) 156 { 157 struct imx_uart_data *pd = 158 container_of(chip, struct imx_uart_data, chip); 159 vaddr_t vbase = 0; 160 paddr_t pbase = 0; 161 size_t size = 0; 162 163 if (parms && parms[0]) 164 IMSG("imx_uart: device parameters ignored (%s)", parms); 165 166 if (dt_map_dev(fdt, offs, &vbase, &size) < 0) 167 return -1; 168 169 pbase = virt_to_phys((void *)vbase); 170 imx_uart_init(pd, pbase); 171 172 return 0; 173 } 174 175 static void imx_uart_dev_free(struct serial_chip *chip) 176 { 177 struct imx_uart_data *pd = 178 container_of(chip, struct imx_uart_data, chip); 179 180 free(pd); 181 } 182 183 static const struct serial_driver imx_uart_driver = { 184 .dev_alloc = imx_uart_dev_alloc, 185 .dev_init = imx_uart_dev_init, 186 .dev_free = imx_uart_dev_free, 187 }; 188 189 static const struct dt_device_match imx_match_table[] = { 190 { .compatible = "fsl,imx6q-uart" }, 191 { 0 } 192 }; 193 194 const struct dt_driver imx_dt_driver __dt_driver = { 195 .name = "imx_uart", 196 .match_table = imx_match_table, 197 .driver = &imx_uart_driver, 198 }; 199 200 #endif /* CFG_DT */ 201