1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * (c) 2020 Jorge Ramirez <jorge@foundries.io>, Foundries Ltd. 4 */ 5 #include <arm.h> 6 #include <drivers/imx_i2c.h> 7 #include <initcall.h> 8 #include <io.h> 9 #include <kernel/boot.h> 10 #include <kernel/delay.h> 11 #include <kernel/dt.h> 12 #include <libfdt.h> 13 #include <mm/core_memprot.h> 14 #include <mm/core_mmu.h> 15 #include <platform_config.h> 16 #include <stdlib.h> 17 #include <trace.h> 18 #include <util.h> 19 20 #define I2C_CLK_RATE 24000000 /* Bits per second */ 21 22 #define USE_I2C_STATIC_ADDRESS \ 23 (!defined(CFG_DT) || defined(CFG_EXTERNAL_DTB_OVERLAY)) 24 25 /* Utility macros (__x identifies the bus [1 .. 3]) */ 26 #define I2C_CFG_SCL(__x) (IOMUXC_I2C1_SCL_CFG_OFF + ((__x) - 1) * 0x8) 27 #define I2C_CFG_SDA(__x) (IOMUXC_I2C1_SDA_CFG_OFF + ((__x) - 1) * 0x8) 28 #define I2C_MUX_SCL(__x) (IOMUXC_I2C1_SCL_MUX_OFF + ((__x) - 1) * 0x8) 29 #define I2C_MUX_SDA(__x) (IOMUXC_I2C1_SDA_MUX_OFF + ((__x) - 1) * 0x8) 30 #if defined(CFG_MX8MM) 31 /* IOMUX */ 32 #define I2C_INP_SCL(__x) 0 /* Not implemented */ 33 #define I2C_INP_SDA(__x) 0 /* Not implemented */ 34 #define I2C_INP_VAL(__x) 0 /* Not implemented */ 35 #define I2C_MUX_VAL(__x) 0x010 36 #define I2C_CFG_VAL(__x) 0x1c3 37 /* Clock */ 38 #define I2C_CLK_CGRBM(__x) 0 /* Not implemented */ 39 #define I2C_CLK_CGR(__x) CCM_CCRG_I2C##__x 40 #elif defined(CFG_MX6ULL) 41 /* IOMUX */ 42 #define I2C_INP_SCL(__x) (IOMUXC_I2C1_SCL_INP_OFF + ((__x) - 1) * 0x8) 43 #define I2C_INP_SDA(__x) (IOMUXC_I2C1_SDA_INP_OFF + ((__x) - 1) * 0x8) 44 #define I2C_INP_VAL(__x) (((__x) == 1) ? 0x1 : 0x2) 45 #define I2C_MUX_VAL(__x) 0x012 46 #define I2C_CFG_VAL(__x) 0x1b8b0 47 /* Clock */ 48 #define I2C_CLK_CGRBM(__x) BM_CCM_CCGR2_I2C##__x##_SERIAL 49 #define I2C_CLK_CGR(__x) CCM_CCGR2 50 #else 51 #error IMX_I2C driver not supported on this platform 52 #endif 53 54 static struct io_pa_va i2c_bus[3] = { 55 #if USE_I2C_STATIC_ADDRESS 56 #if defined(I2C1_BASE) 57 [0] = { .pa = I2C1_BASE, }, 58 #endif 59 #if defined(I2C2_BASE) 60 [1] = { .pa = I2C2_BASE, }, 61 #endif 62 #if defined(I2C3_BASE) 63 [2] = { .pa = I2C3_BASE, }, 64 #endif 65 #endif 66 }; 67 68 static struct imx_i2c_clk { 69 struct io_pa_va base; 70 uint32_t i2c[ARRAY_SIZE(i2c_bus)]; 71 uint32_t cgrbm[ARRAY_SIZE(i2c_bus)]; 72 } i2c_clk = { 73 .base.pa = CCM_BASE, 74 .i2c = { I2C_CLK_CGR(1), I2C_CLK_CGR(2), I2C_CLK_CGR(3), }, 75 .cgrbm = { I2C_CLK_CGRBM(1), I2C_CLK_CGRBM(2), I2C_CLK_CGRBM(3), }, 76 }; 77 78 static struct imx_i2c_mux { 79 struct io_pa_va base; 80 struct imx_i2c_mux_regs { 81 uint32_t scl_mux; 82 uint32_t scl_cfg; 83 uint32_t scl_inp; 84 uint32_t sda_mux; 85 uint32_t sda_cfg; 86 uint32_t sda_inp; 87 } i2c[ARRAY_SIZE(i2c_bus)]; 88 } i2c_mux = { 89 .base.pa = IOMUXC_BASE, 90 .i2c = {{ .scl_mux = I2C_MUX_SCL(1), .scl_cfg = I2C_CFG_SCL(1), 91 .scl_inp = I2C_INP_SCL(1), .sda_mux = I2C_MUX_SDA(1), 92 .sda_cfg = I2C_CFG_SDA(1), .sda_inp = I2C_INP_SDA(1), }, 93 { .scl_mux = I2C_MUX_SCL(2), .scl_cfg = I2C_CFG_SCL(2), 94 .scl_inp = I2C_INP_SCL(2), .sda_mux = I2C_MUX_SDA(2), 95 .sda_cfg = I2C_CFG_SDA(2), .sda_inp = I2C_INP_SDA(2), }, 96 { .scl_mux = I2C_MUX_SCL(3), .scl_cfg = I2C_CFG_SCL(3), 97 .scl_inp = I2C_INP_SCL(3), .sda_mux = I2C_MUX_SDA(3), 98 .sda_cfg = I2C_CFG_SDA(3), .sda_inp = I2C_INP_SDA(3), },}, 99 }; 100 101 #define I2DR 0x10 102 #define I2SR 0x0C 103 #define I2CR 0x08 104 #define IFDR 0x04 105 106 #define I2CR_IEN BIT(7) 107 #define I2CR_IIEN BIT(6) 108 #define I2CR_MSTA BIT(5) 109 #define I2CR_MTX BIT(4) 110 #define I2CR_TX_NO_AK BIT(3) 111 #define I2CR_RSTA BIT(2) 112 113 #define I2SR_ICF BIT(7) 114 #define I2SR_IBB BIT(5) 115 #define I2SR_IAL BIT(4) 116 #define I2SR_IIF BIT(1) 117 #define I2SR_RX_NO_AK BIT(0) 118 119 static uint8_t i2c_io_read8(uint8_t bid, uint32_t address) 120 { 121 return io_read8(i2c_bus[bid].va + address); 122 } 123 124 static void i2c_io_write8(uint8_t bid, uint32_t address, uint8_t data) 125 { 126 return io_write8(i2c_bus[bid].va + address, data); 127 } 128 129 static bool bus_is_idle(uint32_t sr) 130 { 131 return (sr & I2SR_IBB) == 0; 132 } 133 134 static bool bus_is_busy(uint32_t sr) 135 { 136 return !bus_is_idle(sr); 137 } 138 139 static bool isr_active(uint32_t sr) 140 { 141 return (sr & I2SR_IIF) == I2SR_IIF; 142 } 143 144 static struct ifdr_pair { 145 uint32_t divider; 146 uint8_t prescaler; 147 } ifdr_table[] = { 148 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 149 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 150 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 151 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 152 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 153 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 154 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 155 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 156 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 157 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 158 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 159 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 160 { 3072, 0x1E }, { 3840, 0x1F } 161 }; 162 163 static void i2c_set_prescaler(uint8_t bid, uint32_t bps) 164 { 165 struct ifdr_pair *p = ifdr_table; 166 struct ifdr_pair *q = p + ARRAY_SIZE(ifdr_table) - 1; 167 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; 168 169 if (div < p->divider) 170 q = p; 171 else if (div > q->divider) 172 p = q; 173 174 while (p != q) { 175 if (div <= p->divider) 176 break; 177 p++; 178 } 179 180 i2c_io_write8(bid, IFDR, p->prescaler); 181 } 182 183 static void i2c_set_bus_speed(uint8_t bid, int bps) 184 { 185 vaddr_t addr = i2c_clk.base.va; 186 uint32_t val = 0; 187 188 #if defined(CFG_MX8MM) 189 addr += CCM_CCGRx_SET(i2c_clk.i2c[bid]); 190 val = CCM_CCGRx_ALWAYS_ON(0); 191 #elif defined(CFG_MX6ULL) 192 addr += i2c_clk.i2c[bid]; 193 val = i2c_clk.cgrbm[bid] | io_read32(addr); 194 #else 195 #error IMX_I2C driver not supported on this platform 196 #endif 197 io_write32(addr, val); 198 i2c_set_prescaler(bid, bps); 199 } 200 201 static TEE_Result i2c_sync_bus(uint8_t bid, bool (*match)(uint32_t), 202 uint32_t *status) 203 { 204 uint64_t tref = timeout_init_us(100000); 205 uint32_t sr = 0; 206 207 while (!timeout_elapsed(tref)) { 208 sr = i2c_io_read8(bid, I2SR); 209 if (sr & I2SR_IAL) { 210 EMSG("bus arbitration lost"); 211 i2c_io_write8(bid, I2SR, sr & ~I2SR_IAL); 212 return TEE_ERROR_COMMUNICATION; 213 } 214 if ((*match)(sr)) { 215 if (status) 216 *status = sr; 217 return TEE_SUCCESS; 218 } 219 } 220 221 return TEE_ERROR_BUSY; 222 } 223 224 static TEE_Result i2c_idle_bus(uint8_t bid) 225 { 226 uint8_t tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MSTA; 227 TEE_Result ret = TEE_SUCCESS; 228 229 i2c_io_write8(bid, I2CR, tmp); 230 ret = i2c_sync_bus(bid, &bus_is_idle, NULL); 231 i2c_io_write8(bid, I2SR, 0); 232 233 return ret; 234 } 235 236 static TEE_Result i2c_write_byte(uint8_t bid, uint8_t byte) 237 { 238 TEE_Result ret = TEE_SUCCESS; 239 uint32_t status = 0; 240 241 i2c_io_write8(bid, I2DR, byte); 242 ret = i2c_sync_bus(bid, &isr_active, &status); 243 i2c_io_write8(bid, I2SR, 0); 244 245 if (!ret && (status & I2SR_RX_NO_AK)) 246 return TEE_ERROR_BAD_STATE; 247 248 return ret; 249 } 250 251 static TEE_Result i2c_read_byte(uint8_t bid, uint8_t *p) 252 { 253 TEE_Result ret = TEE_SUCCESS; 254 255 *p = i2c_io_read8(bid, I2DR); 256 ret = i2c_sync_bus(bid, &isr_active, NULL); 257 i2c_io_write8(bid, I2SR, 0); 258 259 return ret; 260 } 261 262 static TEE_Result i2c_write_data(uint8_t bid, const uint8_t *buf, int len) 263 { 264 TEE_Result ret = TEE_SUCCESS; 265 uint32_t tmp = 0; 266 267 if (!len) 268 return TEE_SUCCESS; 269 270 tmp = i2c_io_read8(bid, I2CR) | I2CR_MTX | I2CR_TX_NO_AK; 271 i2c_io_write8(bid, I2CR, tmp); 272 273 while (len--) { 274 ret = i2c_write_byte(bid, *buf++); 275 if (ret) 276 return ret; 277 } 278 279 return ret; 280 } 281 282 static TEE_Result i2c_read_data(uint8_t bid, uint8_t *buf, int len) 283 { 284 TEE_Result ret = TEE_SUCCESS; 285 uint8_t dummy = 0; 286 uint32_t tmp = 0; 287 288 if (!len) 289 return TEE_SUCCESS; 290 291 tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MTX; 292 tmp = (len == 1) ? tmp | I2CR_TX_NO_AK : tmp & ~I2CR_TX_NO_AK; 293 i2c_io_write8(bid, I2CR, tmp); 294 i2c_io_read8(bid, I2DR); 295 296 ret = i2c_read_byte(bid, &dummy); 297 if (ret) 298 return ret; 299 300 /* 301 * A data transfer ends when the master signals a stop; for a master 302 * receiver to terminate a transfer it must inform the slave transmiter 303 * by not acknowledging the last data byte. This is done by setting the 304 * transmit acknowledge bit before reading the next-to-last byte. 305 */ 306 do { 307 if (len == 2) { 308 tmp = i2c_io_read8(bid, I2CR) | I2CR_TX_NO_AK; 309 i2c_io_write8(bid, I2CR, tmp); 310 } 311 312 ret = i2c_read_byte(bid, buf++); 313 if (ret) 314 return ret; 315 } while (len--); 316 317 return ret; 318 } 319 320 static TEE_Result i2c_init_transfer(uint8_t bid, uint8_t chip) 321 { 322 TEE_Result ret = TEE_SUCCESS; 323 uint32_t tmp = 0; 324 325 ret = i2c_idle_bus(bid); 326 if (ret) 327 return ret; 328 329 /* Enable the interface */ 330 i2c_io_write8(bid, I2CR, I2CR_IEN); 331 332 tmp = i2c_io_read8(bid, I2CR) | I2CR_MSTA; 333 i2c_io_write8(bid, I2CR, tmp); 334 335 /* Wait until the bus is active */ 336 ret = i2c_sync_bus(bid, &bus_is_busy, NULL); 337 if (ret) 338 return ret; 339 340 /* Slave address on the bus */ 341 return i2c_write_data(bid, &chip, 1); 342 } 343 344 TEE_Result imx_i2c_read(uint8_t bid, uint8_t chip, uint8_t *buf, int len) 345 { 346 TEE_Result ret = TEE_SUCCESS; 347 348 if (bid >= ARRAY_SIZE(i2c_bus)) 349 return TEE_ERROR_BAD_PARAMETERS; 350 351 if ((len && !buf) || chip > 0x7F) 352 return TEE_ERROR_BAD_PARAMETERS; 353 354 if (!i2c_bus[bid].va) 355 return TEE_ERROR_BAD_PARAMETERS; 356 357 ret = i2c_init_transfer(bid, chip << 1 | BIT(0)); 358 if (!ret) 359 ret = i2c_read_data(bid, buf, len); 360 361 if (i2c_idle_bus(bid)) 362 IMSG("bus not idle"); 363 364 return ret; 365 } 366 367 TEE_Result imx_i2c_write(uint8_t bid, uint8_t chip, const uint8_t *buf, int len) 368 { 369 TEE_Result ret = TEE_SUCCESS; 370 371 if (bid >= ARRAY_SIZE(i2c_bus)) 372 return TEE_ERROR_BAD_PARAMETERS; 373 374 if ((len && !buf) || chip > 0x7F) 375 return TEE_ERROR_BAD_PARAMETERS; 376 377 if (!i2c_bus[bid].va) 378 return TEE_ERROR_BAD_PARAMETERS; 379 380 ret = i2c_init_transfer(bid, chip << 1); 381 if (!ret) 382 ret = i2c_write_data(bid, buf, len); 383 384 if (i2c_idle_bus(bid)) 385 IMSG("bus not idle"); 386 387 return ret; 388 } 389 390 TEE_Result imx_i2c_probe(uint8_t bid, uint8_t chip) 391 { 392 if (bid >= ARRAY_SIZE(i2c_bus)) 393 return TEE_ERROR_BAD_PARAMETERS; 394 395 if (!i2c_bus[bid].va) 396 return TEE_ERROR_BAD_PARAMETERS; 397 398 if (chip > 0x7F) 399 return TEE_ERROR_BAD_PARAMETERS; 400 401 return imx_i2c_write(bid, chip, NULL, 0); 402 } 403 404 /* 405 * I2C bus initialization: configure the IOMUX and enable the clock. 406 * @bid: Bus ID: (0=I2C1), (1=I2C2), (2=I2C3). 407 * @bps: Bus baud rate, in bits per second. 408 */ 409 TEE_Result imx_i2c_init(uint8_t bid, int bps) 410 { 411 struct imx_i2c_mux *mux = &i2c_mux; 412 413 if (bid >= ARRAY_SIZE(i2c_bus)) 414 return TEE_ERROR_BAD_PARAMETERS; 415 416 if (!bps) 417 return TEE_ERROR_BAD_PARAMETERS; 418 419 if (!i2c_bus[bid].va) 420 return TEE_ERROR_BAD_PARAMETERS; 421 422 io_write32(mux->base.va + mux->i2c[bid].scl_mux, I2C_MUX_VAL(bid)); 423 io_write32(mux->base.va + mux->i2c[bid].scl_cfg, I2C_CFG_VAL(bid)); 424 if (mux->i2c[bid].scl_inp) 425 io_write32(mux->base.va + mux->i2c[bid].scl_inp, 426 I2C_INP_VAL(bid + 1)); 427 428 io_write32(mux->base.va + mux->i2c[bid].sda_mux, I2C_MUX_VAL(bid)); 429 io_write32(mux->base.va + mux->i2c[bid].sda_cfg, I2C_CFG_VAL(bid)); 430 if (mux->i2c[bid].sda_inp) 431 io_write32(mux->base.va + mux->i2c[bid].sda_inp, 432 I2C_INP_VAL(bid + 1)); 433 434 /* Baud rate in bits per second */ 435 i2c_set_bus_speed(bid, bps); 436 437 return TEE_SUCCESS; 438 } 439 440 static TEE_Result get_va(paddr_t pa, vaddr_t *va) 441 { 442 if (!core_mmu_add_mapping(MEM_AREA_IO_SEC, pa, 0x10000)) 443 return TEE_ERROR_GENERIC; 444 445 *va = (vaddr_t)phys_to_virt(pa, MEM_AREA_IO_SEC); 446 if (*va) 447 return TEE_SUCCESS; 448 449 return TEE_ERROR_GENERIC; 450 } 451 452 #if !USE_I2C_STATIC_ADDRESS 453 static const char *const dt_i2c_match_table[] = { 454 "fsl,imx21-i2c", 455 }; 456 457 static TEE_Result i2c_mapped(const char *i2c_match) 458 { 459 TEE_Result ret = TEE_ERROR_GENERIC; 460 void *fdt = get_dt(); 461 size_t size = 0; 462 size_t i = 0; 463 int off = 0; 464 465 if (!fdt) 466 return TEE_ERROR_NOT_SUPPORTED; 467 468 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { 469 off = fdt_node_offset_by_compatible(fdt, off, i2c_match); 470 if (off < 0) 471 break; 472 473 if (!(_fdt_get_status(fdt, off) & DT_STATUS_OK_SEC)) { 474 EMSG("i2c%zu not enabled", i + 1); 475 continue; 476 } 477 478 if (dt_map_dev(fdt, off, &i2c_bus[i].va, &size) < 0) { 479 EMSG("i2c%zu not enabled", i + 1); 480 continue; 481 } 482 483 i2c_bus[i].pa = virt_to_phys((void *)i2c_bus[i].va); 484 ret = TEE_SUCCESS; 485 } 486 487 return ret; 488 } 489 490 static TEE_Result i2c_map_controller(void) 491 { 492 TEE_Result ret = TEE_ERROR_GENERIC; 493 size_t i = 0; 494 495 for (i = 0; i < ARRAY_SIZE(dt_i2c_match_table); i++) { 496 ret = i2c_mapped(dt_i2c_match_table[i]); 497 if (!ret || ret == TEE_ERROR_NOT_SUPPORTED) 498 return ret; 499 } 500 501 return ret; 502 } 503 #else 504 static TEE_Result i2c_map_controller(void) 505 { 506 TEE_Result ret = TEE_ERROR_GENERIC; 507 size_t n = 0; 508 509 for (n = 0; n < ARRAY_SIZE(i2c_bus); n++) { 510 if (i2c_bus[n].pa) { 511 if (get_va(i2c_bus[n].pa, &i2c_bus[n].va)) 512 EMSG("i2c%zu not enabled", n + 1); 513 else 514 ret = TEE_SUCCESS; 515 } else { 516 IMSG("i2c%zu not enabled", n + 1); 517 } 518 } 519 520 return ret; 521 } 522 #endif /* !USE_I2C_STATIC_ADDRESS */ 523 524 static TEE_Result i2c_init(void) 525 { 526 if (get_va(i2c_clk.base.pa, &i2c_clk.base.va)) 527 return TEE_ERROR_GENERIC; 528 529 if (get_va(i2c_mux.base.pa, &i2c_mux.base.va)) 530 return TEE_ERROR_GENERIC; 531 532 return i2c_map_controller(); 533 } 534 535 early_init(i2c_init); 536