1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * (c) 2020 Jorge Ramirez <jorge@foundries.io>, Foundries Ltd. 4 */ 5 #include <arm.h> 6 #include <drivers/imx_i2c.h> 7 #include <initcall.h> 8 #include <io.h> 9 #include <kernel/boot.h> 10 #include <kernel/delay.h> 11 #include <kernel/dt.h> 12 #include <libfdt.h> 13 #include <mm/core_memprot.h> 14 #include <mm/core_mmu.h> 15 #include <platform_config.h> 16 #include <stdlib.h> 17 #include <trace.h> 18 #include <util.h> 19 20 #define I2C_CLK_RATE 24000000 /* Bits per second */ 21 22 /* Utility macros (__x identifies the bus [1 .. 3]) */ 23 #define I2C_CFG_SCL(__x) (IOMUXC_I2C1_SCL_CFG_OFF + ((__x) - 1) * 0x8) 24 #define I2C_CFG_SDA(__x) (IOMUXC_I2C1_SDA_CFG_OFF + ((__x) - 1) * 0x8) 25 #define I2C_MUX_SCL(__x) (IOMUXC_I2C1_SCL_MUX_OFF + ((__x) - 1) * 0x8) 26 #define I2C_MUX_SDA(__x) (IOMUXC_I2C1_SDA_MUX_OFF + ((__x) - 1) * 0x8) 27 #if defined(CFG_MX8MM) 28 /* IOMUX */ 29 #define I2C_INP_SCL(__x) 0 /* Not implemented */ 30 #define I2C_INP_SDA(__x) 0 /* Not implemented */ 31 #define I2C_INP_VAL(__x) 0 /* Not implemented */ 32 #define I2C_MUX_VAL(__x) 0x010 33 #define I2C_CFG_VAL(__x) 0x1c3 34 /* Clock */ 35 #define I2C_CLK_CGRBM(__x) 0 /* Not implemented */ 36 #define I2C_CLK_CGR(__x) CCM_CCRG_I2C##__x 37 #elif defined(CFG_MX6ULL) 38 /* IOMUX */ 39 #define I2C_INP_SCL(__x) (IOMUXC_I2C1_SCL_INP_OFF + ((__x) - 1) * 0x8) 40 #define I2C_INP_SDA(__x) (IOMUXC_I2C1_SDA_INP_OFF + ((__x) - 1) * 0x8) 41 #define I2C_INP_VAL(__x) (((__x) == 1) ? 0x1 : 0x2) 42 #define I2C_MUX_VAL(__x) 0x012 43 #define I2C_CFG_VAL(__x) 0x1b8b0 44 /* Clock */ 45 #define I2C_CLK_CGRBM(__x) BM_CCM_CCGR2_I2C##__x##_SERIAL 46 #define I2C_CLK_CGR(__x) CCM_CCGR2 47 #else 48 #error IMX_I2C driver not supported on this platform 49 #endif 50 51 static struct io_pa_va i2c_bus[3] = { 52 #if !defined(CFG_DT) || defined(CFG_EXTERNAL_DTB_OVERLAY) 53 #if defined(I2C1_BASE) 54 [0] = { .pa = I2C1_BASE, }, 55 #endif 56 #if defined(I2C2_BASE) 57 [1] = { .pa = I2C2_BASE, }, 58 #endif 59 #if defined(I2C3_BASE) 60 [2] = { .pa = I2C3_BASE, }, 61 #endif 62 #endif 63 }; 64 65 static struct imx_i2c_clk { 66 struct io_pa_va base; 67 uint32_t i2c[ARRAY_SIZE(i2c_bus)]; 68 uint32_t cgrbm[ARRAY_SIZE(i2c_bus)]; 69 } i2c_clk = { 70 .base.pa = CCM_BASE, 71 .i2c = { I2C_CLK_CGR(1), I2C_CLK_CGR(2), I2C_CLK_CGR(3), }, 72 .cgrbm = { I2C_CLK_CGRBM(1), I2C_CLK_CGRBM(2), I2C_CLK_CGRBM(3), }, 73 }; 74 75 static struct imx_i2c_mux { 76 struct io_pa_va base; 77 struct imx_i2c_mux_regs { 78 uint32_t scl_mux; 79 uint32_t scl_cfg; 80 uint32_t scl_inp; 81 uint32_t sda_mux; 82 uint32_t sda_cfg; 83 uint32_t sda_inp; 84 } i2c[ARRAY_SIZE(i2c_bus)]; 85 } i2c_mux = { 86 .base.pa = IOMUXC_BASE, 87 .i2c = {{ .scl_mux = I2C_MUX_SCL(1), .scl_cfg = I2C_CFG_SCL(1), 88 .scl_inp = I2C_INP_SCL(1), .sda_mux = I2C_MUX_SDA(1), 89 .sda_cfg = I2C_CFG_SDA(1), .sda_inp = I2C_INP_SDA(1), }, 90 { .scl_mux = I2C_MUX_SCL(2), .scl_cfg = I2C_CFG_SCL(2), 91 .scl_inp = I2C_INP_SCL(2), .sda_mux = I2C_MUX_SDA(2), 92 .sda_cfg = I2C_CFG_SDA(2), .sda_inp = I2C_INP_SDA(2), }, 93 { .scl_mux = I2C_MUX_SCL(3), .scl_cfg = I2C_CFG_SCL(3), 94 .scl_inp = I2C_INP_SCL(3), .sda_mux = I2C_MUX_SDA(3), 95 .sda_cfg = I2C_CFG_SDA(3), .sda_inp = I2C_INP_SDA(3), },}, 96 }; 97 98 #define I2DR 0x10 99 #define I2SR 0x0C 100 #define I2CR 0x08 101 #define IFDR 0x04 102 103 #define I2CR_IEN BIT(7) 104 #define I2CR_IIEN BIT(6) 105 #define I2CR_MSTA BIT(5) 106 #define I2CR_MTX BIT(4) 107 #define I2CR_TX_NO_AK BIT(3) 108 #define I2CR_RSTA BIT(2) 109 110 #define I2SR_ICF BIT(7) 111 #define I2SR_IBB BIT(5) 112 #define I2SR_IAL BIT(4) 113 #define I2SR_IIF BIT(1) 114 #define I2SR_RX_NO_AK BIT(0) 115 116 static uint8_t i2c_io_read8(uint8_t bid, uint32_t address) 117 { 118 return io_read8(i2c_bus[bid].va + address); 119 } 120 121 static void i2c_io_write8(uint8_t bid, uint32_t address, uint8_t data) 122 { 123 return io_write8(i2c_bus[bid].va + address, data); 124 } 125 126 static bool bus_is_idle(uint32_t sr) 127 { 128 return (sr & I2SR_IBB) == 0; 129 } 130 131 static bool bus_is_busy(uint32_t sr) 132 { 133 return !bus_is_idle(sr); 134 } 135 136 static bool isr_active(uint32_t sr) 137 { 138 return (sr & I2SR_IIF) == I2SR_IIF; 139 } 140 141 static struct ifdr_pair { 142 uint32_t divider; 143 uint8_t prescaler; 144 } ifdr_table[] = { 145 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 146 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 147 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 148 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 149 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 150 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 151 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 152 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 153 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 154 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 155 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 156 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 157 { 3072, 0x1E }, { 3840, 0x1F } 158 }; 159 160 static void i2c_set_prescaler(uint8_t bid, uint32_t bps) 161 { 162 struct ifdr_pair *p = ifdr_table; 163 struct ifdr_pair *q = p + ARRAY_SIZE(ifdr_table) - 1; 164 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; 165 166 if (div < p->divider) 167 q = p; 168 else if (div > q->divider) 169 p = q; 170 171 while (p != q) { 172 if (div <= p->divider) 173 break; 174 p++; 175 } 176 177 i2c_io_write8(bid, IFDR, p->prescaler); 178 } 179 180 static void i2c_set_bus_speed(uint8_t bid, int bps) 181 { 182 vaddr_t addr = i2c_clk.base.va; 183 uint32_t val = 0; 184 185 #if defined(CFG_MX8MM) 186 addr += CCM_CCGRx_SET(i2c_clk.i2c[bid]); 187 val = CCM_CCGRx_ALWAYS_ON(0); 188 #elif defined(CFG_MX6ULL) 189 addr += i2c_clk.i2c[bid]; 190 val = i2c_clk.cgrbm[bid] | io_read32(addr); 191 #else 192 #error IMX_I2C driver not supported on this platform 193 #endif 194 io_write32(addr, val); 195 i2c_set_prescaler(bid, bps); 196 } 197 198 static TEE_Result i2c_sync_bus(uint8_t bid, bool (*match)(uint32_t), 199 uint32_t *status) 200 { 201 uint64_t tref = timeout_init_us(100000); 202 uint32_t sr = 0; 203 204 while (!timeout_elapsed(tref)) { 205 sr = i2c_io_read8(bid, I2SR); 206 if (sr & I2SR_IAL) { 207 EMSG("bus arbitration lost"); 208 i2c_io_write8(bid, I2SR, sr & ~I2SR_IAL); 209 return TEE_ERROR_COMMUNICATION; 210 } 211 if ((*match)(sr)) { 212 if (status) 213 *status = sr; 214 return TEE_SUCCESS; 215 } 216 } 217 218 return TEE_ERROR_BUSY; 219 } 220 221 static TEE_Result i2c_idle_bus(uint8_t bid) 222 { 223 uint8_t tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MSTA; 224 TEE_Result ret = TEE_SUCCESS; 225 226 i2c_io_write8(bid, I2CR, tmp); 227 ret = i2c_sync_bus(bid, &bus_is_idle, NULL); 228 i2c_io_write8(bid, I2SR, 0); 229 230 return ret; 231 } 232 233 static TEE_Result i2c_write_byte(uint8_t bid, uint8_t byte) 234 { 235 TEE_Result ret = TEE_SUCCESS; 236 uint32_t status = 0; 237 238 i2c_io_write8(bid, I2DR, byte); 239 ret = i2c_sync_bus(bid, &isr_active, &status); 240 i2c_io_write8(bid, I2SR, 0); 241 242 if (!ret && (status & I2SR_RX_NO_AK)) 243 return TEE_ERROR_BAD_STATE; 244 245 return ret; 246 } 247 248 static TEE_Result i2c_read_byte(uint8_t bid, uint8_t *p) 249 { 250 TEE_Result ret = TEE_SUCCESS; 251 252 *p = i2c_io_read8(bid, I2DR); 253 ret = i2c_sync_bus(bid, &isr_active, NULL); 254 i2c_io_write8(bid, I2SR, 0); 255 256 return ret; 257 } 258 259 static TEE_Result i2c_write_data(uint8_t bid, const uint8_t *buf, int len) 260 { 261 TEE_Result ret = TEE_SUCCESS; 262 uint32_t tmp = 0; 263 264 if (!len) 265 return TEE_SUCCESS; 266 267 tmp = i2c_io_read8(bid, I2CR) | I2CR_MTX | I2CR_TX_NO_AK; 268 i2c_io_write8(bid, I2CR, tmp); 269 270 while (len--) { 271 ret = i2c_write_byte(bid, *buf++); 272 if (ret) 273 return ret; 274 } 275 276 return ret; 277 } 278 279 static TEE_Result i2c_read_data(uint8_t bid, uint8_t *buf, int len) 280 { 281 TEE_Result ret = TEE_SUCCESS; 282 uint8_t dummy = 0; 283 uint32_t tmp = 0; 284 285 if (!len) 286 return TEE_SUCCESS; 287 288 tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MTX; 289 tmp = (len == 1) ? tmp | I2CR_TX_NO_AK : tmp & ~I2CR_TX_NO_AK; 290 i2c_io_write8(bid, I2CR, tmp); 291 i2c_io_read8(bid, I2DR); 292 293 ret = i2c_read_byte(bid, &dummy); 294 if (ret) 295 return ret; 296 297 /* 298 * A data transfer ends when the master signals a stop; for a master 299 * receiver to terminate a transfer it must inform the slave transmiter 300 * by not acknowledging the last data byte. This is done by setting the 301 * transmit acknowledge bit before reading the next-to-last byte. 302 */ 303 do { 304 if (len == 2) { 305 tmp = i2c_io_read8(bid, I2CR) | I2CR_TX_NO_AK; 306 i2c_io_write8(bid, I2CR, tmp); 307 } 308 309 ret = i2c_read_byte(bid, buf++); 310 if (ret) 311 return ret; 312 } while (len--); 313 314 return ret; 315 } 316 317 static TEE_Result i2c_init_transfer(uint8_t bid, uint8_t chip) 318 { 319 TEE_Result ret = TEE_SUCCESS; 320 uint32_t tmp = 0; 321 322 ret = i2c_idle_bus(bid); 323 if (ret) 324 return ret; 325 326 /* Enable the interface */ 327 i2c_io_write8(bid, I2CR, I2CR_IEN); 328 329 tmp = i2c_io_read8(bid, I2CR) | I2CR_MSTA; 330 i2c_io_write8(bid, I2CR, tmp); 331 332 /* Wait until the bus is active */ 333 ret = i2c_sync_bus(bid, &bus_is_busy, NULL); 334 if (ret) 335 return ret; 336 337 /* Slave address on the bus */ 338 return i2c_write_data(bid, &chip, 1); 339 } 340 341 TEE_Result imx_i2c_read(uint8_t bid, uint8_t chip, uint8_t *buf, int len) 342 { 343 TEE_Result ret = TEE_SUCCESS; 344 345 if (bid >= ARRAY_SIZE(i2c_bus)) 346 return TEE_ERROR_BAD_PARAMETERS; 347 348 if ((len && !buf) || chip > 0x7F) 349 return TEE_ERROR_BAD_PARAMETERS; 350 351 if (!i2c_bus[bid].va) 352 return TEE_ERROR_BAD_PARAMETERS; 353 354 ret = i2c_init_transfer(bid, chip << 1 | BIT(0)); 355 if (!ret) 356 ret = i2c_read_data(bid, buf, len); 357 358 if (i2c_idle_bus(bid)) 359 IMSG("bus not idle"); 360 361 return ret; 362 } 363 364 TEE_Result imx_i2c_write(uint8_t bid, uint8_t chip, const uint8_t *buf, int len) 365 { 366 TEE_Result ret = TEE_SUCCESS; 367 368 if (bid >= ARRAY_SIZE(i2c_bus)) 369 return TEE_ERROR_BAD_PARAMETERS; 370 371 if ((len && !buf) || chip > 0x7F) 372 return TEE_ERROR_BAD_PARAMETERS; 373 374 if (!i2c_bus[bid].va) 375 return TEE_ERROR_BAD_PARAMETERS; 376 377 ret = i2c_init_transfer(bid, chip << 1); 378 if (!ret) 379 ret = i2c_write_data(bid, buf, len); 380 381 if (i2c_idle_bus(bid)) 382 IMSG("bus not idle"); 383 384 return ret; 385 } 386 387 TEE_Result imx_i2c_probe(uint8_t bid, uint8_t chip) 388 { 389 if (bid >= ARRAY_SIZE(i2c_bus)) 390 return TEE_ERROR_BAD_PARAMETERS; 391 392 if (!i2c_bus[bid].va) 393 return TEE_ERROR_BAD_PARAMETERS; 394 395 if (chip > 0x7F) 396 return TEE_ERROR_BAD_PARAMETERS; 397 398 return imx_i2c_write(bid, chip, NULL, 0); 399 } 400 401 /* 402 * I2C bus initialization: configure the IOMUX and enable the clock. 403 * @bid: Bus ID: (0=I2C1), (1=I2C2), (2=I2C3). 404 * @bps: Bus baud rate, in bits per second. 405 */ 406 TEE_Result imx_i2c_init(uint8_t bid, int bps) 407 { 408 struct imx_i2c_mux *mux = &i2c_mux; 409 410 if (bid >= ARRAY_SIZE(i2c_bus)) 411 return TEE_ERROR_BAD_PARAMETERS; 412 413 if (!bps) 414 return TEE_ERROR_BAD_PARAMETERS; 415 416 if (!i2c_bus[bid].va) 417 return TEE_ERROR_BAD_PARAMETERS; 418 419 io_write32(mux->base.va + mux->i2c[bid].scl_mux, I2C_MUX_VAL(bid)); 420 io_write32(mux->base.va + mux->i2c[bid].scl_cfg, I2C_CFG_VAL(bid)); 421 if (mux->i2c[bid].scl_inp) 422 io_write32(mux->base.va + mux->i2c[bid].scl_inp, 423 I2C_INP_VAL(bid + 1)); 424 425 io_write32(mux->base.va + mux->i2c[bid].sda_mux, I2C_MUX_VAL(bid)); 426 io_write32(mux->base.va + mux->i2c[bid].sda_cfg, I2C_CFG_VAL(bid)); 427 if (mux->i2c[bid].sda_inp) 428 io_write32(mux->base.va + mux->i2c[bid].sda_inp, 429 I2C_INP_VAL(bid + 1)); 430 431 /* Baud rate in bits per second */ 432 i2c_set_bus_speed(bid, bps); 433 434 return TEE_SUCCESS; 435 } 436 437 static TEE_Result get_va(paddr_t pa, vaddr_t *va) 438 { 439 if (!core_mmu_add_mapping(MEM_AREA_IO_SEC, pa, 0x10000)) 440 return TEE_ERROR_GENERIC; 441 442 *va = (vaddr_t)phys_to_virt(pa, MEM_AREA_IO_SEC); 443 if (*va) 444 return TEE_SUCCESS; 445 446 return TEE_ERROR_GENERIC; 447 } 448 449 #if defined(CFG_DT) && !defined(CFG_EXTERNAL_DTB_OVERLAY) 450 static const char *const dt_i2c_match_table[] = { 451 "fsl,imx21-i2c", 452 }; 453 454 static TEE_Result i2c_mapped(const char *i2c_match) 455 { 456 TEE_Result ret = TEE_ERROR_GENERIC; 457 void *fdt = get_dt(); 458 size_t size = 0; 459 size_t i = 0; 460 int off = 0; 461 462 if (!fdt) 463 return TEE_ERROR_NOT_SUPPORTED; 464 465 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { 466 off = fdt_node_offset_by_compatible(fdt, off, i2c_match); 467 if (off < 0) 468 break; 469 470 if (!(_fdt_get_status(fdt, off) & DT_STATUS_OK_SEC)) { 471 EMSG("i2c%zu not enabled", i + 1); 472 continue; 473 } 474 475 if (dt_map_dev(fdt, off, &i2c_bus[i].va, &size) < 0) { 476 EMSG("i2c%zu not enabled", i + 1); 477 continue; 478 } 479 480 i2c_bus[i].pa = virt_to_phys((void *)i2c_bus[i].va); 481 ret = TEE_SUCCESS; 482 } 483 484 return ret; 485 } 486 487 static TEE_Result i2c_map_controller(void) 488 { 489 TEE_Result ret = TEE_ERROR_GENERIC; 490 size_t i = 0; 491 492 for (i = 0; i < ARRAY_SIZE(dt_i2c_match_table); i++) { 493 ret = i2c_mapped(dt_i2c_match_table[i]); 494 if (!ret || ret == TEE_ERROR_NOT_SUPPORTED) 495 return ret; 496 } 497 498 return ret; 499 } 500 #else 501 static TEE_Result i2c_map_controller(void) 502 { 503 TEE_Result ret = TEE_ERROR_GENERIC; 504 size_t n = 0; 505 506 for (n = 0; n < ARRAY_SIZE(i2c_bus); n++) { 507 if (i2c_bus[n].pa) { 508 if (get_va(i2c_bus[n].pa, &i2c_bus[n].va)) 509 EMSG("i2c%zu not enabled", n + 1); 510 else 511 ret = TEE_SUCCESS; 512 } else { 513 IMSG("i2c%zu not enabled", n + 1); 514 } 515 } 516 517 return ret; 518 } 519 #endif 520 521 static TEE_Result i2c_init(void) 522 { 523 if (get_va(i2c_clk.base.pa, &i2c_clk.base.va)) 524 return TEE_ERROR_GENERIC; 525 526 if (get_va(i2c_mux.base.pa, &i2c_mux.base.va)) 527 return TEE_ERROR_GENERIC; 528 529 return i2c_map_controller(); 530 } 531 532 early_init(i2c_init); 533