1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * (c) 2020 Jorge Ramirez <jorge@foundries.io>, Foundries Ltd. 4 */ 5 #include <arm.h> 6 #include <drivers/imx_i2c.h> 7 #include <initcall.h> 8 #include <io.h> 9 #include <kernel/boot.h> 10 #include <kernel/delay.h> 11 #include <kernel/dt.h> 12 #include <libfdt.h> 13 #include <mm/core_memprot.h> 14 #include <mm/core_mmu.h> 15 #include <platform_config.h> 16 #include <stdlib.h> 17 #include <trace.h> 18 #include <util.h> 19 20 #define I2C_CLK_RATE 24000000 /* Bits per second */ 21 22 #define USE_I2C_STATIC_ADDRESS \ 23 (!defined(CFG_DT) || defined(CFG_EXTERNAL_DTB_OVERLAY)) 24 25 /* SoC optional: iomuxc daisy configuration register */ 26 #ifndef I2C_INP_SCL 27 #define I2C_INP_SCL(__x) 0 28 #define I2C_INP_SDA(__x) 0 29 #define I2C_INP_VAL(__x) 0 30 #endif 31 32 /* SoC optional: clock gate bitmask */ 33 #ifndef I2C_CLK_CGRBM 34 #define I2C_CLK_CGRBM(__x) 0 35 #endif 36 37 static struct io_pa_va i2c_bus[3] = { 38 #if USE_I2C_STATIC_ADDRESS 39 #if defined(I2C1_BASE) 40 [0] = { .pa = I2C1_BASE, }, 41 #endif 42 #if defined(I2C2_BASE) 43 [1] = { .pa = I2C2_BASE, }, 44 #endif 45 #if defined(I2C3_BASE) 46 [2] = { .pa = I2C3_BASE, }, 47 #endif 48 #endif 49 }; 50 51 static struct imx_i2c_clk { 52 struct io_pa_va base; 53 uint32_t i2c[ARRAY_SIZE(i2c_bus)]; 54 uint32_t cgrbm[ARRAY_SIZE(i2c_bus)]; 55 } i2c_clk = { 56 .base.pa = CCM_BASE, 57 .i2c = { I2C_CLK_CGR(1), I2C_CLK_CGR(2), I2C_CLK_CGR(3), }, 58 .cgrbm = { I2C_CLK_CGRBM(1), I2C_CLK_CGRBM(2), I2C_CLK_CGRBM(3), }, 59 }; 60 61 static struct imx_i2c_mux { 62 struct io_pa_va base; 63 struct imx_i2c_mux_regs { 64 uint32_t scl_mux; 65 uint32_t scl_cfg; 66 uint32_t scl_inp; 67 uint32_t sda_mux; 68 uint32_t sda_cfg; 69 uint32_t sda_inp; 70 } i2c[ARRAY_SIZE(i2c_bus)]; 71 } i2c_mux = { 72 .base.pa = IOMUXC_BASE, 73 .i2c = {{ .scl_mux = I2C_MUX_SCL(1), .scl_cfg = I2C_CFG_SCL(1), 74 .scl_inp = I2C_INP_SCL(1), .sda_mux = I2C_MUX_SDA(1), 75 .sda_cfg = I2C_CFG_SDA(1), .sda_inp = I2C_INP_SDA(1), }, 76 { .scl_mux = I2C_MUX_SCL(2), .scl_cfg = I2C_CFG_SCL(2), 77 .scl_inp = I2C_INP_SCL(2), .sda_mux = I2C_MUX_SDA(2), 78 .sda_cfg = I2C_CFG_SDA(2), .sda_inp = I2C_INP_SDA(2), }, 79 { .scl_mux = I2C_MUX_SCL(3), .scl_cfg = I2C_CFG_SCL(3), 80 .scl_inp = I2C_INP_SCL(3), .sda_mux = I2C_MUX_SDA(3), 81 .sda_cfg = I2C_CFG_SDA(3), .sda_inp = I2C_INP_SDA(3), },}, 82 }; 83 84 #define I2DR 0x10 85 #define I2SR 0x0C 86 #define I2CR 0x08 87 #define IFDR 0x04 88 89 #define I2CR_IEN BIT(7) 90 #define I2CR_IIEN BIT(6) 91 #define I2CR_MSTA BIT(5) 92 #define I2CR_MTX BIT(4) 93 #define I2CR_TX_NO_AK BIT(3) 94 #define I2CR_RSTA BIT(2) 95 96 #define I2SR_ICF BIT(7) 97 #define I2SR_IBB BIT(5) 98 #define I2SR_IAL BIT(4) 99 #define I2SR_IIF BIT(1) 100 #define I2SR_RX_NO_AK BIT(0) 101 102 static uint8_t i2c_io_read8(uint8_t bid, uint32_t address) 103 { 104 return io_read8(i2c_bus[bid].va + address); 105 } 106 107 static void i2c_io_write8(uint8_t bid, uint32_t address, uint8_t data) 108 { 109 return io_write8(i2c_bus[bid].va + address, data); 110 } 111 112 static bool bus_is_idle(uint32_t sr) 113 { 114 return (sr & I2SR_IBB) == 0; 115 } 116 117 static bool bus_is_busy(uint32_t sr) 118 { 119 return !bus_is_idle(sr); 120 } 121 122 static bool isr_active(uint32_t sr) 123 { 124 return (sr & I2SR_IIF) == I2SR_IIF; 125 } 126 127 static struct ifdr_pair { 128 uint32_t divider; 129 uint8_t prescaler; 130 } ifdr_table[] = { 131 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 132 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 133 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 134 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 135 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 136 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 137 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 138 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 139 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 140 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 141 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 142 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 143 { 3072, 0x1E }, { 3840, 0x1F } 144 }; 145 146 static void i2c_set_prescaler(uint8_t bid, uint32_t bps) 147 { 148 struct ifdr_pair *p = ifdr_table; 149 struct ifdr_pair *q = p + ARRAY_SIZE(ifdr_table) - 1; 150 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; 151 152 if (div < p->divider) 153 q = p; 154 else if (div > q->divider) 155 p = q; 156 157 while (p != q) { 158 if (div <= p->divider) 159 break; 160 p++; 161 } 162 163 i2c_io_write8(bid, IFDR, p->prescaler); 164 } 165 166 static void i2c_set_bus_speed(uint8_t bid, int bps) 167 { 168 vaddr_t addr = i2c_clk.base.va; 169 uint32_t val = 0; 170 171 #if defined(CFG_MX8MM) 172 addr += CCM_CCGRx_SET(i2c_clk.i2c[bid]); 173 val = CCM_CCGRx_ALWAYS_ON(0); 174 #elif defined(CFG_MX6ULL) 175 addr += i2c_clk.i2c[bid]; 176 val = i2c_clk.cgrbm[bid] | io_read32(addr); 177 #endif 178 io_write32(addr, val); 179 i2c_set_prescaler(bid, bps); 180 } 181 182 static TEE_Result i2c_sync_bus(uint8_t bid, bool (*match)(uint32_t), 183 uint32_t *status) 184 { 185 uint64_t tref = timeout_init_us(100000); 186 uint32_t sr = 0; 187 188 while (!timeout_elapsed(tref)) { 189 sr = i2c_io_read8(bid, I2SR); 190 if (sr & I2SR_IAL) { 191 EMSG("bus arbitration lost"); 192 i2c_io_write8(bid, I2SR, sr & ~I2SR_IAL); 193 return TEE_ERROR_COMMUNICATION; 194 } 195 if ((*match)(sr)) { 196 if (status) 197 *status = sr; 198 return TEE_SUCCESS; 199 } 200 } 201 202 return TEE_ERROR_BUSY; 203 } 204 205 static TEE_Result i2c_idle_bus(uint8_t bid) 206 { 207 uint8_t tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MSTA; 208 TEE_Result ret = TEE_SUCCESS; 209 210 i2c_io_write8(bid, I2CR, tmp); 211 ret = i2c_sync_bus(bid, &bus_is_idle, NULL); 212 i2c_io_write8(bid, I2SR, 0); 213 214 return ret; 215 } 216 217 static TEE_Result i2c_write_byte(uint8_t bid, uint8_t byte) 218 { 219 TEE_Result ret = TEE_SUCCESS; 220 uint32_t status = 0; 221 222 i2c_io_write8(bid, I2DR, byte); 223 ret = i2c_sync_bus(bid, &isr_active, &status); 224 i2c_io_write8(bid, I2SR, 0); 225 226 if (!ret && (status & I2SR_RX_NO_AK)) 227 return TEE_ERROR_BAD_STATE; 228 229 return ret; 230 } 231 232 static TEE_Result i2c_read_byte(uint8_t bid, uint8_t *p) 233 { 234 TEE_Result ret = TEE_SUCCESS; 235 236 *p = i2c_io_read8(bid, I2DR); 237 ret = i2c_sync_bus(bid, &isr_active, NULL); 238 i2c_io_write8(bid, I2SR, 0); 239 240 return ret; 241 } 242 243 static TEE_Result i2c_write_data(uint8_t bid, const uint8_t *buf, int len) 244 { 245 TEE_Result ret = TEE_SUCCESS; 246 uint32_t tmp = 0; 247 248 if (!len) 249 return TEE_SUCCESS; 250 251 tmp = i2c_io_read8(bid, I2CR) | I2CR_MTX | I2CR_TX_NO_AK; 252 i2c_io_write8(bid, I2CR, tmp); 253 254 while (len--) { 255 ret = i2c_write_byte(bid, *buf++); 256 if (ret) 257 return ret; 258 } 259 260 return ret; 261 } 262 263 static TEE_Result i2c_read_data(uint8_t bid, uint8_t *buf, int len) 264 { 265 TEE_Result ret = TEE_SUCCESS; 266 uint8_t dummy = 0; 267 uint32_t tmp = 0; 268 269 if (!len) 270 return TEE_SUCCESS; 271 272 tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MTX; 273 tmp = (len == 1) ? tmp | I2CR_TX_NO_AK : tmp & ~I2CR_TX_NO_AK; 274 i2c_io_write8(bid, I2CR, tmp); 275 i2c_io_read8(bid, I2DR); 276 277 ret = i2c_read_byte(bid, &dummy); 278 if (ret) 279 return ret; 280 281 /* 282 * A data transfer ends when the master signals a stop; for a master 283 * receiver to terminate a transfer it must inform the slave transmiter 284 * by not acknowledging the last data byte. This is done by setting the 285 * transmit acknowledge bit before reading the next-to-last byte. 286 */ 287 do { 288 if (len == 2) { 289 tmp = i2c_io_read8(bid, I2CR) | I2CR_TX_NO_AK; 290 i2c_io_write8(bid, I2CR, tmp); 291 } 292 293 ret = i2c_read_byte(bid, buf++); 294 if (ret) 295 return ret; 296 } while (len--); 297 298 return ret; 299 } 300 301 static TEE_Result i2c_init_transfer(uint8_t bid, uint8_t chip) 302 { 303 TEE_Result ret = TEE_SUCCESS; 304 uint32_t tmp = 0; 305 306 ret = i2c_idle_bus(bid); 307 if (ret) 308 return ret; 309 310 /* Enable the interface */ 311 i2c_io_write8(bid, I2CR, I2CR_IEN); 312 313 tmp = i2c_io_read8(bid, I2CR) | I2CR_MSTA; 314 i2c_io_write8(bid, I2CR, tmp); 315 316 /* Wait until the bus is active */ 317 ret = i2c_sync_bus(bid, &bus_is_busy, NULL); 318 if (ret) 319 return ret; 320 321 /* Slave address on the bus */ 322 return i2c_write_data(bid, &chip, 1); 323 } 324 325 TEE_Result imx_i2c_read(uint8_t bid, uint8_t chip, uint8_t *buf, int len) 326 { 327 TEE_Result ret = TEE_SUCCESS; 328 329 if (bid >= ARRAY_SIZE(i2c_bus)) 330 return TEE_ERROR_BAD_PARAMETERS; 331 332 if ((len && !buf) || chip > 0x7F) 333 return TEE_ERROR_BAD_PARAMETERS; 334 335 if (!i2c_bus[bid].va) 336 return TEE_ERROR_BAD_PARAMETERS; 337 338 ret = i2c_init_transfer(bid, chip << 1 | BIT(0)); 339 if (!ret) 340 ret = i2c_read_data(bid, buf, len); 341 342 if (i2c_idle_bus(bid)) 343 IMSG("bus not idle"); 344 345 return ret; 346 } 347 348 TEE_Result imx_i2c_write(uint8_t bid, uint8_t chip, const uint8_t *buf, int len) 349 { 350 TEE_Result ret = TEE_SUCCESS; 351 352 if (bid >= ARRAY_SIZE(i2c_bus)) 353 return TEE_ERROR_BAD_PARAMETERS; 354 355 if ((len && !buf) || chip > 0x7F) 356 return TEE_ERROR_BAD_PARAMETERS; 357 358 if (!i2c_bus[bid].va) 359 return TEE_ERROR_BAD_PARAMETERS; 360 361 ret = i2c_init_transfer(bid, chip << 1); 362 if (!ret) 363 ret = i2c_write_data(bid, buf, len); 364 365 if (i2c_idle_bus(bid)) 366 IMSG("bus not idle"); 367 368 return ret; 369 } 370 371 TEE_Result imx_i2c_probe(uint8_t bid, uint8_t chip) 372 { 373 if (bid >= ARRAY_SIZE(i2c_bus)) 374 return TEE_ERROR_BAD_PARAMETERS; 375 376 if (!i2c_bus[bid].va) 377 return TEE_ERROR_BAD_PARAMETERS; 378 379 if (chip > 0x7F) 380 return TEE_ERROR_BAD_PARAMETERS; 381 382 return imx_i2c_write(bid, chip, NULL, 0); 383 } 384 385 /* 386 * I2C bus initialization: configure the IOMUX and enable the clock. 387 * @bid: Bus ID: (0=I2C1), (1=I2C2), (2=I2C3). 388 * @bps: Bus baud rate, in bits per second. 389 */ 390 TEE_Result imx_i2c_init(uint8_t bid, int bps) 391 { 392 struct imx_i2c_mux *mux = &i2c_mux; 393 394 if (bid >= ARRAY_SIZE(i2c_bus)) 395 return TEE_ERROR_BAD_PARAMETERS; 396 397 if (!bps) 398 return TEE_ERROR_BAD_PARAMETERS; 399 400 if (!i2c_bus[bid].va) 401 return TEE_ERROR_BAD_PARAMETERS; 402 403 io_write32(mux->base.va + mux->i2c[bid].scl_mux, I2C_MUX_VAL(bid)); 404 io_write32(mux->base.va + mux->i2c[bid].scl_cfg, I2C_CFG_VAL(bid)); 405 if (mux->i2c[bid].scl_inp) 406 io_write32(mux->base.va + mux->i2c[bid].scl_inp, 407 I2C_INP_VAL(mux->i2c[bid].scl_inp)); 408 409 io_write32(mux->base.va + mux->i2c[bid].sda_mux, I2C_MUX_VAL(bid)); 410 io_write32(mux->base.va + mux->i2c[bid].sda_cfg, I2C_CFG_VAL(bid)); 411 if (mux->i2c[bid].sda_inp) 412 io_write32(mux->base.va + mux->i2c[bid].sda_inp, 413 I2C_INP_VAL(mux->i2c[bid].sda_inp)); 414 415 /* Baud rate in bits per second */ 416 i2c_set_bus_speed(bid, bps); 417 418 return TEE_SUCCESS; 419 } 420 421 static TEE_Result get_va(paddr_t pa, vaddr_t *va) 422 { 423 if (!core_mmu_add_mapping(MEM_AREA_IO_SEC, pa, 0x10000)) 424 return TEE_ERROR_GENERIC; 425 426 *va = (vaddr_t)phys_to_virt(pa, MEM_AREA_IO_SEC); 427 if (*va) 428 return TEE_SUCCESS; 429 430 return TEE_ERROR_GENERIC; 431 } 432 433 #if !USE_I2C_STATIC_ADDRESS 434 static const char *const dt_i2c_match_table[] = { 435 "fsl,imx21-i2c", 436 }; 437 438 static TEE_Result i2c_mapped(const char *i2c_match) 439 { 440 TEE_Result ret = TEE_ERROR_GENERIC; 441 void *fdt = get_dt(); 442 size_t size = 0; 443 size_t i = 0; 444 int off = 0; 445 446 if (!fdt) 447 return TEE_ERROR_NOT_SUPPORTED; 448 449 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { 450 off = fdt_node_offset_by_compatible(fdt, off, i2c_match); 451 if (off < 0) 452 break; 453 454 if (!(_fdt_get_status(fdt, off) & DT_STATUS_OK_SEC)) { 455 EMSG("i2c%zu not enabled", i + 1); 456 continue; 457 } 458 459 if (dt_map_dev(fdt, off, &i2c_bus[i].va, &size) < 0) { 460 EMSG("i2c%zu not enabled", i + 1); 461 continue; 462 } 463 464 i2c_bus[i].pa = virt_to_phys((void *)i2c_bus[i].va); 465 ret = TEE_SUCCESS; 466 } 467 468 return ret; 469 } 470 471 static TEE_Result i2c_map_controller(void) 472 { 473 TEE_Result ret = TEE_ERROR_GENERIC; 474 size_t i = 0; 475 476 for (i = 0; i < ARRAY_SIZE(dt_i2c_match_table); i++) { 477 ret = i2c_mapped(dt_i2c_match_table[i]); 478 if (!ret || ret == TEE_ERROR_NOT_SUPPORTED) 479 return ret; 480 } 481 482 return ret; 483 } 484 #else 485 static TEE_Result i2c_map_controller(void) 486 { 487 TEE_Result ret = TEE_ERROR_GENERIC; 488 size_t n = 0; 489 490 for (n = 0; n < ARRAY_SIZE(i2c_bus); n++) { 491 if (i2c_bus[n].pa) { 492 if (get_va(i2c_bus[n].pa, &i2c_bus[n].va)) 493 EMSG("i2c%zu not enabled", n + 1); 494 else 495 ret = TEE_SUCCESS; 496 } else { 497 IMSG("i2c%zu not enabled", n + 1); 498 } 499 } 500 501 return ret; 502 } 503 #endif 504 505 static TEE_Result i2c_init(void) 506 { 507 if (get_va(i2c_clk.base.pa, &i2c_clk.base.va)) 508 return TEE_ERROR_GENERIC; 509 510 if (get_va(i2c_mux.base.pa, &i2c_mux.base.va)) 511 return TEE_ERROR_GENERIC; 512 513 return i2c_map_controller(); 514 } 515 516 early_init(i2c_init); 517