1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * (c) 2020 Jorge Ramirez <jorge@foundries.io>, Foundries Ltd. 4 */ 5 #include <arm.h> 6 #include <drivers/imx_i2c.h> 7 #include <initcall.h> 8 #include <io.h> 9 #include <kernel/boot.h> 10 #include <kernel/delay.h> 11 #include <kernel/dt.h> 12 #include <libfdt.h> 13 #include <mm/core_memprot.h> 14 #include <mm/core_mmu.h> 15 #include <platform_config.h> 16 #include <stdlib.h> 17 #include <trace.h> 18 #include <util.h> 19 20 #define I2C_CLK_RATE 24000000 /* Bits per second */ 21 22 /* Utility macros (__x identifies the bus [1 .. 3]) */ 23 #define I2C_CFG_SCL(__x) (IOMUXC_I2C1_SCL_CFG_OFF + ((__x) - 1) * 0x8) 24 #define I2C_CFG_SDA(__x) (IOMUXC_I2C1_SDA_CFG_OFF + ((__x) - 1) * 0x8) 25 #define I2C_MUX_SCL(__x) (IOMUXC_I2C1_SCL_MUX_OFF + ((__x) - 1) * 0x8) 26 #define I2C_MUX_SDA(__x) (IOMUXC_I2C1_SDA_MUX_OFF + ((__x) - 1) * 0x8) 27 #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) || defined(CFG_MX8MP) 28 /* IOMUX */ 29 #define I2C_INP_SCL(__x) 0 /* Not implemented */ 30 #define I2C_INP_SDA(__x) 0 /* Not implemented */ 31 #define I2C_INP_VAL(__x) 0 /* Not implemented */ 32 #define I2C_MUX_VAL(__x) 0x010 33 #define I2C_CFG_VAL(__x) 0x1c3 34 /* Clock */ 35 #define I2C_CLK_CGRBM(__x) 0 /* Not implemented */ 36 #define I2C_CLK_CGR6BM(__x) 0 37 #define I2C_CLK_CGR(__x) CCM_CCRG_I2C##__x 38 #elif defined(CFG_MX6ULL) 39 /* IOMUX */ 40 #define I2C_INP_SCL(__x) (IOMUXC_I2C1_SCL_INP_OFF + ((__x) - 1) * 0x8) 41 #define I2C_INP_SDA(__x) (IOMUXC_I2C1_SDA_INP_OFF + ((__x) - 1) * 0x8) 42 #define I2C_INP_VAL(__x) (((__x) == 1) ? 0x1 : 0x2) 43 #define I2C_MUX_VAL(__x) 0x012 44 #define I2C_CFG_VAL(__x) 0x1b8b0 45 /* Clock */ 46 #define I2C_CLK_CGRBM(__x) BM_CCM_CCGR2_I2C##__x##_SERIAL 47 #define I2C_CLK_CGR6BM(__x) BM_CCM_CCGR6_I2C##__x##_SERIAL 48 #define I2C_CLK_CGR(__x) (((__x) == 4) ? CCM_CCGR6 : CCM_CCGR2) 49 #else 50 #error IMX_I2C driver not supported on this platform 51 #endif 52 53 #if !defined(CFG_MX8MP) 54 static struct io_pa_va i2c_bus[4] = { 55 #if !defined(CFG_DT) || defined(CFG_EXTERNAL_DTB_OVERLAY) 56 #if defined(I2C1_BASE) 57 [0] = { .pa = I2C1_BASE, }, 58 #endif 59 #if defined(I2C2_BASE) 60 [1] = { .pa = I2C2_BASE, }, 61 #endif 62 #if defined(I2C3_BASE) 63 [2] = { .pa = I2C3_BASE, }, 64 #endif 65 #if defined(I2C4_BASE) 66 [3] = { .pa = I2C4_BASE, }, 67 #endif 68 #endif 69 }; 70 #else 71 static struct io_pa_va i2c_bus[6] = { 72 #if !defined(CFG_DT) || defined(CFG_EXTERNAL_DTB_OVERLAY) 73 #if defined(I2C1_BASE) 74 [0] = { .pa = I2C1_BASE, }, 75 #endif 76 #if defined(I2C2_BASE) 77 [1] = { .pa = I2C2_BASE, }, 78 #endif 79 #if defined(I2C3_BASE) 80 [2] = { .pa = I2C3_BASE, }, 81 #endif 82 #if defined(I2C4_BASE) 83 [3] = { .pa = I2C4_BASE, }, 84 #endif 85 #if defined(I2C5_BASE) 86 [4] = { .pa = I2C5_BASE, }, 87 #endif 88 #if defined(I2C6_BASE) 89 [5] = { .pa = I2C6_BASE, }, 90 #endif 91 92 #endif 93 }; 94 #endif 95 96 static struct imx_i2c_clk { 97 struct io_pa_va base; 98 uint32_t i2c[ARRAY_SIZE(i2c_bus)]; 99 uint32_t cgrbm[ARRAY_SIZE(i2c_bus)]; 100 } i2c_clk = { 101 .base.pa = CCM_BASE, 102 .i2c = { I2C_CLK_CGR(1), I2C_CLK_CGR(2), I2C_CLK_CGR(3), I2C_CLK_CGR(4), }, 103 .cgrbm = { I2C_CLK_CGRBM(1), I2C_CLK_CGRBM(2), I2C_CLK_CGRBM(3), I2C_CLK_CGR6BM(4),}, 104 }; 105 106 static struct imx_i2c_mux { 107 struct io_pa_va base; 108 struct imx_i2c_mux_regs { 109 uint32_t scl_mux; 110 uint32_t scl_cfg; 111 uint32_t scl_inp; 112 uint32_t sda_mux; 113 uint32_t sda_cfg; 114 uint32_t sda_inp; 115 } i2c[ARRAY_SIZE(i2c_bus)]; 116 } i2c_mux = { 117 .base.pa = IOMUXC_BASE, 118 .i2c = {{ .scl_mux = I2C_MUX_SCL(1), .scl_cfg = I2C_CFG_SCL(1), 119 .scl_inp = I2C_INP_SCL(1), .sda_mux = I2C_MUX_SDA(1), 120 .sda_cfg = I2C_CFG_SDA(1), .sda_inp = I2C_INP_SDA(1), }, 121 { .scl_mux = I2C_MUX_SCL(2), .scl_cfg = I2C_CFG_SCL(2), 122 .scl_inp = I2C_INP_SCL(2), .sda_mux = I2C_MUX_SDA(2), 123 .sda_cfg = I2C_CFG_SDA(2), .sda_inp = I2C_INP_SDA(2), }, 124 { .scl_mux = I2C_MUX_SCL(3), .scl_cfg = I2C_CFG_SCL(3), 125 .scl_inp = I2C_INP_SCL(3), .sda_mux = I2C_MUX_SDA(3), 126 .sda_cfg = I2C_CFG_SDA(3), .sda_inp = I2C_INP_SDA(3), }, 127 { .scl_mux = I2C_MUX_SCL(4), .scl_cfg = I2C_CFG_SCL(4), 128 .scl_inp = I2C_INP_SCL(4), .sda_mux = I2C_MUX_SDA(4), 129 .sda_cfg = I2C_CFG_SDA(4), .sda_inp = I2C_INP_SDA(4), },}, 130 }; 131 132 #define I2DR 0x10 133 #define I2SR 0x0C 134 #define I2CR 0x08 135 #define IFDR 0x04 136 137 #define I2CR_IEN BIT(7) 138 #define I2CR_IIEN BIT(6) 139 #define I2CR_MSTA BIT(5) 140 #define I2CR_MTX BIT(4) 141 #define I2CR_TX_NO_AK BIT(3) 142 #define I2CR_RSTA BIT(2) 143 144 #define I2SR_ICF BIT(7) 145 #define I2SR_IBB BIT(5) 146 #define I2SR_IAL BIT(4) 147 #define I2SR_IIF BIT(1) 148 #define I2SR_RX_NO_AK BIT(0) 149 150 static uint8_t i2c_io_read8(uint8_t bid, uint32_t address) 151 { 152 return io_read8(i2c_bus[bid].va + address); 153 } 154 155 static void i2c_io_write8(uint8_t bid, uint32_t address, uint8_t data) 156 { 157 return io_write8(i2c_bus[bid].va + address, data); 158 } 159 160 static bool bus_is_idle(uint32_t sr) 161 { 162 return (sr & I2SR_IBB) == 0; 163 } 164 165 static bool bus_is_busy(uint32_t sr) 166 { 167 return !bus_is_idle(sr); 168 } 169 170 static bool isr_active(uint32_t sr) 171 { 172 return (sr & I2SR_IIF) == I2SR_IIF; 173 } 174 175 static struct ifdr_pair { 176 uint32_t divider; 177 uint8_t prescaler; 178 } ifdr_table[] = { 179 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 180 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 181 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 182 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 183 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 184 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 185 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 186 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 187 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 188 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 189 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 190 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 191 { 3072, 0x1E }, { 3840, 0x1F } 192 }; 193 194 static void i2c_set_prescaler(uint8_t bid, uint32_t bps) 195 { 196 struct ifdr_pair *p = ifdr_table; 197 struct ifdr_pair *q = p + ARRAY_SIZE(ifdr_table) - 1; 198 uint32_t div = (I2C_CLK_RATE + bps - 1) / bps; 199 200 if (div < p->divider) 201 q = p; 202 else if (div > q->divider) 203 p = q; 204 205 while (p != q) { 206 if (div <= p->divider) 207 break; 208 p++; 209 } 210 211 i2c_io_write8(bid, IFDR, p->prescaler); 212 } 213 214 static void i2c_set_bus_speed(uint8_t bid, int bps) 215 { 216 vaddr_t addr = i2c_clk.base.va; 217 uint32_t val = 0; 218 219 #if defined(CFG_MX8MM) || defined(CFG_MX8MQ) || defined(CFG_MX8MP) 220 addr += CCM_CCGRx_SET(i2c_clk.i2c[bid]); 221 val = CCM_CCGRx_ALWAYS_ON(0); 222 #elif defined(CFG_MX6ULL) 223 addr += i2c_clk.i2c[bid]; 224 val = i2c_clk.cgrbm[bid] | io_read32(addr); 225 #else 226 #error IMX_I2C driver not supported on this platform 227 #endif 228 io_write32(addr, val); 229 i2c_set_prescaler(bid, bps); 230 } 231 232 static TEE_Result i2c_sync_bus(uint8_t bid, bool (*match)(uint32_t), 233 uint32_t *status) 234 { 235 uint64_t tref = timeout_init_us(100000); 236 uint32_t sr = 0; 237 238 while (!timeout_elapsed(tref)) { 239 sr = i2c_io_read8(bid, I2SR); 240 if (sr & I2SR_IAL) { 241 EMSG("bus arbitration lost"); 242 i2c_io_write8(bid, I2SR, sr & ~I2SR_IAL); 243 return TEE_ERROR_COMMUNICATION; 244 } 245 if ((*match)(sr)) { 246 if (status) 247 *status = sr; 248 return TEE_SUCCESS; 249 } 250 } 251 252 return TEE_ERROR_BUSY; 253 } 254 255 static TEE_Result i2c_idle_bus(uint8_t bid) 256 { 257 uint8_t tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MSTA; 258 TEE_Result ret = TEE_SUCCESS; 259 260 i2c_io_write8(bid, I2CR, tmp); 261 ret = i2c_sync_bus(bid, &bus_is_idle, NULL); 262 i2c_io_write8(bid, I2SR, 0); 263 264 return ret; 265 } 266 267 static TEE_Result i2c_write_byte(uint8_t bid, uint8_t byte) 268 { 269 TEE_Result ret = TEE_SUCCESS; 270 uint32_t status = 0; 271 272 i2c_io_write8(bid, I2DR, byte); 273 ret = i2c_sync_bus(bid, &isr_active, &status); 274 i2c_io_write8(bid, I2SR, 0); 275 276 if (!ret && (status & I2SR_RX_NO_AK)) 277 return TEE_ERROR_BAD_STATE; 278 279 return ret; 280 } 281 282 static TEE_Result i2c_read_byte(uint8_t bid, uint8_t *p) 283 { 284 TEE_Result ret = TEE_SUCCESS; 285 286 *p = i2c_io_read8(bid, I2DR); 287 ret = i2c_sync_bus(bid, &isr_active, NULL); 288 i2c_io_write8(bid, I2SR, 0); 289 290 return ret; 291 } 292 293 static TEE_Result i2c_write_data(uint8_t bid, const uint8_t *buf, int len) 294 { 295 TEE_Result ret = TEE_SUCCESS; 296 uint32_t tmp = 0; 297 298 if (!len) 299 return TEE_SUCCESS; 300 301 tmp = i2c_io_read8(bid, I2CR) | I2CR_MTX | I2CR_TX_NO_AK; 302 i2c_io_write8(bid, I2CR, tmp); 303 304 while (len--) { 305 ret = i2c_write_byte(bid, *buf++); 306 if (ret) 307 return ret; 308 } 309 310 return ret; 311 } 312 313 static TEE_Result i2c_read_data(uint8_t bid, uint8_t *buf, int len) 314 { 315 TEE_Result ret = TEE_SUCCESS; 316 uint8_t dummy = 0; 317 uint32_t tmp = 0; 318 319 if (!len) 320 return TEE_SUCCESS; 321 322 tmp = i2c_io_read8(bid, I2CR) & ~I2CR_MTX; 323 tmp = (len == 1) ? tmp | I2CR_TX_NO_AK : tmp & ~I2CR_TX_NO_AK; 324 i2c_io_write8(bid, I2CR, tmp); 325 i2c_io_read8(bid, I2DR); 326 327 ret = i2c_read_byte(bid, &dummy); 328 if (ret) 329 return ret; 330 331 /* 332 * A data transfer ends when the master signals a stop; for a master 333 * receiver to terminate a transfer it must inform the slave transmiter 334 * by not acknowledging the last data byte. This is done by setting the 335 * transmit acknowledge bit before reading the next-to-last byte. 336 */ 337 do { 338 if (len == 2) { 339 tmp = i2c_io_read8(bid, I2CR) | I2CR_TX_NO_AK; 340 i2c_io_write8(bid, I2CR, tmp); 341 } 342 343 ret = i2c_read_byte(bid, buf++); 344 if (ret) 345 return ret; 346 } while (len--); 347 348 return ret; 349 } 350 351 static TEE_Result i2c_init_transfer(uint8_t bid, uint8_t chip) 352 { 353 TEE_Result ret = TEE_SUCCESS; 354 uint32_t tmp = 0; 355 356 ret = i2c_idle_bus(bid); 357 if (ret) 358 return ret; 359 360 /* Enable the interface */ 361 tmp = !(i2c_io_read8(bid, I2CR) & I2CR_IEN); 362 if (tmp) { 363 i2c_io_write8(bid, I2CR, I2CR_IEN); 364 udelay(50); 365 } 366 i2c_io_write8(bid, I2SR, 0); 367 368 tmp = i2c_io_read8(bid, I2CR) | I2CR_MSTA; 369 i2c_io_write8(bid, I2CR, tmp); 370 371 /* Wait until the bus is active */ 372 ret = i2c_sync_bus(bid, &bus_is_busy, NULL); 373 if (ret) 374 return ret; 375 376 /* Slave address on the bus */ 377 return i2c_write_data(bid, &chip, 1); 378 } 379 380 TEE_Result imx_i2c_read(uint8_t bid, uint8_t chip, uint8_t *buf, int len) 381 { 382 TEE_Result ret = TEE_SUCCESS; 383 384 if (bid >= ARRAY_SIZE(i2c_bus)) 385 return TEE_ERROR_BAD_PARAMETERS; 386 387 if ((len && !buf) || chip > 0x7F) 388 return TEE_ERROR_BAD_PARAMETERS; 389 390 if (!i2c_bus[bid].va) 391 return TEE_ERROR_BAD_PARAMETERS; 392 393 ret = i2c_init_transfer(bid, chip << 1 | BIT(0)); 394 if (!ret) 395 ret = i2c_read_data(bid, buf, len); 396 397 if (i2c_idle_bus(bid)) 398 IMSG("bus not idle"); 399 400 return ret; 401 } 402 403 TEE_Result imx_i2c_write(uint8_t bid, uint8_t chip, const uint8_t *buf, int len) 404 { 405 TEE_Result ret = TEE_SUCCESS; 406 407 if (bid >= ARRAY_SIZE(i2c_bus)) 408 return TEE_ERROR_BAD_PARAMETERS; 409 410 if ((len && !buf) || chip > 0x7F) 411 return TEE_ERROR_BAD_PARAMETERS; 412 413 if (!i2c_bus[bid].va) 414 return TEE_ERROR_BAD_PARAMETERS; 415 416 ret = i2c_init_transfer(bid, chip << 1); 417 if (!ret) 418 ret = i2c_write_data(bid, buf, len); 419 420 if (i2c_idle_bus(bid)) 421 IMSG("bus not idle"); 422 423 return ret; 424 } 425 426 TEE_Result imx_i2c_probe(uint8_t bid, uint8_t chip) 427 { 428 if (bid >= ARRAY_SIZE(i2c_bus)) 429 return TEE_ERROR_BAD_PARAMETERS; 430 431 if (!i2c_bus[bid].va) 432 return TEE_ERROR_BAD_PARAMETERS; 433 434 if (chip > 0x7F) 435 return TEE_ERROR_BAD_PARAMETERS; 436 437 return imx_i2c_write(bid, chip, NULL, 0); 438 } 439 440 /* 441 * I2C bus initialization: configure the IOMUX and enable the clock. 442 * @bid: Bus ID: (0=I2C1), (1=I2C2), (2=I2C3), (3=I2C4). 443 * @bps: Bus baud rate, in bits per second. 444 */ 445 TEE_Result imx_i2c_init(uint8_t bid, int bps) 446 { 447 struct imx_i2c_mux *mux = &i2c_mux; 448 449 if (bid >= ARRAY_SIZE(i2c_bus)) 450 return TEE_ERROR_BAD_PARAMETERS; 451 452 if (!bps) 453 return TEE_ERROR_BAD_PARAMETERS; 454 455 if (!i2c_bus[bid].va) 456 return TEE_ERROR_BAD_PARAMETERS; 457 458 io_write32(mux->base.va + mux->i2c[bid].scl_mux, I2C_MUX_VAL(bid)); 459 io_write32(mux->base.va + mux->i2c[bid].scl_cfg, I2C_CFG_VAL(bid)); 460 if (mux->i2c[bid].scl_inp) 461 io_write32(mux->base.va + mux->i2c[bid].scl_inp, 462 I2C_INP_VAL(bid + 1)); 463 464 io_write32(mux->base.va + mux->i2c[bid].sda_mux, I2C_MUX_VAL(bid)); 465 io_write32(mux->base.va + mux->i2c[bid].sda_cfg, I2C_CFG_VAL(bid)); 466 if (mux->i2c[bid].sda_inp) 467 io_write32(mux->base.va + mux->i2c[bid].sda_inp, 468 I2C_INP_VAL(bid + 1)); 469 470 /* Baud rate in bits per second */ 471 i2c_set_bus_speed(bid, bps); 472 473 return TEE_SUCCESS; 474 } 475 476 static TEE_Result get_va(paddr_t pa, vaddr_t *va) 477 { 478 *va = (vaddr_t)core_mmu_add_mapping(MEM_AREA_IO_SEC, pa, 0x10000); 479 if (!*va) 480 return TEE_ERROR_GENERIC; 481 482 return TEE_SUCCESS; 483 } 484 485 #if defined(CFG_DT) && !defined(CFG_EXTERNAL_DTB_OVERLAY) 486 static const char *const dt_i2c_match_table[] = { 487 "fsl,imx21-i2c", 488 }; 489 490 static TEE_Result i2c_mapped(const char *i2c_match) 491 { 492 TEE_Result ret = TEE_ERROR_GENERIC; 493 void *fdt = get_dt(); 494 size_t size = 0; 495 size_t i = 0; 496 int off = 0; 497 498 if (!fdt) 499 return TEE_ERROR_NOT_SUPPORTED; 500 501 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { 502 off = fdt_node_offset_by_compatible(fdt, off, i2c_match); 503 if (off < 0) 504 break; 505 506 if (!(_fdt_get_status(fdt, off) & DT_STATUS_OK_SEC)) { 507 EMSG("i2c%zu not enabled", i + 1); 508 continue; 509 } 510 511 if (dt_map_dev(fdt, off, &i2c_bus[i].va, &size) < 0) { 512 EMSG("i2c%zu not enabled", i + 1); 513 continue; 514 } 515 516 i2c_bus[i].pa = virt_to_phys((void *)i2c_bus[i].va); 517 ret = TEE_SUCCESS; 518 } 519 520 return ret; 521 } 522 523 static TEE_Result i2c_map_controller(void) 524 { 525 TEE_Result ret = TEE_ERROR_GENERIC; 526 size_t i = 0; 527 528 for (i = 0; i < ARRAY_SIZE(dt_i2c_match_table); i++) { 529 ret = i2c_mapped(dt_i2c_match_table[i]); 530 if (!ret || ret == TEE_ERROR_NOT_SUPPORTED) 531 return ret; 532 } 533 534 return ret; 535 } 536 #else 537 static TEE_Result i2c_map_controller(void) 538 { 539 TEE_Result ret = TEE_ERROR_GENERIC; 540 size_t n = 0; 541 542 for (n = 0; n < ARRAY_SIZE(i2c_bus); n++) { 543 if (i2c_bus[n].pa) { 544 if (get_va(i2c_bus[n].pa, &i2c_bus[n].va)) 545 EMSG("i2c%zu not enabled", n + 1); 546 else 547 ret = TEE_SUCCESS; 548 } else { 549 IMSG("i2c%zu not enabled", n + 1); 550 } 551 } 552 553 return ret; 554 } 555 #endif 556 557 static TEE_Result i2c_init(void) 558 { 559 if (get_va(i2c_clk.base.pa, &i2c_clk.base.va)) 560 return TEE_ERROR_GENERIC; 561 562 if (get_va(i2c_mux.base.pa, &i2c_mux.base.va)) 563 return TEE_ERROR_GENERIC; 564 565 return i2c_map_controller(); 566 } 567 568 early_init(i2c_init); 569