1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <assert.h> 28 #include <drivers/hi16xx_uart.h> 29 #include <io.h> 30 #include <mm/core_mmu.h> 31 #include <util.h> 32 33 /* Register offsets */ 34 35 #define UART_RBR 0x00 /* RX data buffer register */ 36 #define UART_THR 0x00 /* TX data buffer register */ 37 #define UART_DLL 0x00 /* Lower-bit frequency divider register */ 38 39 #define UART_IEL 0x04 /* Interrupt enable register */ 40 #define UART_DLH 0x04 /* Upper-bit frequency divider register */ 41 42 #define UART_FCR 0x08 /* FIFO control register */ 43 44 #define UART_LCR 0x0C /* Line control register */ 45 46 #define UART_LSR 0x14 /* Line status register */ 47 48 #define UART_USR 0x7C /* Status register */ 49 50 /* 51 * Line control register 52 */ 53 54 /* Data length selection */ 55 #define UART_LCR_DLS5 0x0 /* 5 bits */ 56 #define UART_LCR_DLS6 0x1 /* 6 bits */ 57 #define UART_LCR_DLS7 0x2 /* 7 bits */ 58 #define UART_LCR_DLS8 0x3 /* 8 bits */ 59 60 /* Enable access to UART_DLL and UART_DLH */ 61 #define UART_LCR_DLAB 0x80 62 63 /* 64 * FIFO control register 65 */ 66 67 #define UART_FCR_FIFO_EN 0x1 /* Enable FIFO (depth: 32 bytes) */ 68 #define UART_FCR_RX_FIFO_RST 0x2 /* Clear receive FIFO (auto reset) */ 69 #define UART_FCR_TX_FIFO_RST 0x4 /* Clear send FIFO (auto reset) */ 70 71 72 /* 73 * Status register 74 */ 75 76 #define UART_USR_BUSY_BIT 0 /* 0: idle/non-activated, 1: busy */ 77 #define UART_USR_TFNF_BIT 1 /* Transmit FIFO not full bit */ 78 #define UART_USR_TFE_BIT 2 /* Transmit FIFO empty bit */ 79 #define UART_USR_RFNE_BIT 3 /* Receive FIFO not empty bit */ 80 #define UART_USR_RFF_BIT 4 /* Receive FIFO full bit */ 81 82 static vaddr_t chip_to_base(struct serial_chip *chip) 83 { 84 struct hi16xx_uart_data *pd = 85 container_of(chip, struct hi16xx_uart_data, chip); 86 87 return io_pa_or_va(&pd->base); 88 } 89 90 static void hi16xx_uart_flush(struct serial_chip *chip) 91 { 92 vaddr_t base = chip_to_base(chip); 93 94 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 95 ; 96 } 97 98 static void hi16xx_uart_putc(struct serial_chip *chip, int ch) 99 { 100 vaddr_t base = chip_to_base(chip); 101 102 /* Wait until TX FIFO is empty */ 103 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 104 ; 105 106 /* Put character into TX FIFO */ 107 write32(ch & 0xFF, base + UART_THR); 108 } 109 110 static bool hi16xx_uart_have_rx_data(struct serial_chip *chip) 111 { 112 vaddr_t base = chip_to_base(chip); 113 114 return (read32(base + UART_USR) & UART_USR_RFNE_BIT); 115 } 116 117 static int hi16xx_uart_getchar(struct serial_chip *chip) 118 { 119 vaddr_t base = chip_to_base(chip); 120 121 while (!hi16xx_uart_have_rx_data(chip)) 122 ; 123 return read32(base + UART_RBR) & 0xFF; 124 } 125 126 static const struct serial_ops hi16xx_uart_ops = { 127 .flush = hi16xx_uart_flush, 128 .getchar = hi16xx_uart_getchar, 129 .have_rx_data = hi16xx_uart_have_rx_data, 130 .putc = hi16xx_uart_putc, 131 }; 132 133 void hi16xx_uart_init(struct hi16xx_uart_data *pd, paddr_t base, 134 uint32_t uart_clk, uint32_t baud_rate) 135 { 136 uint16_t freq_div = uart_clk / (16 * baud_rate); 137 138 pd->base.pa = base; 139 pd->chip.ops = &hi16xx_uart_ops; 140 141 /* Enable (and clear) FIFOs */ 142 write32(UART_FCR_FIFO_EN, base + UART_FCR); 143 144 /* Enable access to _DLL and _DLH */ 145 write32(UART_LCR_DLAB, base + UART_LCR); 146 147 /* Calculate and set UART_DLL */ 148 write32(freq_div & 0xFF, base + UART_DLL); 149 150 /* Calculate and set UART_DLH */ 151 write32((freq_div >> 8) & 0xFF, base + UART_DLH); 152 153 /* Clear _DLL/_DLH access bit, set data size (8 bits), parity etc. */ 154 write32(UART_LCR_DLS8, base + UART_LCR); 155 156 /* Disable interrupt mode */ 157 write32(0, base + UART_IEL); 158 159 hi16xx_uart_flush(&pd->chip); 160 } 161 162