1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <assert.h> 28 #include <drivers/hi16xx_uart.h> 29 #include <io.h> 30 #include <keep.h> 31 #include <mm/core_mmu.h> 32 #include <util.h> 33 34 /* Register offsets */ 35 36 #define UART_RBR 0x00 /* RX data buffer register */ 37 #define UART_THR 0x00 /* TX data buffer register */ 38 #define UART_DLL 0x00 /* Lower-bit frequency divider register */ 39 40 #define UART_IEL 0x04 /* Interrupt enable register */ 41 #define UART_DLH 0x04 /* Upper-bit frequency divider register */ 42 43 #define UART_FCR 0x08 /* FIFO control register */ 44 45 #define UART_LCR 0x0C /* Line control register */ 46 47 #define UART_LSR 0x14 /* Line status register */ 48 49 #define UART_USR 0x7C /* Status register */ 50 51 /* 52 * Line control register 53 */ 54 55 /* Data length selection */ 56 #define UART_LCR_DLS5 0x0 /* 5 bits */ 57 #define UART_LCR_DLS6 0x1 /* 6 bits */ 58 #define UART_LCR_DLS7 0x2 /* 7 bits */ 59 #define UART_LCR_DLS8 0x3 /* 8 bits */ 60 61 /* Enable access to UART_DLL and UART_DLH */ 62 #define UART_LCR_DLAB 0x80 63 64 /* 65 * FIFO control register 66 */ 67 68 #define UART_FCR_FIFO_EN 0x1 /* Enable FIFO (depth: 32 bytes) */ 69 #define UART_FCR_RX_FIFO_RST 0x2 /* Clear receive FIFO (auto reset) */ 70 #define UART_FCR_TX_FIFO_RST 0x4 /* Clear send FIFO (auto reset) */ 71 72 73 /* 74 * Status register 75 */ 76 77 #define UART_USR_BUSY_BIT 0 /* 0: idle/non-activated, 1: busy */ 78 #define UART_USR_TFNF_BIT 1 /* Transmit FIFO not full bit */ 79 #define UART_USR_TFE_BIT 2 /* Transmit FIFO empty bit */ 80 #define UART_USR_RFNE_BIT 3 /* Receive FIFO not empty bit */ 81 #define UART_USR_RFF_BIT 4 /* Receive FIFO full bit */ 82 83 static vaddr_t chip_to_base(struct serial_chip *chip) 84 { 85 struct hi16xx_uart_data *pd = 86 container_of(chip, struct hi16xx_uart_data, chip); 87 88 return io_pa_or_va(&pd->base); 89 } 90 91 static void hi16xx_uart_flush(struct serial_chip *chip) 92 { 93 vaddr_t base = chip_to_base(chip); 94 95 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 96 ; 97 } 98 99 static void hi16xx_uart_putc(struct serial_chip *chip, int ch) 100 { 101 vaddr_t base = chip_to_base(chip); 102 103 /* Wait until TX FIFO is empty */ 104 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 105 ; 106 107 /* Put character into TX FIFO */ 108 write32(ch & 0xFF, base + UART_THR); 109 } 110 111 static bool hi16xx_uart_have_rx_data(struct serial_chip *chip) 112 { 113 vaddr_t base = chip_to_base(chip); 114 115 return (read32(base + UART_USR) & UART_USR_RFNE_BIT); 116 } 117 118 static int hi16xx_uart_getchar(struct serial_chip *chip) 119 { 120 vaddr_t base = chip_to_base(chip); 121 122 while (!hi16xx_uart_have_rx_data(chip)) 123 ; 124 return read32(base + UART_RBR) & 0xFF; 125 } 126 127 static const struct serial_ops hi16xx_uart_ops = { 128 .flush = hi16xx_uart_flush, 129 .getchar = hi16xx_uart_getchar, 130 .have_rx_data = hi16xx_uart_have_rx_data, 131 .putc = hi16xx_uart_putc, 132 }; 133 KEEP_PAGER(hi16xx_uart_ops); 134 135 void hi16xx_uart_init(struct hi16xx_uart_data *pd, paddr_t base, 136 uint32_t uart_clk, uint32_t baud_rate) 137 { 138 uint16_t freq_div = uart_clk / (16 * baud_rate); 139 140 pd->base.pa = base; 141 pd->chip.ops = &hi16xx_uart_ops; 142 143 /* Enable (and clear) FIFOs */ 144 write32(UART_FCR_FIFO_EN, base + UART_FCR); 145 146 /* Enable access to _DLL and _DLH */ 147 write32(UART_LCR_DLAB, base + UART_LCR); 148 149 /* Calculate and set UART_DLL */ 150 write32(freq_div & 0xFF, base + UART_DLL); 151 152 /* Calculate and set UART_DLH */ 153 write32((freq_div >> 8) & 0xFF, base + UART_DLH); 154 155 /* Clear _DLL/_DLH access bit, set data size (8 bits), parity etc. */ 156 write32(UART_LCR_DLS8, base + UART_LCR); 157 158 /* Disable interrupt mode */ 159 write32(0, base + UART_IEL); 160 161 hi16xx_uart_flush(&pd->chip); 162 } 163 164