1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <drivers/hi16xx_uart.h> 28 #include <io.h> 29 30 #include <arm.h> 31 32 /* Register offsets */ 33 34 #define UART_RBR 0x00 /* RX data buffer register */ 35 #define UART_THR 0x00 /* TX data buffer register */ 36 #define UART_DLL 0x00 /* Lower-bit frequency divider register */ 37 38 #define UART_IEL 0x04 /* Interrupt enable register */ 39 #define UART_DLH 0x04 /* Upper-bit frequency divider register */ 40 41 #define UART_FCR 0x08 /* FIFO control register */ 42 43 #define UART_LCR 0x0C /* Line control register */ 44 45 #define UART_LSR 0x14 /* Line status register */ 46 47 #define UART_USR 0x7C /* Status register */ 48 49 /* 50 * Line control register 51 */ 52 53 /* Data length selection */ 54 #define UART_LCR_DLS5 0x0 /* 5 bits */ 55 #define UART_LCR_DLS6 0x1 /* 6 bits */ 56 #define UART_LCR_DLS7 0x2 /* 7 bits */ 57 #define UART_LCR_DLS8 0x3 /* 8 bits */ 58 59 /* Enable access to UART_DLL and UART_DLH */ 60 #define UART_LCR_DLAB 0x80 61 62 /* 63 * FIFO control register 64 */ 65 66 #define UART_FCR_FIFO_EN 0x1 /* Enable FIFO (depth: 32 bytes) */ 67 #define UART_FCR_RX_FIFO_RST 0x2 /* Clear receive FIFO (auto reset) */ 68 #define UART_FCR_TX_FIFO_RST 0x4 /* Clear send FIFO (auto reset) */ 69 70 71 /* 72 * Status register 73 */ 74 75 #define UART_USR_BUSY_BIT 0 /* 0: idle/non-activated, 1: busy */ 76 #define UART_USR_TFNF_BIT 1 /* Transmit FIFO not full bit */ 77 #define UART_USR_TFE_BIT 2 /* Transmit FIFO empty bit */ 78 #define UART_USR_RFNE_BIT 3 /* Receive FIFO not empty bit */ 79 #define UART_USR_RFF_BIT 4 /* Receive FIFO full bit */ 80 81 void hi16xx_uart_flush(vaddr_t base) 82 { 83 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 84 ; 85 } 86 87 void hi16xx_uart_init(vaddr_t base, uint32_t uart_clk, uint32_t baud_rate) 88 { 89 uint16_t freq_div = uart_clk / (16 * baud_rate); 90 91 /* Clear and enable FIFO */ 92 write32(UART_FCR_FIFO_EN | UART_FCR_RX_FIFO_RST | UART_FCR_TX_FIFO_RST, 93 base + UART_FCR); 94 dsb(); 95 96 /* Enable access to _DLL and _DLH */ 97 write32(UART_LCR_DLAB, base + UART_LCR); 98 dsb(); 99 100 /* Calculate and set UART_DLL */ 101 write32(freq_div & 0xFF, base + UART_DLL); 102 dsb(); 103 104 /* Calculate and set UART_DLH */ 105 write32((freq_div >> 8) & 0xFF, base + UART_DLH); 106 dsb(); 107 108 /* 109 * Clear _DLL and _DLH access bit, set data size (8 bits), parity etc. 110 */ 111 write32(UART_LCR_DLS8, base + UART_LCR); 112 dsb(); 113 114 /* Disable interrupt mode */ 115 write32(0, base + UART_IEL); 116 dsb(); 117 118 hi16xx_uart_flush(base); 119 } 120 121 void hi16xx_uart_putc(int ch, vaddr_t base) 122 { 123 /* 124 * FIXME: Output is garbled if we "wait for not full", it is OK if we 125 * "wait for empty" 126 */ 127 #if 0 128 /* Wait until TX FIFO is not full */ 129 while (!(read32(base + UART_USR) & UART_USR_TFNF_BIT)) 130 ; 131 #endif 132 /* Wait until TX FIFO is empty */ 133 while (!(read32(base + UART_USR) & UART_USR_TFE_BIT)) 134 ; 135 136 /* Put character into TX FIFO */ 137 write32(ch & 0xFF, base + UART_THR); 138 } 139 140 bool hi16xx_uart_have_rx_data(vaddr_t base) 141 { 142 return (read32(base + UART_USR) & UART_USR_RFNE_BIT); 143 } 144 145 int hi16xx_uart_getchar(vaddr_t base) 146 { 147 while (!hi16xx_uart_have_rx_data(base)) 148 ; 149 return read32(base + UART_RBR) & 0xFF; 150 } 151 152