1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2017, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <assert.h> 9 #include <drivers/gic.h> 10 #include <keep.h> 11 #include <kernel/interrupt.h> 12 #include <kernel/panic.h> 13 #include <util.h> 14 #include <io.h> 15 #include <trace.h> 16 17 /* Offsets from gic.gicc_base */ 18 #define GICC_CTLR (0x000) 19 #define GICC_PMR (0x004) 20 #define GICC_IAR (0x00C) 21 #define GICC_EOIR (0x010) 22 23 #define GICC_CTLR_ENABLEGRP0 (1 << 0) 24 #define GICC_CTLR_ENABLEGRP1 (1 << 1) 25 #define GICD_CTLR_ENABLEGRP1S (1 << 2) 26 #define GICC_CTLR_FIQEN (1 << 3) 27 28 /* Offsets from gic.gicd_base */ 29 #define GICD_CTLR (0x000) 30 #define GICD_TYPER (0x004) 31 #define GICD_IGROUPR(n) (0x080 + (n) * 4) 32 #define GICD_ISENABLER(n) (0x100 + (n) * 4) 33 #define GICD_ICENABLER(n) (0x180 + (n) * 4) 34 #define GICD_ISPENDR(n) (0x200 + (n) * 4) 35 #define GICD_ICPENDR(n) (0x280 + (n) * 4) 36 #define GICD_IPRIORITYR(n) (0x400 + (n) * 4) 37 #define GICD_ITARGETSR(n) (0x800 + (n) * 4) 38 #define GICD_IGROUPMODR(n) (0xd00 + (n) * 4) 39 #define GICD_SGIR (0xF00) 40 41 #define GICD_CTLR_ENABLEGRP0 (1 << 0) 42 #define GICD_CTLR_ENABLEGRP1 (1 << 1) 43 44 /* Number of Private Peripheral Interrupt */ 45 #define NUM_PPI 32 46 47 /* Number of Software Generated Interrupt */ 48 #define NUM_SGI 16 49 50 /* Number of Non-secure Software Generated Interrupt */ 51 #define NUM_NS_SGI 8 52 53 /* Number of interrupts in one register */ 54 #define NUM_INTS_PER_REG 32 55 56 /* Number of targets in one register */ 57 #define NUM_TARGETS_PER_REG 4 58 59 /* Accessors to access ITARGETSRn */ 60 #define ITARGETSR_FIELD_BITS 8 61 #define ITARGETSR_FIELD_MASK 0xff 62 63 /* Maximum number of interrups a GIC can support */ 64 #define GIC_MAX_INTS 1020 65 66 #define GICC_IAR_IT_ID_MASK 0x3ff 67 #define GICC_IAR_CPU_ID_MASK 0x7 68 #define GICC_IAR_CPU_ID_SHIFT 10 69 70 static void gic_op_add(struct itr_chip *chip, size_t it, uint32_t flags); 71 static void gic_op_enable(struct itr_chip *chip, size_t it); 72 static void gic_op_disable(struct itr_chip *chip, size_t it); 73 static void gic_op_raise_pi(struct itr_chip *chip, size_t it); 74 static void gic_op_raise_sgi(struct itr_chip *chip, size_t it, 75 uint8_t cpu_mask); 76 static void gic_op_set_affinity(struct itr_chip *chip, size_t it, 77 uint8_t cpu_mask); 78 79 static const struct itr_ops gic_ops = { 80 .add = gic_op_add, 81 .enable = gic_op_enable, 82 .disable = gic_op_disable, 83 .raise_pi = gic_op_raise_pi, 84 .raise_sgi = gic_op_raise_sgi, 85 .set_affinity = gic_op_set_affinity, 86 }; 87 DECLARE_KEEP_PAGER(gic_ops); 88 89 static size_t probe_max_it(vaddr_t gicc_base __maybe_unused, vaddr_t gicd_base) 90 { 91 int i; 92 uint32_t old_ctlr; 93 size_t ret = 0; 94 const size_t max_regs = ((GIC_MAX_INTS + NUM_INTS_PER_REG - 1) / 95 NUM_INTS_PER_REG) - 1; 96 97 /* 98 * Probe which interrupt number is the largest. 99 */ 100 #if defined(CFG_ARM_GICV3) 101 old_ctlr = read_icc_ctlr(); 102 write_icc_ctlr(0); 103 #else 104 old_ctlr = io_read32(gicc_base + GICC_CTLR); 105 io_write32(gicc_base + GICC_CTLR, 0); 106 #endif 107 for (i = max_regs; i >= 0; i--) { 108 uint32_t old_reg; 109 uint32_t reg; 110 int b; 111 112 old_reg = io_read32(gicd_base + GICD_ISENABLER(i)); 113 io_write32(gicd_base + GICD_ISENABLER(i), 0xffffffff); 114 reg = io_read32(gicd_base + GICD_ISENABLER(i)); 115 io_write32(gicd_base + GICD_ICENABLER(i), ~old_reg); 116 for (b = NUM_INTS_PER_REG - 1; b >= 0; b--) { 117 if (BIT32(b) & reg) { 118 ret = i * NUM_INTS_PER_REG + b; 119 goto out; 120 } 121 } 122 } 123 out: 124 #if defined(CFG_ARM_GICV3) 125 write_icc_ctlr(old_ctlr); 126 #else 127 io_write32(gicc_base + GICC_CTLR, old_ctlr); 128 #endif 129 return ret; 130 } 131 132 void gic_cpu_init(struct gic_data *gd) 133 { 134 #if defined(CFG_ARM_GICV3) 135 assert(gd->gicd_base); 136 #else 137 assert(gd->gicd_base && gd->gicc_base); 138 #endif 139 140 /* per-CPU interrupts config: 141 * ID0-ID7(SGI) for Non-secure interrupts 142 * ID8-ID15(SGI) for Secure interrupts. 143 * All PPI config as Non-secure interrupts. 144 */ 145 io_write32(gd->gicd_base + GICD_IGROUPR(0), 0xffff00ff); 146 147 /* Set the priority mask to permit Non-secure interrupts, and to 148 * allow the Non-secure world to adjust the priority mask itself 149 */ 150 #if defined(CFG_ARM_GICV3) 151 write_icc_pmr(0x80); 152 write_icc_igrpen1(1); 153 #else 154 io_write32(gd->gicc_base + GICC_PMR, 0x80); 155 156 /* Enable GIC */ 157 io_write32(gd->gicc_base + GICC_CTLR, 158 GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | 159 GICC_CTLR_FIQEN); 160 #endif 161 } 162 163 void gic_init(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, 164 vaddr_t gicd_base) 165 { 166 size_t n; 167 168 gic_init_base_addr(gd, gicc_base, gicd_base); 169 170 for (n = 0; n <= gd->max_it / NUM_INTS_PER_REG; n++) { 171 /* Disable interrupts */ 172 io_write32(gd->gicd_base + GICD_ICENABLER(n), 0xffffffff); 173 174 /* Make interrupts non-pending */ 175 io_write32(gd->gicd_base + GICD_ICPENDR(n), 0xffffffff); 176 177 /* Mark interrupts non-secure */ 178 if (n == 0) { 179 /* per-CPU inerrupts config: 180 * ID0-ID7(SGI) for Non-secure interrupts 181 * ID8-ID15(SGI) for Secure interrupts. 182 * All PPI config as Non-secure interrupts. 183 */ 184 io_write32(gd->gicd_base + GICD_IGROUPR(n), 0xffff00ff); 185 } else { 186 io_write32(gd->gicd_base + GICD_IGROUPR(n), 0xffffffff); 187 } 188 } 189 190 /* Set the priority mask to permit Non-secure interrupts, and to 191 * allow the Non-secure world to adjust the priority mask itself 192 */ 193 #if defined(CFG_ARM_GICV3) 194 write_icc_pmr(0x80); 195 write_icc_igrpen1(1); 196 io_setbits32(gd->gicd_base + GICD_CTLR, GICD_CTLR_ENABLEGRP1S); 197 #else 198 io_write32(gd->gicc_base + GICC_PMR, 0x80); 199 200 /* Enable GIC */ 201 io_write32(gd->gicc_base + GICC_CTLR, GICC_CTLR_FIQEN | 202 GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1); 203 io_setbits32(gd->gicd_base + GICD_CTLR, 204 GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1); 205 #endif 206 } 207 208 void gic_init_base_addr(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, 209 vaddr_t gicd_base) 210 { 211 gd->gicc_base = gicc_base; 212 gd->gicd_base = gicd_base; 213 gd->max_it = probe_max_it(gicc_base, gicd_base); 214 gd->chip.ops = &gic_ops; 215 } 216 217 static void gic_it_add(struct gic_data *gd, size_t it) 218 { 219 size_t idx = it / NUM_INTS_PER_REG; 220 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 221 222 /* Disable the interrupt */ 223 io_write32(gd->gicd_base + GICD_ICENABLER(idx), mask); 224 /* Make it non-pending */ 225 io_write32(gd->gicd_base + GICD_ICPENDR(idx), mask); 226 /* Assign it to group0 */ 227 io_clrbits32(gd->gicd_base + GICD_IGROUPR(idx), mask); 228 #if defined(CFG_ARM_GICV3) 229 /* Assign it to group1S */ 230 io_setbits32(gd->gicd_base + GICD_IGROUPMODR(idx), mask); 231 #endif 232 } 233 234 static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it, 235 uint8_t cpu_mask) 236 { 237 size_t idx __maybe_unused = it / NUM_INTS_PER_REG; 238 uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG); 239 uint32_t target, target_shift; 240 vaddr_t itargetsr = gd->gicd_base + 241 GICD_ITARGETSR(it / NUM_TARGETS_PER_REG); 242 243 /* Assigned to group0 */ 244 assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 245 246 /* Route it to selected CPUs */ 247 target = io_read32(itargetsr); 248 target_shift = (it % NUM_TARGETS_PER_REG) * ITARGETSR_FIELD_BITS; 249 target &= ~(ITARGETSR_FIELD_MASK << target_shift); 250 target |= cpu_mask << target_shift; 251 DMSG("cpu_mask: writing 0x%x to 0x%" PRIxVA, target, itargetsr); 252 io_write32(itargetsr, target); 253 DMSG("cpu_mask: 0x%x", io_read32(itargetsr)); 254 } 255 256 static void gic_it_set_prio(struct gic_data *gd, size_t it, uint8_t prio) 257 { 258 size_t idx __maybe_unused = it / NUM_INTS_PER_REG; 259 uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG); 260 261 /* Assigned to group0 */ 262 assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 263 264 /* Set prio it to selected CPUs */ 265 DMSG("prio: writing 0x%x to 0x%" PRIxVA, 266 prio, gd->gicd_base + GICD_IPRIORITYR(0) + it); 267 io_write8(gd->gicd_base + GICD_IPRIORITYR(0) + it, prio); 268 } 269 270 static void gic_it_enable(struct gic_data *gd, size_t it) 271 { 272 size_t idx = it / NUM_INTS_PER_REG; 273 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 274 vaddr_t base = gd->gicd_base; 275 276 /* Assigned to group0 */ 277 assert(!(io_read32(base + GICD_IGROUPR(idx)) & mask)); 278 if (it >= NUM_SGI) { 279 /* 280 * Not enabled yet, except Software Generated Interrupt 281 * which is implementation defined 282 */ 283 assert(!(io_read32(base + GICD_ISENABLER(idx)) & mask)); 284 } 285 286 /* Enable the interrupt */ 287 io_write32(base + GICD_ISENABLER(idx), mask); 288 } 289 290 static void gic_it_disable(struct gic_data *gd, size_t it) 291 { 292 size_t idx = it / NUM_INTS_PER_REG; 293 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 294 295 /* Assigned to group0 */ 296 assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 297 298 /* Disable the interrupt */ 299 io_write32(gd->gicd_base + GICD_ICENABLER(idx), mask); 300 } 301 302 static void gic_it_set_pending(struct gic_data *gd, size_t it) 303 { 304 size_t idx = it / NUM_INTS_PER_REG; 305 uint32_t mask = BIT32(it % NUM_INTS_PER_REG); 306 307 /* Should be Peripheral Interrupt */ 308 assert(it >= NUM_SGI); 309 310 /* Raise the interrupt */ 311 io_write32(gd->gicd_base + GICD_ISPENDR(idx), mask); 312 } 313 314 static void gic_it_raise_sgi(struct gic_data *gd, size_t it, 315 uint8_t cpu_mask, uint8_t group) 316 { 317 uint32_t mask_id = it & 0xf; 318 uint32_t mask_group = group & 0x1; 319 uint32_t mask_cpu = cpu_mask & 0xff; 320 uint32_t mask = (mask_id | SHIFT_U32(mask_group, 15) | 321 SHIFT_U32(mask_cpu, 16)); 322 323 /* Should be Software Generated Interrupt */ 324 assert(it < NUM_SGI); 325 326 /* Raise the interrupt */ 327 io_write32(gd->gicd_base + GICD_SGIR, mask); 328 } 329 330 static uint32_t gic_read_iar(struct gic_data *gd __maybe_unused) 331 { 332 #if defined(CFG_ARM_GICV3) 333 return read_icc_iar1(); 334 #else 335 return io_read32(gd->gicc_base + GICC_IAR); 336 #endif 337 } 338 339 static void gic_write_eoir(struct gic_data *gd __maybe_unused, uint32_t eoir) 340 { 341 #if defined(CFG_ARM_GICV3) 342 write_icc_eoir1(eoir); 343 #else 344 io_write32(gd->gicc_base + GICC_EOIR, eoir); 345 #endif 346 } 347 348 static bool gic_it_is_enabled(struct gic_data *gd, size_t it) 349 { 350 size_t idx = it / NUM_INTS_PER_REG; 351 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 352 return !!(io_read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask); 353 } 354 355 static bool __maybe_unused gic_it_get_group(struct gic_data *gd, size_t it) 356 { 357 size_t idx = it / NUM_INTS_PER_REG; 358 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 359 return !!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask); 360 } 361 362 static uint32_t __maybe_unused gic_it_get_target(struct gic_data *gd, size_t it) 363 { 364 size_t reg_idx = it / NUM_TARGETS_PER_REG; 365 uint32_t target_shift = (it % NUM_TARGETS_PER_REG) * 366 ITARGETSR_FIELD_BITS; 367 uint32_t target_mask = ITARGETSR_FIELD_MASK << target_shift; 368 uint32_t target = io_read32(gd->gicd_base + GICD_ITARGETSR(reg_idx)); 369 370 return (target & target_mask) >> target_shift; 371 } 372 373 void gic_dump_state(struct gic_data *gd) 374 { 375 int i; 376 377 #if defined(CFG_ARM_GICV3) 378 DMSG("GICC_CTLR: 0x%x", read_icc_ctlr()); 379 #else 380 DMSG("GICC_CTLR: 0x%x", io_read32(gd->gicc_base + GICC_CTLR)); 381 #endif 382 DMSG("GICD_CTLR: 0x%x", io_read32(gd->gicd_base + GICD_CTLR)); 383 384 for (i = 0; i < (int)gd->max_it; i++) { 385 if (gic_it_is_enabled(gd, i)) { 386 DMSG("irq%d: enabled, group:%d, target:%x", i, 387 gic_it_get_group(gd, i), gic_it_get_target(gd, i)); 388 } 389 } 390 } 391 392 void gic_it_handle(struct gic_data *gd) 393 { 394 uint32_t iar; 395 uint32_t id; 396 397 iar = gic_read_iar(gd); 398 id = iar & GICC_IAR_IT_ID_MASK; 399 400 if (id < gd->max_it) 401 itr_handle(id); 402 else 403 DMSG("ignoring interrupt %" PRIu32, id); 404 405 gic_write_eoir(gd, iar); 406 } 407 408 static void gic_op_add(struct itr_chip *chip, size_t it, 409 uint32_t flags __unused) 410 { 411 struct gic_data *gd = container_of(chip, struct gic_data, chip); 412 413 if (it >= gd->max_it) 414 panic(); 415 416 gic_it_add(gd, it); 417 /* Set the CPU mask to deliver interrupts to any online core */ 418 gic_it_set_cpu_mask(gd, it, 0xff); 419 gic_it_set_prio(gd, it, 0x1); 420 } 421 422 static void gic_op_enable(struct itr_chip *chip, size_t it) 423 { 424 struct gic_data *gd = container_of(chip, struct gic_data, chip); 425 426 if (it >= gd->max_it) 427 panic(); 428 429 gic_it_enable(gd, it); 430 } 431 432 static void gic_op_disable(struct itr_chip *chip, size_t it) 433 { 434 struct gic_data *gd = container_of(chip, struct gic_data, chip); 435 436 if (it >= gd->max_it) 437 panic(); 438 439 gic_it_disable(gd, it); 440 } 441 442 static void gic_op_raise_pi(struct itr_chip *chip, size_t it) 443 { 444 struct gic_data *gd = container_of(chip, struct gic_data, chip); 445 446 if (it >= gd->max_it) 447 panic(); 448 449 gic_it_set_pending(gd, it); 450 } 451 452 static void gic_op_raise_sgi(struct itr_chip *chip, size_t it, 453 uint8_t cpu_mask) 454 { 455 struct gic_data *gd = container_of(chip, struct gic_data, chip); 456 457 if (it >= gd->max_it) 458 panic(); 459 460 if (it < NUM_NS_SGI) 461 gic_it_raise_sgi(gd, it, cpu_mask, 1); 462 else 463 gic_it_raise_sgi(gd, it, cpu_mask, 0); 464 } 465 static void gic_op_set_affinity(struct itr_chip *chip, size_t it, 466 uint8_t cpu_mask) 467 { 468 struct gic_data *gd = container_of(chip, struct gic_data, chip); 469 470 if (it >= gd->max_it) 471 panic(); 472 473 gic_it_set_cpu_mask(gd, it, cpu_mask); 474 } 475