1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <drivers/clk.h> 8 #include <drivers/clk_dt.h> 9 #include <drivers/stm32_rif.h> 10 #include <drivers/stm32_risaf.h> 11 #include <dt-bindings/firewall/stm32mp25-risaf.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/dt.h> 15 #include <kernel/pm.h> 16 #include <kernel/tee_misc.h> 17 #include <libfdt.h> 18 #include <mm/core_memprot.h> 19 #include <platform_config.h> 20 #include <stdint.h> 21 #include <util.h> 22 23 /* RISAF general registers (base relative) */ 24 #define _RISAF_CR U(0x00) 25 #define _RISAF_SR U(0x04) 26 #define _RISAF_IASR U(0x08) 27 #define _RISAF_IACR U(0xC) 28 #define _RISAF_IAESR0 U(0x20) 29 #define _RISAF_IADDR0 U(0x24) 30 #define _RISAF_IAESR1 U(0x28) 31 #define _RISAF_IADDR1 U(0x2C) 32 #define _RISAF_KEYR U(0x30) 33 #define _RISAF_HWCFGR U(0xFF0) 34 #define _RISAF_VERR U(0xFF4) 35 #define _RISAF_IPIDR U(0xFF8) 36 #define _RISAF_SIDR U(0xFFC) 37 38 /* RISAF general register field description */ 39 /* _RISAF_CR register fields */ 40 #define _RISAF_CR_GLOCK BIT(0) 41 /* _RISAF_SR register fields */ 42 #define _RISAF_SR_KEYVALID BIT(0) 43 #define _RISAF_SR_KEYRDY BIT(1) 44 #define _RISAF_SR_ENCDIS BIT(2) 45 /* _RISAF_IACR register fields */ 46 #define _RISAF_IACR_CAEF BIT(0) 47 #define _RISAF_IACR_IAEF0 BIT(1) 48 #define _RISAF_IACR_IAEF1 BIT(2) 49 /* _RISAF_HWCFGR register fields */ 50 #define _RISAF_HWCFGR_CFG1_SHIFT U(0) 51 #define _RISAF_HWCFGR_CFG1_MASK GENMASK_32(7, 0) 52 #define _RISAF_HWCFGR_CFG2_SHIFT U(8) 53 #define _RISAF_HWCFGR_CFG2_MASK GENMASK_32(15, 8) 54 #define _RISAF_HWCFGR_CFG3_SHIFT U(16) 55 #define _RISAF_HWCFGR_CFG3_MASK GENMASK_32(23, 16) 56 #define _RISAF_HWCFGR_CFG4_SHIFT U(24) 57 #define _RISAF_HWCFGR_CFG4_MASK GENMASK_32(31, 24) 58 /* _RISAF_VERR register fields */ 59 #define _RISAF_VERR_MINREV_SHIFT U(0) 60 #define _RISAF_VERR_MINREV_MASK GENMASK_32(3, 0) 61 #define _RISAF_VERR_MAJREV_SHIFT U(4) 62 #define _RISAF_VERR_MAJREV_MASK GENMASK_32(7, 4) 63 64 /* RISAF region registers (base relative) */ 65 #define _RISAF_REG_BASE U(0x40) 66 #define _RISAF_REG_SIZE U(0x40) 67 #define _RISAF_REG(n) (_RISAF_REG_BASE + \ 68 (((n) - 1) * _RISAF_REG_SIZE)) 69 #define _RISAF_REG_CFGR_OFFSET U(0x0) 70 #define _RISAF_REG_CFGR(n) (_RISAF_REG(n) + _RISAF_REG_CFGR_OFFSET) 71 #define _RISAF_REG_STARTR_OFFSET U(0x4) 72 #define _RISAF_REG_STARTR(n) (_RISAF_REG(n) + \ 73 _RISAF_REG_STARTR_OFFSET) 74 #define _RISAF_REG_ENDR_OFFSET U(0x8) 75 #define _RISAF_REG_ENDR(n) (_RISAF_REG(n) + _RISAF_REG_ENDR_OFFSET) 76 #define _RISAF_REG_CIDCFGR_OFFSET U(0xC) 77 #define _RISAF_REG_CIDCFGR(n) (_RISAF_REG(n) + \ 78 _RISAF_REG_CIDCFGR_OFFSET) 79 80 /* RISAF region register field description */ 81 /* _RISAF_REG_CFGR(n) register fields */ 82 #define _RISAF_REG_CFGR_BREN_SHIFT U(0) 83 #define _RISAF_REG_CFGR_BREN BIT(_RISAF_REG_CFGR_BREN_SHIFT) 84 #define _RISAF_REG_CFGR_SEC_SHIFT U(8) 85 #define _RISAF_REG_CFGR_SEC BIT(_RISAF_REG_CFGR_SEC_SHIFT) 86 #define _RISAF_REG_CFGR_ENC_SHIFT U(15) 87 #define _RISAF_REG_CFGR_ENC BIT(_RISAF_REG_CFGR_ENC_SHIFT) 88 #define _RISAF_REG_CFGR_PRIVC_SHIFT U(16) 89 #define _RISAF_REG_CFGR_PRIVC_MASK GENMASK_32(23, 16) 90 #define _RISAF_REG_CFGR_ALL_MASK (_RISAF_REG_CFGR_BREN | \ 91 _RISAF_REG_CFGR_SEC | \ 92 _RISAF_REG_CFGR_ENC | \ 93 _RISAF_REG_CFGR_PRIVC_MASK) 94 95 /* _RISAF_REG_CIDCFGR(n) register fields */ 96 #define _RISAF_REG_CIDCFGR_RDENC_SHIFT U(0) 97 #define _RISAF_REG_CIDCFGR_RDENC_MASK GENMASK_32(7, 0) 98 #define _RISAF_REG_CIDCFGR_WRENC_SHIFT U(16) 99 #define _RISAF_REG_CIDCFGR_WRENC_MASK GENMASK_32(23, 16) 100 #define _RISAF_REG_CIDCFGR_ALL_MASK (_RISAF_REG_CIDCFGR_RDENC_MASK | \ 101 _RISAF_REG_CIDCFGR_WRENC_MASK) 102 #define _RISAF_REG_READ_OK(reg, cid) \ 103 ((reg) & BIT((cid) + _RISAF_REG_CIDCFGR_RDENC_SHIFT)) 104 #define _RISAF_REG_WRITE_OK(reg, cid) \ 105 ((reg) & BIT((cid) + _RISAF_REG_CIDCFGR_WRENC_SHIFT)) 106 107 #define _RISAF_GET_REGION_ID(cfg) ((cfg) & DT_RISAF_REG_ID_MASK) 108 109 #define _RISAF_NB_CID_SUPPORTED U(8) 110 111 /** 112 * struct stm32_risaf_region - RISAF memory region 113 * 114 * @addr: Region base address. 115 * @len: Length of the memory region. 116 * @cfg: Region configuration. 117 */ 118 struct stm32_risaf_region { 119 paddr_t addr; 120 size_t len; 121 uint32_t cfg; 122 }; 123 124 /** 125 * struct stm32_risaf_pdata - RISAF platform data 126 * 127 * @base: Base address of the RISAF instance. 128 * @clock: Clock of the RISAF. 129 * @regions: Number of memory regions, defined by the device tree configuration. 130 * @risaf_name: Name of the RISAF instance 131 * @nregions: Number of memory regions found in the device tree. 132 * @conf_lock: State whether the RISAF configuration is locked. 133 * @mem_base: Base address of the memory range covered by the RISAF instance. 134 * @mem_size: Size of the memory range covered by the RISAF instance. 135 * @enc_supported: If true, the RISAF instance supports encryption of the memory 136 * regions. 137 */ 138 struct stm32_risaf_pdata { 139 struct io_pa_va base; 140 struct clk *clock; 141 struct stm32_risaf_region *regions; 142 char risaf_name[20]; 143 unsigned int nregions; 144 unsigned int conf_lock; 145 paddr_t mem_base; 146 size_t mem_size; 147 bool enc_supported; 148 }; 149 150 /** 151 * struct stm32_risaf_ddata - RISAF driver data 152 * 153 * @mask_regions: Number of address bits to match when determining access to a 154 * base region or subregion (WIDTH). 155 * @max_base_regions: Number of subdivision of the memory range (A.K.A memory 156 * regions) supported by the RISAF instance. 157 * @granularity: Length of the smallest possible region size. 158 */ 159 struct stm32_risaf_ddata { 160 uint32_t mask_regions; 161 uint32_t max_base_regions; 162 uint32_t granularity; 163 }; 164 165 struct stm32_risaf_instance { 166 struct stm32_risaf_pdata pdata; 167 struct stm32_risaf_ddata *ddata; 168 169 SLIST_ENTRY(stm32_risaf_instance) link; 170 }; 171 172 struct stm32_risaf_version { 173 uint32_t major; 174 uint32_t minor; 175 uint32_t ip_id; 176 uint32_t size_id; 177 }; 178 179 /** 180 * struct stm32_risaf_compat_data - Describes RISAF associated data 181 * for compatible list. 182 * 183 * @supported_encryption: identify RISAF encryption capabilities. 184 */ 185 struct stm32_risaf_compat_data { 186 bool supported_encryption; 187 }; 188 189 static bool is_tdcid; 190 191 static const struct stm32_risaf_compat_data stm32_risaf_compat = { 192 .supported_encryption = false, 193 }; 194 195 static const struct stm32_risaf_compat_data stm32_risaf_enc_compat = { 196 .supported_encryption = true, 197 }; 198 199 static SLIST_HEAD(, stm32_risaf_instance) risaf_list = 200 SLIST_HEAD_INITIALIZER(risaf_list); 201 202 static vaddr_t risaf_base(struct stm32_risaf_instance *risaf) 203 { 204 return io_pa_or_va_secure(&risaf->pdata.base, 1); 205 } 206 207 static uint32_t stm32_risaf_get_region_config(uint32_t cfg) 208 { 209 return SHIFT_U32((cfg & DT_RISAF_EN_MASK) >> DT_RISAF_EN_SHIFT, 210 _RISAF_REG_CFGR_BREN_SHIFT) | 211 SHIFT_U32((cfg & DT_RISAF_SEC_MASK) >> DT_RISAF_SEC_SHIFT, 212 _RISAF_REG_CFGR_SEC_SHIFT) | 213 SHIFT_U32((cfg & DT_RISAF_ENC_MASK) >> (DT_RISAF_ENC_SHIFT + 1), 214 _RISAF_REG_CFGR_ENC_SHIFT) | 215 SHIFT_U32((cfg & DT_RISAF_PRIV_MASK) >> DT_RISAF_PRIV_SHIFT, 216 _RISAF_REG_CFGR_PRIVC_SHIFT); 217 } 218 219 static uint32_t stm32_risaf_get_region_cid_config(uint32_t cfg) 220 { 221 return SHIFT_U32((cfg & DT_RISAF_WRITE_MASK) >> DT_RISAF_WRITE_SHIFT, 222 _RISAF_REG_CIDCFGR_WRENC_SHIFT) | 223 SHIFT_U32((cfg & DT_RISAF_READ_MASK) >> DT_RISAF_READ_SHIFT, 224 _RISAF_REG_CIDCFGR_RDENC_SHIFT); 225 } 226 227 void stm32_risaf_clear_illegal_access_flags(void) 228 { 229 struct stm32_risaf_instance *risaf = NULL; 230 231 SLIST_FOREACH(risaf, &risaf_list, link) { 232 vaddr_t base = io_pa_or_va_secure(&risaf->pdata.base, 1); 233 234 if (!io_read32(base + _RISAF_IASR)) 235 continue; 236 237 io_write32(base + _RISAF_IACR, _RISAF_IACR_CAEF | 238 _RISAF_IACR_IAEF0 | _RISAF_IACR_IAEF1); 239 } 240 } 241 242 void stm32_risaf_print_erroneous_data(void) 243 { 244 struct stm32_risaf_instance *risaf = NULL; 245 246 if (!IS_ENABLED(CFG_TEE_CORE_DEBUG)) 247 return; 248 249 SLIST_FOREACH(risaf, &risaf_list, link) { 250 vaddr_t base = io_pa_or_va_secure(&risaf->pdata.base, 1); 251 252 /* Check if faulty address on this RISAF */ 253 if (!io_read32(base + _RISAF_IASR)) 254 continue; 255 256 IMSG("\n\nDUMPING DATA FOR %s\n\n", risaf->pdata.risaf_name); 257 IMSG("====================================================="); 258 IMSG("Status register (IAESR0): %#"PRIx32, 259 io_read32(base + _RISAF_IAESR0)); 260 261 /* Reserved if dual port feature not available */ 262 if (io_read32(base + _RISAF_IAESR1)) 263 IMSG("Status register Dual Port (IAESR1) %#"PRIx32, 264 io_read32(base + _RISAF_IAESR1)); 265 266 IMSG("-----------------------------------------------------"); 267 if (virt_to_phys((void *)base) == RISAF4_BASE) { 268 IMSG("Faulty address (IADDR0): %#"PRIxPA, 269 risaf->pdata.mem_base + 270 io_read32(base + _RISAF_IADDR0)); 271 272 /* Reserved if dual port feature not available */ 273 if (io_read32(base + _RISAF_IADDR1)) 274 IMSG("Dual port faulty address (IADDR1): %#"PRIxPA, 275 risaf->pdata.mem_base + 276 io_read32(base + _RISAF_IADDR1)); 277 } else { 278 IMSG("Faulty address (IADDR0): %#"PRIx32, 279 io_read32(base + _RISAF_IADDR0)); 280 281 /* Reserved if dual port feature not available */ 282 if (io_read32(base + _RISAF_IADDR1)) 283 IMSG("Dual port faulty address (IADDR1): %#"PRIx32, 284 io_read32(base + _RISAF_IADDR1)); 285 } 286 287 IMSG("=====================================================\n"); 288 }; 289 } 290 291 static __maybe_unused 292 bool risaf_is_hw_encryption_enabled(struct stm32_risaf_instance *risaf) 293 { 294 return (io_read32(risaf_base(risaf) + _RISAF_SR) & 295 _RISAF_SR_ENCDIS) != _RISAF_SR_ENCDIS; 296 } 297 298 static TEE_Result 299 risaf_check_region_boundaries(struct stm32_risaf_instance *risaf, 300 struct stm32_risaf_region *region) 301 { 302 if (!core_is_buffer_inside(region->addr, region->len, 303 risaf->pdata.mem_base, 304 risaf->pdata.mem_size)) { 305 EMSG("Region %#"PRIxPA"..%#"PRIxPA" outside RISAF area %#"PRIxPA"...%#"PRIxPA, 306 region->addr, region->addr + region->len - 1, 307 risaf->pdata.mem_base, 308 risaf->pdata.mem_base + risaf->pdata.mem_size - 1); 309 return TEE_ERROR_BAD_PARAMETERS; 310 } 311 312 if (!risaf->ddata->granularity || 313 (region->addr % risaf->ddata->granularity) || 314 (region->len % risaf->ddata->granularity)) { 315 EMSG("RISAF %#"PRIxPA": start/end address granularity not respected", 316 risaf->pdata.base.pa); 317 return TEE_ERROR_BAD_PARAMETERS; 318 } 319 320 return TEE_SUCCESS; 321 } 322 323 static TEE_Result 324 risaf_check_overlap(struct stm32_risaf_instance *risaf __maybe_unused, 325 struct stm32_risaf_region *region, unsigned int index) 326 { 327 unsigned int i = 0; 328 329 for (i = 0; i < index; i++) { 330 /* Skip region if there's no configuration */ 331 if (!region[i].cfg) 332 continue; 333 334 if (core_is_buffer_intersect(region[index].addr, 335 region[index].len, 336 region[i].addr, 337 region[i].len)) { 338 EMSG("RISAF %#"PRIxPA": Regions %u and %u overlap", 339 risaf->pdata.base.pa, index, i); 340 return TEE_ERROR_GENERIC; 341 } 342 } 343 344 return TEE_SUCCESS; 345 } 346 347 static TEE_Result risaf_configure_region(struct stm32_risaf_instance *risaf, 348 uint32_t region_id, uint32_t cfg, 349 uint32_t cid_cfg, paddr_t saddr, 350 paddr_t eaddr) 351 { 352 uint32_t mask = risaf->ddata->mask_regions; 353 vaddr_t base = risaf_base(risaf); 354 355 if (cfg & _RISAF_REG_CFGR_ENC) { 356 if (!risaf->pdata.enc_supported) { 357 EMSG("RISAF %#"PRIxPA": encryption feature error", 358 risaf->pdata.base.pa); 359 return TEE_ERROR_GENERIC; 360 } 361 362 if ((cfg & _RISAF_REG_CFGR_SEC) != _RISAF_REG_CFGR_SEC) { 363 EMSG("RISAF %#"PRIxPA": encryption on non-secure area", 364 risaf->pdata.base.pa); 365 return TEE_ERROR_GENERIC; 366 } 367 } 368 369 io_clrbits32(base + _RISAF_REG_CFGR(region_id), _RISAF_REG_CFGR_BREN); 370 371 io_clrsetbits32(base + _RISAF_REG_STARTR(region_id), mask, 372 (saddr - risaf->pdata.mem_base) & mask); 373 io_clrsetbits32(base + _RISAF_REG_ENDR(region_id), mask, 374 (eaddr - risaf->pdata.mem_base) & mask); 375 io_clrsetbits32(base + _RISAF_REG_CIDCFGR(region_id), 376 _RISAF_REG_CIDCFGR_ALL_MASK, 377 cid_cfg & _RISAF_REG_CIDCFGR_ALL_MASK); 378 379 io_clrsetbits32(base + _RISAF_REG_CFGR(region_id), 380 _RISAF_REG_CFGR_ALL_MASK, 381 cfg & _RISAF_REG_CFGR_ALL_MASK); 382 383 DMSG("RISAF %#"PRIxPA": region %02"PRIu32" - start %#"PRIxPA 384 "- end %#"PRIxPA" - cfg %#08"PRIx32" - cidcfg %#08"PRIx32, 385 risaf->pdata.base.pa, region_id, 386 risaf->pdata.mem_base + 387 io_read32(base + _RISAF_REG_STARTR(region_id)), 388 risaf->pdata.mem_base + 389 io_read32(base + _RISAF_REG_ENDR(region_id)), 390 io_read32(base + _RISAF_REG_CFGR(region_id)), 391 io_read32(base + _RISAF_REG_CIDCFGR(region_id))); 392 393 return TEE_SUCCESS; 394 } 395 396 static void risaf_print_version(struct stm32_risaf_instance *risaf) 397 { 398 vaddr_t base = risaf_base(risaf); 399 struct stm32_risaf_version __maybe_unused version = { 400 .major = (io_read32(base + _RISAF_VERR) & 401 _RISAF_VERR_MAJREV_MASK) >> _RISAF_VERR_MAJREV_SHIFT, 402 .minor = (io_read32(base + _RISAF_VERR) & 403 _RISAF_VERR_MINREV_MASK) >> _RISAF_VERR_MINREV_SHIFT, 404 .ip_id = io_read32(base + _RISAF_IPIDR), 405 .size_id = io_read32(base + _RISAF_SIDR) 406 }; 407 408 DMSG("RISAF %#"PRIxPA" version %"PRIu32".%"PRIu32", ip%#"PRIx32" size%#"PRIx32, 409 risaf->pdata.base.pa, version.major, version.minor, version.ip_id, 410 version.size_id); 411 } 412 413 static __maybe_unused 414 void stm32_risaf_lock(struct stm32_risaf_instance *risaf) 415 { 416 assert(risaf); 417 418 io_setbits32(risaf_base(risaf) + _RISAF_CR, _RISAF_CR_GLOCK); 419 } 420 421 static __maybe_unused 422 void stm32_risaf_is_locked(struct stm32_risaf_instance *risaf, bool *state) 423 { 424 assert(risaf); 425 426 *state = (io_read32(risaf_base(risaf) + _RISAF_CR) & 427 _RISAF_CR_GLOCK) == _RISAF_CR_GLOCK; 428 } 429 430 static TEE_Result stm32_risaf_init_ddata(struct stm32_risaf_instance *risaf) 431 { 432 vaddr_t base = risaf_base(risaf); 433 uint32_t granularity = 0; 434 uint32_t mask_lsb = 0; 435 uint32_t mask_msb = 0; 436 uint32_t hwcfgr = 0; 437 438 risaf->ddata = calloc(1, sizeof(*risaf->ddata)); 439 if (!risaf->ddata) 440 return TEE_ERROR_OUT_OF_MEMORY; 441 442 /* Get address mask depending on RISAF instance HW configuration */ 443 hwcfgr = io_read32(base + _RISAF_HWCFGR); 444 mask_lsb = (hwcfgr & _RISAF_HWCFGR_CFG3_MASK) >> 445 _RISAF_HWCFGR_CFG3_SHIFT; 446 mask_msb = mask_lsb + ((hwcfgr & _RISAF_HWCFGR_CFG4_MASK) >> 447 _RISAF_HWCFGR_CFG4_SHIFT) - 1U; 448 risaf->ddata->mask_regions = GENMASK_32(mask_msb, mask_lsb); 449 risaf->ddata->max_base_regions = (hwcfgr & _RISAF_HWCFGR_CFG1_MASK) >> 450 _RISAF_HWCFGR_CFG1_SHIFT; 451 452 /* Get IP region granularity */ 453 granularity = io_read32(risaf_base(risaf) + _RISAF_HWCFGR); 454 granularity = BIT((granularity & _RISAF_HWCFGR_CFG3_MASK) >> 455 _RISAF_HWCFGR_CFG3_SHIFT); 456 risaf->ddata->granularity = granularity; 457 458 return TEE_SUCCESS; 459 } 460 461 static TEE_Result stm32_risaf_pm_resume(struct stm32_risaf_instance *risaf) 462 { 463 struct stm32_risaf_region *regions = risaf->pdata.regions; 464 size_t i = 0; 465 466 for (i = 0; i < risaf->pdata.nregions; i++) { 467 uint32_t id = _RISAF_GET_REGION_ID(regions[i].cfg); 468 paddr_t start_addr = 0; 469 paddr_t end_addr = 0; 470 uint32_t cid_cfg = 0; 471 uint32_t cfg = 0; 472 473 if (!id) 474 continue; 475 476 cfg = stm32_risaf_get_region_config(regions[i].cfg); 477 cid_cfg = stm32_risaf_get_region_cid_config(regions[i].cfg); 478 start_addr = regions[i].addr; 479 end_addr = start_addr + regions[i].len - 1U; 480 if (risaf_configure_region(risaf, id, cfg, cid_cfg, 481 start_addr, end_addr)) 482 panic(); 483 } 484 485 return TEE_SUCCESS; 486 } 487 488 static TEE_Result stm32_risaf_pm_suspend(struct stm32_risaf_instance *risaf) 489 { 490 vaddr_t base = io_pa_or_va_secure(&risaf->pdata.base, 1); 491 size_t i = 0; 492 493 for (i = 0; i < risaf->pdata.nregions; i++) { 494 uint32_t id = _RISAF_GET_REGION_ID(risaf->pdata.regions[i].cfg); 495 struct stm32_risaf_region *region = risaf->pdata.regions + i; 496 paddr_t start_addr = 0; 497 paddr_t end_addr = 0; 498 uint32_t cid_cfg = 0; 499 uint32_t priv = 0; 500 uint32_t rden = 0; 501 uint32_t wren = 0; 502 uint32_t cfg = 0; 503 uint32_t enc = 0; 504 uint32_t sec = 0; 505 uint32_t en = 0; 506 507 /* Skip region not defined in DT, not configured in probe */ 508 if (!id) 509 continue; 510 511 cfg = io_read32(base + _RISAF_REG_CFGR(id)); 512 en = cfg & _RISAF_REG_CFGR_BREN; 513 sec = (cfg & _RISAF_REG_CFGR_SEC) >> _RISAF_REG_CFGR_SEC_SHIFT; 514 enc = (cfg & _RISAF_REG_CFGR_ENC) >> _RISAF_REG_CFGR_ENC_SHIFT; 515 priv = (cfg & _RISAF_REG_CFGR_PRIVC_MASK) >> 516 _RISAF_REG_CFGR_PRIVC_SHIFT; 517 518 cid_cfg = io_read32(base + _RISAF_REG_CIDCFGR(id)); 519 rden = cid_cfg & _RISAF_REG_CIDCFGR_RDENC_MASK; 520 wren = (cid_cfg & _RISAF_REG_CIDCFGR_WRENC_MASK) >> 521 _RISAF_REG_CIDCFGR_WRENC_SHIFT; 522 523 region->cfg = id | SHIFT_U32(en, DT_RISAF_EN_SHIFT) | 524 SHIFT_U32(sec, DT_RISAF_SEC_SHIFT) | 525 SHIFT_U32(enc, DT_RISAF_ENC_SHIFT + 1) | 526 SHIFT_U32(priv, DT_RISAF_PRIV_SHIFT) | 527 SHIFT_U32(rden, DT_RISAF_READ_SHIFT) | 528 SHIFT_U32(wren, DT_RISAF_WRITE_SHIFT); 529 start_addr = io_read32(base + _RISAF_REG_STARTR(id)); 530 end_addr = io_read32(base + _RISAF_REG_ENDR(id)); 531 region->addr = start_addr + risaf->pdata.mem_base; 532 region->len = end_addr - start_addr + 1; 533 } 534 535 return TEE_SUCCESS; 536 } 537 538 static TEE_Result 539 stm32_risaf_pm(enum pm_op op, unsigned int pm_hint, 540 const struct pm_callback_handle *pm_handle) 541 { 542 struct stm32_risaf_instance *risaf = pm_handle->handle; 543 TEE_Result res = TEE_ERROR_GENERIC; 544 545 assert(risaf); 546 547 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 548 return TEE_SUCCESS; 549 550 if (op == PM_OP_RESUME) 551 res = stm32_risaf_pm_resume(risaf); 552 else 553 res = stm32_risaf_pm_suspend(risaf); 554 555 return res; 556 } 557 558 static TEE_Result stm32_risaf_probe(const void *fdt, int node, 559 const void *compat_data) 560 { 561 const struct stm32_risaf_compat_data *compat = compat_data; 562 struct stm32_risaf_instance *risaf = NULL; 563 struct stm32_risaf_region *regions = NULL; 564 TEE_Result res = TEE_ERROR_GENERIC; 565 struct dt_node_info dt_info = { }; 566 const fdt32_t *conf_list = NULL; 567 const fdt64_t *cuint = NULL; 568 unsigned int nregions = 0; 569 unsigned int i = 0; 570 int len = 0; 571 572 res = stm32_rifsc_check_tdcid(&is_tdcid); 573 if (res) 574 return res; 575 576 if (!is_tdcid) 577 return TEE_SUCCESS; 578 579 risaf = calloc(1, sizeof(*risaf)); 580 if (!risaf) 581 return TEE_ERROR_OUT_OF_MEMORY; 582 583 fdt_fill_device_info(fdt, &dt_info, node); 584 if (dt_info.reg == DT_INFO_INVALID_REG || 585 dt_info.reg_size == DT_INFO_INVALID_REG_SIZE) { 586 free(risaf); 587 return TEE_ERROR_BAD_PARAMETERS; 588 } 589 590 risaf->pdata.base.pa = dt_info.reg; 591 io_pa_or_va_secure(&risaf->pdata.base, dt_info.reg_size); 592 593 risaf->pdata.enc_supported = compat->supported_encryption; 594 595 res = clk_dt_get_by_index(fdt, node, 0, &risaf->pdata.clock); 596 if (!risaf->pdata.clock) 597 goto err; 598 599 conf_list = fdt_getprop(fdt, node, "memory-region", &len); 600 if (!conf_list) { 601 DMSG("RISAF %#"PRIxPA": No configuration in DT, use default", 602 risaf->pdata.base.pa); 603 free(risaf); 604 return TEE_SUCCESS; 605 } 606 607 nregions = (unsigned int)len / sizeof(uint32_t); 608 609 /* Silently allow unexpected truncated names */ 610 strncpy(risaf->pdata.risaf_name, fdt_get_name(fdt, node, NULL), 611 sizeof(risaf->pdata.risaf_name) - 1); 612 613 res = clk_enable(risaf->pdata.clock); 614 if (res) 615 goto err; 616 617 res = stm32_risaf_init_ddata(risaf); 618 if (res) 619 goto err_clk; 620 621 risaf_print_version(risaf); 622 623 cuint = fdt_getprop(fdt, node, "st,mem-map", &len); 624 if (!cuint || (size_t)len != sizeof(*cuint) * 2) 625 panic(); 626 627 risaf->pdata.mem_base = (paddr_t)fdt64_to_cpu(*cuint); 628 risaf->pdata.mem_size = (size_t)fdt64_to_cpu(*(cuint + 1)); 629 630 regions = calloc(nregions, sizeof(*regions)); 631 if (nregions && !regions) { 632 res = TEE_ERROR_OUT_OF_MEMORY; 633 goto err_ddata; 634 } 635 636 DMSG("RISAF %#"PRIxPA" memory range: %#"PRIxPA" - %#"PRIxPA, 637 risaf->pdata.base.pa, risaf->pdata.mem_base, 638 risaf->pdata.mem_base + risaf->pdata.mem_size - 1); 639 640 for (i = 0; i < nregions; i++) { 641 const fdt32_t *prop = NULL; 642 paddr_t start_addr = 0; 643 paddr_t end_addr = 0; 644 uint32_t cid_cfg = 0; 645 uint32_t phandle = 0; 646 uint32_t cfg = 0; 647 uint32_t id = 0; 648 int pnode = 0; 649 650 phandle = fdt32_to_cpu(*(conf_list + i)); 651 pnode = fdt_node_offset_by_phandle(fdt, phandle); 652 if (pnode < 0) 653 continue; 654 655 if (fdt_reg_info(fdt, pnode, ®ions[i].addr, 656 ®ions[i].len)) { 657 EMSG("Invalid config in node %s", 658 fdt_get_name(fdt, pnode, NULL)); 659 panic(); 660 } 661 662 if (!regions[i].len) 663 continue; 664 665 /* 666 * The secure bootloader is in charge of configuring RISAF 667 * related to OP-TEE secure memory. Therefore, skip OP-TEE 668 * region so that RISAF configuration cannot interfere with 669 * OP-TEE execution flow. 670 */ 671 if (regions[i].addr == TZDRAM_BASE && 672 regions[i].len == TZDRAM_SIZE) { 673 continue; 674 } 675 676 prop = fdt_getprop(fdt, pnode, "st,protreg", NULL); 677 if (!prop) 678 continue; 679 680 regions[i].cfg = fdt32_to_cpu(*prop); 681 682 if (risaf_check_region_boundaries(risaf, ®ions[i]) || 683 risaf_check_overlap(risaf, regions, i)) 684 panic(); 685 686 id = _RISAF_GET_REGION_ID(regions[i].cfg); 687 assert(id < risaf->ddata->max_base_regions); 688 689 cfg = stm32_risaf_get_region_config(regions[i].cfg); 690 691 cid_cfg = stm32_risaf_get_region_cid_config(regions[i].cfg); 692 693 start_addr = regions[i].addr; 694 end_addr = start_addr + regions[i].len - 1U; 695 696 if (risaf_configure_region(risaf, id, cfg, cid_cfg, 697 start_addr, end_addr)) 698 panic(); 699 } 700 701 risaf->pdata.regions = regions; 702 risaf->pdata.nregions = nregions; 703 704 SLIST_INSERT_HEAD(&risaf_list, risaf, link); 705 706 register_pm_core_service_cb(stm32_risaf_pm, risaf, "stm32-risaf"); 707 708 return TEE_SUCCESS; 709 710 err_ddata: 711 free(risaf->ddata); 712 err_clk: 713 clk_disable(risaf->pdata.clock); 714 err: 715 free(risaf); 716 return res; 717 } 718 719 static const struct dt_device_match risaf_match_table[] = { 720 { 721 .compatible = "st,stm32mp25-risaf", 722 .compat_data = &stm32_risaf_compat, 723 }, 724 { 725 .compatible = "st,stm32mp25-risaf-enc", 726 .compat_data = &stm32_risaf_enc_compat, 727 }, 728 { } 729 }; 730 731 DEFINE_DT_DRIVER(risaf_dt_driver) = { 732 .name = "stm32-risaf", 733 .match_table = risaf_match_table, 734 .probe = stm32_risaf_probe, 735 }; 736