1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <drivers/stm32_rif.h> 7 #include <drivers/stm32mp_dt_bindings.h> 8 #include <io.h> 9 #include <kernel/boot.h> 10 #include <kernel/dt.h> 11 #include <kernel/dt_driver.h> 12 #include <kernel/panic.h> 13 #include <kernel/pm.h> 14 #include <libfdt.h> 15 #include <mm/core_memprot.h> 16 #include <tee_api_defines.h> 17 #include <trace.h> 18 #include <util.h> 19 20 /* RIFSC offset register */ 21 #define _RIFSC_RISC_SECCFGR0 U(0x10) 22 #define _RIFSC_RISC_PRIVCFGR0 U(0x30) 23 #define _RIFSC_RISC_RCFGLOCKR0 U(0x50) 24 #define _RIFSC_RISC_PER0_CIDCFGR U(0x100) 25 #define _RIFSC_RISC_PER0_SEMCR U(0x104) 26 #define _RIFSC_RIMC_CR U(0xC00) 27 #define _RIFSC_RIMC_ATTR0 U(0xC10) 28 29 #define _RIFSC_HWCFGR3 U(0xFE8) 30 #define _RIFSC_HWCFGR2 U(0xFEC) 31 #define _RIFSC_HWCFGR1 U(0xFF0) 32 #define _RIFSC_VERR U(0xFF4) 33 34 /* RIFSC_HWCFGR2 register fields */ 35 #define _RIFSC_HWCFGR2_CFG1_MASK GENMASK_32(15, 0) 36 #define _RIFSC_HWCFGR2_CFG1_SHIFT U(0) 37 #define _RIFSC_HWCFGR2_CFG2_MASK GENMASK_32(23, 16) 38 #define _RIFSC_HWCFGR2_CFG2_SHIFT U(16) 39 #define _RIFSC_HWCFGR2_CFG3_MASK GENMASK_32(31, 24) 40 #define _RIFSC_HWCFGR2_CFG3_SHIFT U(24) 41 42 /* RIFSC_HWCFGR1 register fields */ 43 #define _RIFSC_HWCFGR1_CFG1_MASK GENMASK_32(3, 0) 44 #define _RIFSC_HWCFGR1_CFG1_SHIFT U(0) 45 #define _RIFSC_HWCFGR1_CFG2_MASK GENMASK_32(7, 4) 46 #define _RIFSC_HWCFGR1_CFG2_SHIFT U(4) 47 #define _RIFSC_HWCFGR1_CFG3_MASK GENMASK_32(11, 8) 48 #define _RIFSC_HWCFGR1_CFG3_SHIFT U(8) 49 #define _RIFSC_HWCFGR1_CFG4_MASK GENMASK_32(15, 12) 50 #define _RIFSC_HWCFGR1_CFG4_SHIFT U(12) 51 #define _RIFSC_HWCFGR1_CFG5_MASK GENMASK_32(19, 16) 52 #define _RIFSC_HWCFGR1_CFG5_SHIFT U(16) 53 #define _RIFSC_HWCFGR1_CFG6_MASK GENMASK_32(23, 20) 54 #define _RIFSC_HWCFGR1_CFG6_SHIFT U(20) 55 56 /* 57 * RISC_CR register fields 58 */ 59 #define _RIFSC_RISC_CR_GLOCK BIT(0) 60 61 /* 62 * RIMC_CR register fields 63 */ 64 #define _RIFSC_RIMC_CR_GLOCK BIT(0) 65 #define _RIFSC_RIMC_CR_TDCID_MASK GENMASK_32(6, 4) 66 67 /* RIFSC_VERR register fields */ 68 #define _RIFSC_VERR_MINREV_MASK GENMASK_32(3, 0) 69 #define _RIFSC_VERR_MINREV_SHIFT U(0) 70 #define _RIFSC_VERR_MAJREV_MASK GENMASK_32(7, 4) 71 #define _RIFSC_VERR_MAJREV_SHIFT U(4) 72 73 /* Periph id per register */ 74 #define _PERIPH_IDS_PER_REG U(32) 75 #define _OFFSET_PERX_CIDCFGR U(0x8) 76 77 #define RIFSC_RISC_CFEN_MASK BIT(0) 78 #define RIFSC_RISC_CFEN_SHIFT U(0) 79 #define RIFSC_RISC_SEM_EN_MASK BIT(1) 80 #define RIFSC_RISC_SEM_EN_SHIFT U(1) 81 #define RIFSC_RISC_SCID_MASK GENMASK_32(6, 4) 82 #define RIFSC_RISC_SCID_SHIFT U(4) 83 #define RIFSC_RISC_SEC_MASK BIT(8) 84 #define RIFSC_RISC_SEC_SHIFT U(8) 85 #define RIFSC_RISC_PRIV_MASK BIT(9) 86 #define RIFSC_RISC_PRIV_SHIFT U(9) 87 #define RIFSC_RISC_LOCK_MASK BIT(10) 88 #define RIFSC_RISC_LOCK_SHIFT U(10) 89 #define RIFSC_RISC_SEML_MASK GENMASK_32(23, 16) 90 #define RIFSC_RISC_SEML_SHIFT U(16) 91 #define RIFSC_RISC_PER_ID_MASK GENMASK_32(31, 24) 92 #define RIFSC_RISC_PER_ID_SHIFT U(24) 93 94 #define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \ 95 RIFSC_RISC_SEM_EN_MASK | \ 96 RIFSC_RISC_SCID_MASK | \ 97 RIFSC_RISC_SEML_MASK) 98 #define RIFSC_RISC_PERx_CID_SHIFT U(0) 99 100 #define RIFSC_RIMC_MODE_MASK BIT(2) 101 #define RIFSC_RIMC_MCID_MASK GENMASK_32(6, 4) 102 #define RIFSC_RIMC_MSEC_MASK BIT(8) 103 #define RIFSC_RIMC_MPRIV_MASK BIT(9) 104 #define RIFSC_RIMC_M_ID_MASK GENMASK_32(23, 16) 105 106 #define RIFSC_RIMC_ATTRx_MASK (RIFSC_RIMC_MODE_MASK | \ 107 RIFSC_RIMC_MCID_MASK | \ 108 RIFSC_RIMC_MSEC_MASK | \ 109 RIFSC_RIMC_MPRIV_MASK) 110 111 /* max entries */ 112 #define MAX_RIMU U(16) 113 #define MAX_RISUP U(128) 114 115 #define _RIF_FLD_GET(field, value) (((uint32_t)(value) & \ 116 (field ## _MASK)) >>\ 117 (field ## _SHIFT)) 118 119 struct risup_cfg { 120 uint32_t cid_attr; 121 uint32_t id; 122 bool sec; 123 bool priv; 124 bool lock; 125 bool pm_sem; 126 }; 127 128 struct rimu_cfg { 129 uint32_t id; 130 uint32_t attr; 131 }; 132 133 struct rifsc_driver_data { 134 bool rif_en; 135 bool sec_en; 136 bool priv_en; 137 uint8_t nb_rimu; 138 uint8_t nb_risup; 139 uint8_t nb_risal; 140 uint8_t version; 141 }; 142 143 struct rifsc_platdata { 144 uintptr_t base; 145 struct rifsc_driver_data *drv_data; 146 struct risup_cfg *risup; 147 unsigned int nrisup; 148 struct rimu_cfg *rimu; 149 unsigned int nrimu; 150 }; 151 152 /* There is only 1 instance of the RIFSC subsystem */ 153 static struct rifsc_driver_data rifsc_drvdata; 154 static struct rifsc_platdata rifsc_pdata; 155 156 static void stm32_rifsc_get_driverdata(struct rifsc_platdata *pdata) 157 { 158 uint32_t regval = 0; 159 160 regval = io_read32(pdata->base + _RIFSC_HWCFGR1); 161 rifsc_drvdata.rif_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG1, regval) != 0; 162 rifsc_drvdata.sec_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG2, regval) != 0; 163 rifsc_drvdata.priv_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG3, regval) != 0; 164 165 regval = io_read32(pdata->base + _RIFSC_HWCFGR2); 166 rifsc_drvdata.nb_risup = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG1, regval); 167 rifsc_drvdata.nb_rimu = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG2, regval); 168 rifsc_drvdata.nb_risal = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG3, regval); 169 170 pdata->drv_data = &rifsc_drvdata; 171 172 rifsc_drvdata.version = io_read8(pdata->base + _RIFSC_VERR); 173 174 DMSG("RIFSC version %"PRIu32".%"PRIu32, 175 _RIF_FLD_GET(_RIFSC_VERR_MAJREV, rifsc_drvdata.version), 176 _RIF_FLD_GET(_RIFSC_VERR_MINREV, rifsc_drvdata.version)); 177 178 DMSG("HW cap: enabled[rif:sec:priv]:[%s:%s:%s] nb[risup|rimu|risal]:[%"PRIu8",%"PRIu8",%"PRIu8"]", 179 rifsc_drvdata.rif_en ? "true" : "false", 180 rifsc_drvdata.sec_en ? "true" : "false", 181 rifsc_drvdata.priv_en ? "true" : "false", 182 rifsc_drvdata.nb_risup, 183 rifsc_drvdata.nb_rimu, 184 rifsc_drvdata.nb_risal); 185 } 186 187 static TEE_Result stm32_rifsc_glock_config(const void *fdt, int node, 188 struct rifsc_platdata *pdata) 189 { 190 const fdt32_t *cuint = NULL; 191 uint32_t glock_conf = 0; 192 int len = 0; 193 194 cuint = fdt_getprop(fdt, node, "st,glocked", &len); 195 if (!cuint) { 196 DMSG("No global lock on RIF configuration"); 197 return TEE_SUCCESS; 198 } 199 assert(len == sizeof(uint32_t)); 200 201 glock_conf = fdt32_to_cpu(*cuint); 202 203 if (glock_conf & RIFSC_RIMU_GLOCK) { 204 DMSG("Setting global lock on RIMU configuration"); 205 206 io_setbits32(pdata->base + _RIFSC_RIMC_CR, 207 _RIFSC_RIMC_CR_GLOCK); 208 209 if (!(io_read32(pdata->base + _RIFSC_RIMC_CR) & 210 _RIFSC_RIMC_CR_GLOCK)) 211 return TEE_ERROR_ACCESS_DENIED; 212 } 213 214 if (glock_conf & RIFSC_RISUP_GLOCK) { 215 DMSG("Setting global lock on RISUP configuration"); 216 217 io_setbits32(pdata->base, _RIFSC_RISC_CR_GLOCK); 218 219 if (!(io_read32(pdata->base) & _RIFSC_RISC_CR_GLOCK)) 220 return TEE_ERROR_ACCESS_DENIED; 221 } 222 223 return TEE_SUCCESS; 224 } 225 226 static TEE_Result stm32_rifsc_dt_conf_risup(const void *fdt, int node, 227 struct rifsc_platdata *pdata) 228 { 229 const fdt32_t *conf_list = NULL; 230 unsigned int i = 0; 231 int len = 0; 232 233 conf_list = fdt_getprop(fdt, node, "st,protreg", &len); 234 if (!conf_list) { 235 DMSG("No RISUP configuration in DT"); 236 return TEE_ERROR_ITEM_NOT_FOUND; 237 } 238 assert(!(len % sizeof(uint32_t))); 239 240 pdata->nrisup = len / sizeof(uint32_t); 241 pdata->risup = calloc(pdata->nrisup, sizeof(*pdata->risup)); 242 if (!pdata->risup) 243 return TEE_ERROR_OUT_OF_MEMORY; 244 245 for (i = 0; i < pdata->nrisup; i++) { 246 uint32_t value = fdt32_to_cpu(conf_list[i]); 247 struct risup_cfg *risup = pdata->risup + i; 248 249 risup->id = _RIF_FLD_GET(RIFSC_RISC_PER_ID, value); 250 risup->sec = _RIF_FLD_GET(RIFSC_RISC_SEC, value) != 0; 251 risup->priv = _RIF_FLD_GET(RIFSC_RISC_PRIV, value) != 0; 252 risup->lock = _RIF_FLD_GET(RIFSC_RISC_LOCK, value) != 0; 253 risup->cid_attr = _RIF_FLD_GET(RIFSC_RISC_PERx_CID, value); 254 } 255 256 return TEE_SUCCESS; 257 } 258 259 static TEE_Result stm32_rifsc_dt_conf_rimu(const void *fdt, int node, 260 struct rifsc_platdata *pdata) 261 { 262 const fdt32_t *conf_list = NULL; 263 unsigned int i = 0; 264 int len = 0; 265 266 conf_list = fdt_getprop(fdt, node, "st,rimu", &len); 267 if (!conf_list) { 268 DMSG("No RIMU configuration in DT"); 269 return TEE_ERROR_ITEM_NOT_FOUND; 270 } 271 assert(!(len % sizeof(uint32_t))); 272 273 pdata->nrimu = len / sizeof(uint32_t); 274 pdata->rimu = calloc(pdata->nrimu, sizeof(*pdata->rimu)); 275 if (!pdata->rimu) 276 return TEE_ERROR_OUT_OF_MEMORY; 277 278 for (i = 0; i < pdata->nrimu; i++) { 279 uint32_t value = fdt32_to_cpu(*conf_list); 280 struct rimu_cfg *rimu = pdata->rimu + i; 281 282 rimu->id = _RIF_FLD_GET(RIFSC_RIMC_M_ID, value); 283 rimu->attr = _RIF_FLD_GET(RIFSC_RIMC_ATTRx, value); 284 } 285 286 return TEE_SUCCESS; 287 } 288 289 static TEE_Result stm32_rifsc_parse_fdt(const void *fdt, int node, 290 struct rifsc_platdata *pdata) 291 { 292 TEE_Result res = TEE_ERROR_GENERIC; 293 struct io_pa_va base = { }; 294 size_t reg_size = 0; 295 296 base.pa = fdt_reg_base_address(fdt, node); 297 if (base.pa == DT_INFO_INVALID_REG) 298 return TEE_ERROR_BAD_PARAMETERS; 299 300 reg_size = fdt_reg_size(fdt, node); 301 if (reg_size == DT_INFO_INVALID_REG_SIZE) 302 return TEE_ERROR_BAD_PARAMETERS; 303 304 pdata->base = io_pa_or_va_secure(&base, reg_size); 305 306 res = stm32_rifsc_dt_conf_risup(fdt, node, pdata); 307 if (res) 308 return res; 309 310 return stm32_rifsc_dt_conf_rimu(fdt, node, pdata); 311 } 312 313 static TEE_Result stm32_risup_cfg(struct rifsc_platdata *pdata, 314 struct risup_cfg *risup) 315 { 316 uintptr_t offset = sizeof(uint32_t) * (risup->id / _PERIPH_IDS_PER_REG); 317 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 318 struct rifsc_driver_data *drv_data = pdata->drv_data; 319 uint32_t shift = risup->id % _PERIPH_IDS_PER_REG; 320 TEE_Result res = TEE_ERROR_GENERIC; 321 322 if (!risup || risup->id >= drv_data->nb_risup) 323 return TEE_ERROR_BAD_PARAMETERS; 324 325 if (drv_data->sec_en) 326 io_clrsetbits32(pdata->base + _RIFSC_RISC_SECCFGR0 + offset, 327 BIT(shift), SHIFT_U32(risup->sec, shift)); 328 329 if (drv_data->priv_en) 330 io_clrsetbits32(pdata->base + _RIFSC_RISC_PRIVCFGR0 + offset, 331 BIT(shift), SHIFT_U32(risup->priv, shift)); 332 333 if (drv_data->rif_en) 334 io_write32(pdata->base + _RIFSC_RISC_PER0_CIDCFGR + 335 cidcfgr_offset, risup->cid_attr); 336 337 /* Lock configuration for this RISUP */ 338 if (risup->lock) { 339 DMSG("Locking RIF conf for peripheral %"PRIu32, risup->id); 340 io_setbits32(pdata->base + _RIFSC_RISC_RCFGLOCKR0 + offset, 341 BIT(shift)); 342 } 343 344 /* Take semaphore if the resource is in semaphore mode and secured */ 345 if (!stm32_rif_semaphore_enabled_and_ok(risup->cid_attr, RIF_CID1) || 346 !(io_read32(pdata->base + _RIFSC_RISC_SECCFGR0 + offset) & 347 BIT(shift))) { 348 res = stm32_rif_release_semaphore(pdata->base + 349 _RIFSC_RISC_PER0_SEMCR + 350 cidcfgr_offset, 351 MAX_CID_SUPPORTED); 352 if (res) { 353 EMSG("Couldn't release semaphore for resource %"PRIu32, 354 risup->id); 355 return TEE_ERROR_ACCESS_DENIED; 356 } 357 } else { 358 res = stm32_rif_acquire_semaphore(pdata->base + 359 _RIFSC_RISC_PER0_SEMCR + 360 cidcfgr_offset, 361 MAX_CID_SUPPORTED); 362 if (res) { 363 EMSG("Couldn't acquire semaphore for resource %"PRIu32, 364 risup->id); 365 return TEE_ERROR_ACCESS_DENIED; 366 } 367 } 368 369 return TEE_SUCCESS; 370 } 371 372 static TEE_Result stm32_risup_setup(struct rifsc_platdata *pdata) 373 { 374 struct rifsc_driver_data *drv_data = pdata->drv_data; 375 TEE_Result res = TEE_ERROR_GENERIC; 376 unsigned int i = 0; 377 378 for (i = 0; i < pdata->nrisup && i < drv_data->nb_risup; i++) { 379 struct risup_cfg *risup = pdata->risup + i; 380 381 res = stm32_risup_cfg(pdata, risup); 382 if (res) { 383 EMSG("risup cfg(%d/%d) error", i + 1, pdata->nrisup); 384 return res; 385 } 386 } 387 388 return TEE_SUCCESS; 389 } 390 391 static TEE_Result stm32_rimu_cfg(struct rifsc_platdata *pdata, 392 struct rimu_cfg *rimu) 393 { 394 uintptr_t offset = _RIFSC_RIMC_ATTR0 + (sizeof(uint32_t) * rimu->id); 395 struct rifsc_driver_data *drv_data = pdata->drv_data; 396 397 if (!rimu || rimu->id >= drv_data->nb_rimu) 398 return TEE_ERROR_BAD_PARAMETERS; 399 400 if (drv_data->rif_en) 401 io_write32(pdata->base + offset, rimu->attr); 402 403 return TEE_SUCCESS; 404 } 405 406 static TEE_Result stm32_rimu_setup(struct rifsc_platdata *pdata) 407 { 408 struct rifsc_driver_data *drv_data = pdata->drv_data; 409 TEE_Result res = TEE_ERROR_GENERIC; 410 unsigned int i = 0; 411 412 for (i = 0; i < pdata->nrimu && i < drv_data->nb_rimu; i++) { 413 struct rimu_cfg *rimu = pdata->rimu + i; 414 415 res = stm32_rimu_cfg(pdata, rimu); 416 if (res) { 417 EMSG("rimu cfg(%d/%d) error", i + 1, pdata->nrimu); 418 return res; 419 } 420 } 421 422 return TEE_SUCCESS; 423 } 424 425 static TEE_Result stm32_rifsc_sem_pm_suspend(void) 426 { 427 unsigned int i = 0; 428 429 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 430 uint32_t semcfgr = io_read32(rifsc_pdata.base + 431 _RIFSC_RISC_PER0_SEMCR + 432 _OFFSET_PERX_CIDCFGR * i); 433 struct risup_cfg *risup = rifsc_pdata.risup + i; 434 435 /* Save semaphores that were taken by the CID1 */ 436 risup->pm_sem = semcfgr & _SEMCR_MUTEX && 437 ((semcfgr & _SEMCR_SEMCID_MASK) >> 438 _SEMCR_SEMCID_SHIFT) == RIF_CID1; 439 440 FMSG("RIF semaphore %s for ID: %"PRIu32, 441 risup->pm_sem ? "SAVED" : "NOT SAVED", risup->id); 442 } 443 444 return TEE_SUCCESS; 445 } 446 447 static TEE_Result stm32_rifsc_sem_pm_resume(void) 448 { 449 TEE_Result res = TEE_ERROR_GENERIC; 450 unsigned int i = 0; 451 452 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 453 struct risup_cfg *risup = rifsc_pdata.risup + i; 454 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 455 uintptr_t offset = sizeof(uint32_t) * 456 (risup->id / _PERIPH_IDS_PER_REG); 457 uintptr_t perih_offset = risup->id % _PERIPH_IDS_PER_REG; 458 uint32_t seccgfr = io_read32(rifsc_pdata.base + 459 _RIFSC_RISC_SECCFGR0 + offset); 460 uint32_t privcgfr = io_read32(rifsc_pdata.base + 461 _RIFSC_RISC_PRIVCFGR0 + offset); 462 uint32_t lockcfgr = io_read32(rifsc_pdata.base + 463 _RIFSC_RISC_RCFGLOCKR0 + offset); 464 465 /* Update RISUPs fields */ 466 risup->cid_attr = io_read32(rifsc_pdata.base + 467 _RIFSC_RISC_PER0_CIDCFGR + 468 cidcfgr_offset); 469 risup->sec = (seccgfr & BIT(perih_offset)) != 0; 470 risup->priv = (privcgfr & BIT(perih_offset)) != 0; 471 risup->lock = (lockcfgr & BIT(perih_offset)) != 0; 472 473 /* Acquire available appropriate semaphores */ 474 if (!stm32_rif_semaphore_enabled_and_ok(risup->cid_attr, 475 RIF_CID1) || 476 !risup->pm_sem) 477 continue; 478 479 res = stm32_rif_acquire_semaphore(rifsc_pdata.base + 480 _RIFSC_RISC_PER0_SEMCR + 481 cidcfgr_offset, 482 MAX_CID_SUPPORTED); 483 if (res) { 484 EMSG("Could not acquire semaphore for resource %"PRIu32, 485 risup->id); 486 return TEE_ERROR_ACCESS_DENIED; 487 } 488 } 489 490 return TEE_SUCCESS; 491 } 492 493 static TEE_Result 494 stm32_rifsc_sem_pm(enum pm_op op, unsigned int pm_hint, 495 const struct pm_callback_handle *pm_handle __unused) 496 { 497 TEE_Result res = TEE_ERROR_GENERIC; 498 499 if (pm_hint != PM_HINT_CONTEXT_STATE) 500 return TEE_SUCCESS; 501 502 if (op == PM_OP_RESUME) 503 res = stm32_rifsc_sem_pm_resume(); 504 else 505 res = stm32_rifsc_sem_pm_suspend(); 506 507 return res; 508 } 509 510 TEE_Result stm32_rifsc_check_tdcid(bool *tdcid_state) 511 { 512 if (!rifsc_pdata.base) 513 return TEE_ERROR_DEFER_DRIVER_INIT; 514 515 if (((io_read32(rifsc_pdata.base + _RIFSC_RIMC_CR) & 516 _RIFSC_RIMC_CR_TDCID_MASK)) == (RIF_CID1 << SCID_SHIFT)) 517 *tdcid_state = true; 518 else 519 *tdcid_state = false; 520 521 return TEE_SUCCESS; 522 } 523 524 static TEE_Result stm32_rifsc_probe(const void *fdt, int node, 525 const void *compat_data __unused) 526 { 527 TEE_Result res = TEE_ERROR_GENERIC; 528 529 res = stm32_rifsc_parse_fdt(fdt, node, &rifsc_pdata); 530 if (res) { 531 EMSG("Could not parse RIFSC node, res = %#"PRIx32, res); 532 panic(); 533 } 534 535 if (!rifsc_pdata.drv_data) 536 stm32_rifsc_get_driverdata(&rifsc_pdata); 537 538 res = stm32_risup_setup(&rifsc_pdata); 539 if (res) { 540 EMSG("Could not setup RISUPs, res = %#"PRIx32, res); 541 panic(); 542 } 543 544 res = stm32_rimu_setup(&rifsc_pdata); 545 if (res) { 546 EMSG("Could not setup RIMUs, res = %#"PRIx32, res); 547 panic(); 548 } 549 550 res = stm32_rifsc_glock_config(fdt, node, &rifsc_pdata); 551 if (res) 552 panic("Couldn't lock RIFSC configuration"); 553 554 register_pm_core_service_cb(stm32_rifsc_sem_pm, NULL, 555 "stm32-rifsc-semaphores"); 556 557 return TEE_SUCCESS; 558 } 559 560 static const struct dt_device_match rifsc_match_table[] = { 561 { .compatible = "st,stm32mp25-rifsc" }, 562 { } 563 }; 564 565 DEFINE_DT_DRIVER(rifsc_dt_driver) = { 566 .name = "stm32-rifsc", 567 .match_table = rifsc_match_table, 568 .probe = stm32_rifsc_probe, 569 }; 570