1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <drivers/firewall.h> 7 #include <drivers/stm32_rif.h> 8 #include <drivers/stm32_shared_io.h> 9 #include <drivers/stm32mp_dt_bindings.h> 10 #include <io.h> 11 #include <kernel/boot.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <kernel/panic.h> 15 #include <kernel/pm.h> 16 #include <libfdt.h> 17 #include <mm/core_memprot.h> 18 #include <stm32_util.h> 19 #include <tee_api_defines.h> 20 #include <trace.h> 21 #include <util.h> 22 23 /* RIFSC offset register */ 24 #define _RIFSC_RISC_SECCFGR0 U(0x10) 25 #define _RIFSC_RISC_PRIVCFGR0 U(0x30) 26 #define _RIFSC_RISC_RCFGLOCKR0 U(0x50) 27 #define _RIFSC_RISC_PER0_CIDCFGR U(0x100) 28 #define _RIFSC_RISC_PER0_SEMCR U(0x104) 29 #define _RIFSC_RIMC_CR U(0xC00) 30 #define _RIFSC_RIMC_ATTR0 U(0xC10) 31 #if defined(CFG_STM32MP25) 32 #define _RIFSC_RISAL_CFGR0_A(y) (U(0x900) + (0x10 * ((y) - 1))) 33 #define _RIFSC_RISAL_CFGR0_B(y) (U(0x908) + (0x10 * ((y) - 1))) 34 #define _RIFSC_RISAL_ADDR_A U(0x924) 35 #define _RIFSC_RISAL_ADDR_B U(0x92C) 36 #endif /* CFG_STM32MP25 */ 37 #define _RIFSC_HWCFGR3 U(0xFE8) 38 #define _RIFSC_HWCFGR2 U(0xFEC) 39 #define _RIFSC_HWCFGR1 U(0xFF0) 40 #define _RIFSC_VERR U(0xFF4) 41 42 /* RIFSC_HWCFGR2 register fields */ 43 #define _RIFSC_HWCFGR2_CFG1_MASK GENMASK_32(15, 0) 44 #define _RIFSC_HWCFGR2_CFG1_SHIFT U(0) 45 #define _RIFSC_HWCFGR2_CFG2_MASK GENMASK_32(23, 16) 46 #define _RIFSC_HWCFGR2_CFG2_SHIFT U(16) 47 #define _RIFSC_HWCFGR2_CFG3_MASK GENMASK_32(31, 24) 48 #define _RIFSC_HWCFGR2_CFG3_SHIFT U(24) 49 50 /* RIFSC_HWCFGR1 register fields */ 51 #define _RIFSC_HWCFGR1_CFG1_MASK GENMASK_32(3, 0) 52 #define _RIFSC_HWCFGR1_CFG1_SHIFT U(0) 53 #define _RIFSC_HWCFGR1_CFG2_MASK GENMASK_32(7, 4) 54 #define _RIFSC_HWCFGR1_CFG2_SHIFT U(4) 55 #define _RIFSC_HWCFGR1_CFG3_MASK GENMASK_32(11, 8) 56 #define _RIFSC_HWCFGR1_CFG3_SHIFT U(8) 57 #define _RIFSC_HWCFGR1_CFG4_MASK GENMASK_32(15, 12) 58 #define _RIFSC_HWCFGR1_CFG4_SHIFT U(12) 59 #define _RIFSC_HWCFGR1_CFG5_MASK GENMASK_32(19, 16) 60 #define _RIFSC_HWCFGR1_CFG5_SHIFT U(16) 61 #define _RIFSC_HWCFGR1_CFG6_MASK GENMASK_32(23, 20) 62 #define _RIFSC_HWCFGR1_CFG6_SHIFT U(20) 63 64 /* 65 * RISC_CR register fields 66 */ 67 #define _RIFSC_RISC_CR_GLOCK BIT(0) 68 69 /* 70 * RIMC_CR register fields 71 */ 72 #define _RIFSC_RIMC_CR_GLOCK BIT(0) 73 #define _RIFSC_RIMC_CR_TDCID_MASK GENMASK_32(6, 4) 74 75 /* RIFSC_VERR register fields */ 76 #define _RIFSC_VERR_MINREV_MASK GENMASK_32(3, 0) 77 #define _RIFSC_VERR_MINREV_SHIFT U(0) 78 #define _RIFSC_VERR_MAJREV_MASK GENMASK_32(7, 4) 79 #define _RIFSC_VERR_MAJREV_SHIFT U(4) 80 81 /* Periph id per register */ 82 #define _PERIPH_IDS_PER_REG U(32) 83 #define _OFFSET_PERX_CIDCFGR U(0x8) 84 85 #define RIFSC_RISC_CIDCFGR_CFEN_MASK BIT(0) 86 #define RIFSC_RISC_CIDCFGR_CFEN_SHIFT U(0) 87 #define RIFSC_RISC_CIDCFGR_SEM_EN_MASK BIT(1) 88 #define RIFSC_RISC_CIDCFGR_SEM_EN_SHIFT U(1) 89 #define RIFSC_RISC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 90 #define RIFSC_RISC_CIDCFGR_SCID_SHIFT U(4) 91 #define RIFSC_RISC_CIDCFGR_LOCK_MASK BIT(10) 92 #define RIFSC_RISC_CIDCFGR_LOCK_SHIFT U(10) 93 #define RIFSC_RISC_CIDCFGR_SEML_MASK GENMASK_32(23, 16) 94 #define RIFSC_RISC_CIDCFGR_SEML_SHIFT U(16) 95 96 #define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CIDCFGR_CFEN_MASK | \ 97 RIFSC_RISC_CIDCFGR_SEM_EN_MASK | \ 98 RIFSC_RISC_CIDCFGR_SCID_MASK | \ 99 RIFSC_RISC_CIDCFGR_SCID_SHIFT) 100 101 #define RIFSC_RISC_PERx_CID_SHIFT U(0) 102 103 #define RIFSC_RIMC_CIDSEL_MASK BIT(2) 104 #define RIFSC_RIMC_CIDSEL_SHIFT U(2) 105 #define RIFSC_RIMC_MCID_MASK GENMASK_32(6, 4) 106 #define RIFSC_RIMC_MCID_SHIFT U(4) 107 #define RIFSC_RIMC_MSEC_MASK BIT(8) 108 #define RIFSC_RIMC_MPRIV_MASK BIT(9) 109 #define RIFSC_RIMC_M_ID_MASK GENMASK_32(23, 16) 110 111 #define RIFSC_RIMC_ATTRx_MASK (RIFSC_RIMC_MODE_MASK | \ 112 RIFSC_RIMC_MCID_MASK | \ 113 RIFSC_RIMC_MSEC_MASK | \ 114 RIFSC_RIMC_MPRIV_MASK) 115 116 /* max entries */ 117 #define MAX_RIMU U(16) 118 #define MAX_RISUP U(128) 119 120 #define _RIF_FLD_GET(field, value) (((uint32_t)(value) & \ 121 (field ## _MASK)) >>\ 122 (field ## _SHIFT)) 123 124 #define NO_RISUP_ID UINT32_MAX 125 126 struct risup_cfg { 127 uint32_t cid_attr; 128 uint32_t id; 129 bool sec; 130 bool priv; 131 bool lock; 132 bool pm_sem; 133 }; 134 135 struct rimu_cfg { 136 uint32_t id; 137 uint32_t risup_id; 138 uint32_t attr; 139 }; 140 141 struct risal_cfg { 142 uint32_t id; 143 uint32_t blockid; 144 uint32_t attr; 145 }; 146 147 struct rifsc_driver_data { 148 bool rif_en; 149 bool sec_en; 150 bool priv_en; 151 uint8_t nb_rimu; 152 uint8_t nb_risup; 153 #if defined(CFG_STM32MP25) 154 uint8_t nb_risal; 155 #endif /* CFG_STM32MP25 */ 156 uint8_t version; 157 }; 158 159 struct rifsc_platdata { 160 uintptr_t base; 161 struct rifsc_driver_data *drv_data; 162 struct risup_cfg *risup; 163 unsigned int nrisup; 164 struct rimu_cfg *rimu; 165 unsigned int nrimu; 166 #if defined(CFG_STM32MP25) 167 struct risal_cfg *risal; 168 unsigned int nrisal; 169 #endif /* CFG_STM32MP25 */ 170 bool is_tdcid; 171 bool errata_ahbrisab; 172 }; 173 174 /** 175 * struct rimu_risup_pairs - Association of a RISUP and RIMU ID for a peripheral 176 * 177 * @rimu_id: ID of the RIMU 178 * @risup_id: ID of the associated RISUP 179 */ 180 struct rimu_risup_pairs { 181 uint32_t rimu_id; 182 uint32_t risup_id; 183 }; 184 185 #if defined(CFG_STM32MP25) || defined(CFG_STM32MP23) 186 static const struct rimu_risup_pairs rimu_risup[] = { 187 [0] = { 188 .rimu_id = 0, 189 .risup_id = NO_RISUP_ID, 190 }, 191 [1] = { 192 .rimu_id = 1, 193 .risup_id = STM32MP25_RIFSC_SDMMC1_ID, 194 }, 195 [2] = { 196 .rimu_id = 2, 197 .risup_id = STM32MP25_RIFSC_SDMMC2_ID, 198 }, 199 [3] = { 200 .rimu_id = 3, 201 .risup_id = STM32MP25_RIFSC_SDMMC3_ID, 202 }, 203 [4] = { 204 .rimu_id = 4, 205 .risup_id = STM32MP25_RIFSC_USB3DR_ID, 206 }, 207 [5] = { 208 .rimu_id = 5, 209 .risup_id = STM32MP25_RIFSC_USBH_ID, 210 }, 211 [6] = { 212 .rimu_id = 6, 213 .risup_id = STM32MP25_RIFSC_ETH1_ID, 214 }, 215 [7] = { 216 .rimu_id = 7, 217 .risup_id = STM32MP25_RIFSC_ETH2_ID, 218 }, 219 [8] = { 220 .rimu_id = 8, 221 .risup_id = STM32MP25_RIFSC_PCIE_ID, 222 }, 223 [9] = { 224 .rimu_id = 9, 225 .risup_id = STM32MP25_RIFSC_GPU_ID, 226 }, 227 [10] = { 228 .rimu_id = 10, 229 .risup_id = STM32MP25_RIFSC_DCMIPP_ID, 230 }, 231 [11] = { 232 .rimu_id = 11, 233 .risup_id = NO_RISUP_ID, 234 }, 235 [12] = { 236 .rimu_id = 12, 237 .risup_id = NO_RISUP_ID, 238 }, 239 [13] = { 240 .rimu_id = 13, 241 .risup_id = NO_RISUP_ID, 242 }, 243 [14] = { 244 .rimu_id = 14, 245 .risup_id = STM32MP25_RIFSC_VDEC_ID, 246 }, 247 [15] = { 248 .rimu_id = 15, 249 .risup_id = STM32MP25_RIFSC_VENC_ID, 250 }, 251 }; 252 #endif /* CFG_STM32MP25 || CFG_STM32MP23 */ 253 #if defined(CFG_STM32MP21) 254 static const struct rimu_risup_pairs rimu_risup[] = { 255 [0] = { 256 .rimu_id = 0, 257 .risup_id = NO_RISUP_ID, 258 }, 259 [1] = { 260 .rimu_id = 1, 261 .risup_id = STM32MP21_RIFSC_SDMMC1_ID, 262 }, 263 [2] = { 264 .rimu_id = 2, 265 .risup_id = STM32MP21_RIFSC_SDMMC2_ID, 266 }, 267 [3] = { 268 .rimu_id = 3, 269 .risup_id = STM32MP21_RIFSC_SDMMC3_ID, 270 }, 271 [4] = { 272 .rimu_id = 4, 273 .risup_id = STM32MP21_RIFSC_OTG_HS_ID, 274 }, 275 [5] = { 276 .rimu_id = 5, 277 .risup_id = STM32MP21_RIFSC_USBH_ID, 278 }, 279 [6] = { 280 .rimu_id = 6, 281 .risup_id = STM32MP21_RIFSC_ETH1_ID, 282 }, 283 [7] = { 284 .rimu_id = 7, 285 .risup_id = STM32MP21_RIFSC_ETH2_ID, 286 }, 287 [10] = { 288 .rimu_id = 10, 289 .risup_id = STM32MP21_RIFSC_DCMIPP_ID, 290 }, 291 [11] = { 292 .rimu_id = 11, 293 .risup_id = NO_RISUP_ID, 294 }, 295 [12] = { 296 .rimu_id = 12, 297 .risup_id = NO_RISUP_ID, 298 }, 299 }; 300 #endif /* CFG_STM32MP21 */ 301 302 /* There is only 1 instance of the RIFSC subsystem */ 303 static struct rifsc_driver_data rifsc_drvdata; 304 static struct rifsc_platdata rifsc_pdata; 305 306 static void stm32_rifsc_get_driverdata(struct rifsc_platdata *pdata) 307 { 308 uint32_t regval = 0; 309 310 regval = io_read32(pdata->base + _RIFSC_HWCFGR1); 311 rifsc_drvdata.rif_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG1, regval) != 0; 312 rifsc_drvdata.sec_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG2, regval) != 0; 313 rifsc_drvdata.priv_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG3, regval) != 0; 314 315 regval = io_read32(pdata->base + _RIFSC_HWCFGR2); 316 rifsc_drvdata.nb_risup = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG1, regval); 317 rifsc_drvdata.nb_rimu = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG2, regval); 318 #if defined(CFG_STM32MP25) 319 rifsc_drvdata.nb_risal = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG3, regval); 320 #endif /* CFG_STM32MP25 */ 321 322 pdata->drv_data = &rifsc_drvdata; 323 324 rifsc_drvdata.version = io_read8(pdata->base + _RIFSC_VERR); 325 326 DMSG("RIFSC version %"PRIu32".%"PRIu32, 327 _RIF_FLD_GET(_RIFSC_VERR_MAJREV, rifsc_drvdata.version), 328 _RIF_FLD_GET(_RIFSC_VERR_MINREV, rifsc_drvdata.version)); 329 330 #if defined(CFG_STM32MP25) 331 DMSG("HW cap: enabled[rif:sec:priv]:[%s:%s:%s] nb[risup|rimu|risal]:[%"PRIu8",%"PRIu8",%"PRIu8"]", 332 rifsc_drvdata.rif_en ? "true" : "false", 333 rifsc_drvdata.sec_en ? "true" : "false", 334 rifsc_drvdata.priv_en ? "true" : "false", 335 rifsc_drvdata.nb_risup, 336 rifsc_drvdata.nb_rimu, 337 rifsc_drvdata.nb_risal); 338 #else /* CFG_STM32MP25 */ 339 DMSG("HW cap: enabled[rif:sec:priv]:[%s:%s:%s] nb[risup|rimu]:[%"PRIu8",%"PRIu8"]", 340 rifsc_drvdata.rif_en ? "true" : "false", 341 rifsc_drvdata.sec_en ? "true" : "false", 342 rifsc_drvdata.priv_en ? "true" : "false", 343 rifsc_drvdata.nb_risup, 344 rifsc_drvdata.nb_rimu); 345 #endif 346 } 347 348 static TEE_Result stm32_rifsc_glock_config(const void *fdt, int node, 349 struct rifsc_platdata *pdata) 350 { 351 const fdt32_t *cuint = NULL; 352 uint32_t glock_conf = 0; 353 int len = 0; 354 355 cuint = fdt_getprop(fdt, node, "st,glocked", &len); 356 if (!cuint) { 357 DMSG("No global lock on RIF configuration"); 358 return TEE_SUCCESS; 359 } 360 assert(len == sizeof(uint32_t)); 361 362 glock_conf = fdt32_to_cpu(*cuint); 363 364 if (glock_conf & RIFSC_RIMU_GLOCK) { 365 DMSG("Setting global lock on RIMU configuration"); 366 367 io_setbits32(pdata->base + _RIFSC_RIMC_CR, 368 _RIFSC_RIMC_CR_GLOCK); 369 370 if (!(io_read32(pdata->base + _RIFSC_RIMC_CR) & 371 _RIFSC_RIMC_CR_GLOCK)) 372 return TEE_ERROR_ACCESS_DENIED; 373 } 374 375 if (glock_conf & RIFSC_RISUP_GLOCK) { 376 DMSG("Setting global lock on RISUP configuration"); 377 378 io_setbits32(pdata->base, _RIFSC_RISC_CR_GLOCK); 379 380 if (!(io_read32(pdata->base) & _RIFSC_RISC_CR_GLOCK)) 381 return TEE_ERROR_ACCESS_DENIED; 382 } 383 384 return TEE_SUCCESS; 385 } 386 387 static TEE_Result stm32_rifsc_dt_conf_risup(const void *fdt, int node, 388 struct rifsc_platdata *pdata) 389 { 390 const fdt32_t *conf_list = NULL; 391 unsigned int i = 0; 392 int len = 0; 393 394 conf_list = fdt_getprop(fdt, node, "st,protreg", &len); 395 if (!conf_list) { 396 DMSG("No RISUP configuration in DT"); 397 return TEE_ERROR_ITEM_NOT_FOUND; 398 } 399 assert(!(len % sizeof(uint32_t))); 400 401 pdata->nrisup = len / sizeof(uint32_t); 402 pdata->risup = calloc(pdata->nrisup, sizeof(*pdata->risup)); 403 if (!pdata->risup) 404 return TEE_ERROR_OUT_OF_MEMORY; 405 406 for (i = 0; i < pdata->nrisup; i++) { 407 uint32_t value = fdt32_to_cpu(conf_list[i]); 408 struct risup_cfg *risup = pdata->risup + i; 409 410 risup->id = _RIF_FLD_GET(RIF_PER_ID, value); 411 risup->sec = _RIF_FLD_GET(RIF_SEC, value) != 0; 412 risup->priv = _RIF_FLD_GET(RIF_PRIV, value) != 0; 413 risup->lock = _RIF_FLD_GET(RIF_LOCK, value) != 0; 414 risup->cid_attr = _RIF_FLD_GET(RIF_PERx_CID, value); 415 } 416 417 return TEE_SUCCESS; 418 } 419 420 static TEE_Result stm32_rifsc_dt_conf_rimu(const void *fdt, int node, 421 struct rifsc_platdata *pdata) 422 { 423 const fdt32_t *conf_list = NULL; 424 unsigned int i = 0; 425 int len = 0; 426 427 conf_list = fdt_getprop(fdt, node, "st,rimu", &len); 428 if (!conf_list) { 429 DMSG("No RIMU configuration in DT"); 430 return TEE_ERROR_ITEM_NOT_FOUND; 431 } 432 assert(!(len % sizeof(uint32_t))); 433 434 pdata->nrimu = len / sizeof(uint32_t); 435 pdata->rimu = calloc(pdata->nrimu, sizeof(*pdata->rimu)); 436 if (!pdata->rimu) 437 return TEE_ERROR_OUT_OF_MEMORY; 438 439 for (i = 0; i < pdata->nrimu; i++) { 440 uint32_t value = fdt32_to_cpu(conf_list[i]); 441 struct rimu_cfg *rimu = pdata->rimu + i; 442 443 rimu->id = _RIF_FLD_GET(RIMUPROT_RIMC_M_ID, value) - 444 RIMU_ID_OFFSET; 445 rimu->attr = _RIF_FLD_GET(RIMUPROT_RIMC_ATTRx, value); 446 } 447 448 return TEE_SUCCESS; 449 } 450 451 #if defined(CFG_STM32MP25) 452 static TEE_Result stm32_rifsc_dt_conf_risal(const void *fdt, int node, 453 struct rifsc_platdata *pdata) 454 { 455 const fdt32_t *cuint = NULL; 456 int i = 0; 457 int len = 0; 458 459 cuint = fdt_getprop(fdt, node, "st,risal", &len); 460 if (!cuint) { 461 DMSG("No RISAL configuration in DT"); 462 pdata->nrisal = 0; 463 return TEE_ERROR_ITEM_NOT_FOUND; 464 } 465 466 len = len / sizeof(uint32_t); 467 468 pdata->nrisal = len; 469 pdata->risal = calloc(len, sizeof(*pdata->risal)); 470 if (!pdata->risal) 471 return TEE_ERROR_OUT_OF_MEMORY; 472 473 for (i = 0; i < len; i++) { 474 uint32_t value = fdt32_to_cpu(cuint[i]); 475 struct risal_cfg *risal = pdata->risal + i; 476 477 risal->id = _RIF_FLD_GET(RIFSC_RISAL_REG_ID, value); 478 risal->blockid = _RIF_FLD_GET(RIFSC_RISAL_BLOCK_ID, value); 479 risal->attr = _RIF_FLD_GET(RIFSC_RISAL_REGx_CFGR, value); 480 } 481 482 return TEE_SUCCESS; 483 } 484 #endif /* CFG_STM32MP25 */ 485 486 static TEE_Result stm32_rifsc_parse_fdt(const void *fdt, int node, 487 struct rifsc_platdata *pdata) 488 { 489 TEE_Result res = TEE_ERROR_GENERIC; 490 struct io_pa_va base = { }; 491 size_t reg_size = 0; 492 493 if (fdt_reg_info(fdt, node, &base.pa, ®_size)) 494 return TEE_ERROR_BAD_PARAMETERS; 495 496 pdata->base = io_pa_or_va_secure(&base, reg_size); 497 498 res = stm32_rifsc_check_tdcid(&rifsc_pdata.is_tdcid); 499 if (res) 500 panic(); 501 502 res = stm32_rifsc_dt_conf_risup(fdt, node, pdata); 503 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 504 return res; 505 506 if (rifsc_pdata.is_tdcid) { 507 res = stm32_rifsc_dt_conf_rimu(fdt, node, pdata); 508 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 509 return res; 510 511 #if defined(CFG_STM32MP25) 512 res = stm32_rifsc_dt_conf_risal(fdt, node, pdata); 513 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 514 return res; 515 #endif /* CFG_STM32MP25 */ 516 } 517 518 rifsc_pdata.errata_ahbrisab = fdt_getprop(fdt, node, 519 "st,errata-ahbrisab", NULL); 520 521 return TEE_SUCCESS; 522 } 523 524 static TEE_Result stm32_risup_cfg(struct rifsc_platdata *pdata, 525 struct risup_cfg *risup) 526 { 527 uintptr_t offset = sizeof(uint32_t) * (risup->id / _PERIPH_IDS_PER_REG); 528 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 529 struct rifsc_driver_data *drv_data = pdata->drv_data; 530 uint32_t shift = risup->id % _PERIPH_IDS_PER_REG; 531 532 if (!risup || risup->id >= drv_data->nb_risup) 533 return TEE_ERROR_BAD_PARAMETERS; 534 535 if (drv_data->sec_en) 536 io_clrsetbits32_stm32shregs(pdata->base + _RIFSC_RISC_SECCFGR0 + 537 offset, BIT(shift), 538 SHIFT_U32(risup->sec, shift)); 539 540 if (drv_data->priv_en) 541 io_clrsetbits32_stm32shregs(pdata->base + 542 _RIFSC_RISC_PRIVCFGR0 + offset, 543 BIT(shift), 544 SHIFT_U32(risup->priv, shift)); 545 546 if (rifsc_pdata.is_tdcid) { 547 if (drv_data->rif_en) 548 io_write32(pdata->base + _RIFSC_RISC_PER0_CIDCFGR + 549 cidcfgr_offset, risup->cid_attr); 550 551 /* Lock configuration for this RISUP */ 552 if (risup->lock) { 553 DMSG("Locking RIF conf for peripheral ID: %"PRIu32, 554 risup->id); 555 io_setbits32_stm32shregs(pdata->base + 556 _RIFSC_RISC_RCFGLOCKR0 + 557 offset, BIT(shift)); 558 } 559 } 560 561 return TEE_SUCCESS; 562 } 563 564 static TEE_Result stm32_risup_setup(struct rifsc_platdata *pdata) 565 { 566 struct rifsc_driver_data *drv_data = pdata->drv_data; 567 TEE_Result res = TEE_ERROR_GENERIC; 568 unsigned int i = 0; 569 570 for (i = 0; i < pdata->nrisup && i < drv_data->nb_risup; i++) { 571 struct risup_cfg *risup = pdata->risup + i; 572 573 res = stm32_risup_cfg(pdata, risup); 574 if (res) { 575 EMSG("risup cfg(%d/%d) error", i + 1, pdata->nrisup); 576 return res; 577 } 578 } 579 580 return TEE_SUCCESS; 581 } 582 583 /* 584 * Errata: When CID filtering is enabled on one of RISAB 3/4/5 instances, we 585 * forbid the use of CID0 for any initiator on the bus to handle transient CID0 586 * transactions on these RAMs. 587 */ 588 static void stm32_rimu_errata_ahbrisab(struct rifsc_platdata *pdata, 589 struct rimu_cfg *rimu) 590 { 591 unsigned int i = 0; 592 593 if (!pdata->errata_ahbrisab) 594 return; 595 596 for (i = 0; i < ARRAY_SIZE(rimu_risup); i++) { 597 if (rimu->id == rimu_risup[i].rimu_id) { 598 rimu->risup_id = rimu_risup[i].risup_id; 599 break; 600 } 601 } 602 603 if (i == ARRAY_SIZE(rimu_risup)) 604 panic(); 605 606 if (rimu->attr & RIFSC_RIMC_CIDSEL_MASK) { 607 /* No inheritance mode for this RIMU */ 608 if ((rimu->attr & RIFSC_RIMC_MCID_MASK) >> 609 RIFSC_RIMC_MCID_SHIFT == RIF_CID0) { 610 EMSG("A CID should be set for RIMU %"PRIu32, rimu->id); 611 if (!IS_ENABLED(CFG_INSECURE)) 612 panic(); 613 } 614 } else { 615 struct risup_cfg *risup = NULL; 616 uint32_t risup_cidcfgr = 0; 617 unsigned int j = 0; 618 619 /* Handle RIMU with no inheritance mode */ 620 if (rimu->risup_id == NO_RISUP_ID) { 621 EMSG("RIMU %"PRIu32" cannot be set in inheritance mode", 622 rimu->id); 623 if (!IS_ENABLED(CFG_INSECURE)) 624 panic(); 625 return; 626 } 627 628 for (j = 0; j < pdata->nrisup; j++) { 629 if (rimu->risup_id == pdata->risup[j].id) { 630 risup = &pdata->risup[j]; 631 break; 632 } 633 } 634 635 if (!risup) 636 panic(); 637 638 risup_cidcfgr = io_read32(pdata->base + 639 _RIFSC_RISC_PER0_CIDCFGR + 640 _OFFSET_PERX_CIDCFGR * risup->id); 641 642 if (!(risup_cidcfgr & RIFSC_RISC_CIDCFGR_CFEN_MASK) || 643 (!(risup_cidcfgr & RIFSC_RISC_CIDCFGR_SEM_EN_MASK) && 644 ((risup_cidcfgr & RIFSC_RISC_CIDCFGR_SCID_MASK) >> 645 RIFSC_RISC_CIDCFGR_SCID_SHIFT) == RIF_CID0) || 646 (risup_cidcfgr & RIFSC_RISC_CIDCFGR_SEM_EN_MASK && 647 risup_cidcfgr & BIT(RIF_CID0 + 648 RIFSC_RISC_CIDCFGR_SEML_SHIFT))) { 649 EMSG("RIMU %"PRIu32" in inheritance mode with CID0", 650 rimu->id); 651 if (!IS_ENABLED(CFG_INSECURE)) 652 panic(); 653 } 654 } 655 } 656 657 static TEE_Result stm32_rimu_cfg(struct rifsc_platdata *pdata, 658 struct rimu_cfg *rimu) 659 { 660 uintptr_t offset = _RIFSC_RIMC_ATTR0 + (sizeof(uint32_t) * rimu->id); 661 struct rifsc_driver_data *drv_data = pdata->drv_data; 662 663 if (!rimu || rimu->id >= drv_data->nb_rimu) 664 return TEE_ERROR_BAD_PARAMETERS; 665 666 stm32_rimu_errata_ahbrisab(pdata, rimu); 667 668 if (drv_data->rif_en) 669 io_write32(pdata->base + offset, rimu->attr); 670 671 return TEE_SUCCESS; 672 } 673 674 static TEE_Result stm32_rimu_setup(struct rifsc_platdata *pdata) 675 { 676 struct rifsc_driver_data *drv_data = pdata->drv_data; 677 TEE_Result res = TEE_ERROR_GENERIC; 678 unsigned int i = 0; 679 680 for (i = 0; i < pdata->nrimu && i < drv_data->nb_rimu; i++) { 681 struct rimu_cfg *rimu = pdata->rimu + i; 682 683 res = stm32_rimu_cfg(pdata, rimu); 684 if (res) { 685 EMSG("rimu cfg(%d/%d) error", i + 1, pdata->nrimu); 686 return res; 687 } 688 } 689 690 return TEE_SUCCESS; 691 } 692 693 #if defined(CFG_STM32MP25) 694 static TEE_Result stm32_risal_cfg(struct rifsc_platdata *pdata, 695 struct risal_cfg *risal) 696 { 697 struct rifsc_driver_data *drv_data = pdata->drv_data; 698 699 if (!risal || risal->id > drv_data->nb_risal) 700 return TEE_ERROR_BAD_PARAMETERS; 701 702 if (drv_data->rif_en) { 703 uintptr_t offset_a = _RIFSC_RISAL_CFGR0_A(risal->id); 704 uintptr_t offset_b = _RIFSC_RISAL_CFGR0_B(risal->id); 705 706 if (risal->blockid == RIFSC_RISAL_BLOCK_A) 707 io_write32(pdata->base + offset_a, risal->attr); 708 if (risal->blockid == RIFSC_RISAL_BLOCK_B) 709 io_write32(pdata->base + offset_b, risal->attr); 710 } 711 712 return TEE_SUCCESS; 713 } 714 715 static TEE_Result stm32_risal_setup(struct rifsc_platdata *pdata) 716 { 717 unsigned int i = 0; 718 TEE_Result res = TEE_ERROR_GENERIC; 719 720 for (i = 0; i < pdata->nrisal; i++) { 721 struct risal_cfg *risal = pdata->risal + i; 722 723 res = stm32_risal_cfg(pdata, risal); 724 if (res) { 725 EMSG("risal cfg(%u/%u) error", i + 1, pdata->nrisal); 726 return res; 727 } 728 } 729 730 return TEE_SUCCESS; 731 } 732 #endif /* CFG_STM32MP25 */ 733 734 static TEE_Result stm32_rifsc_check_access(struct firewall_query *firewall) 735 { 736 uintptr_t rifsc_base = rifsc_pdata.base; 737 unsigned int cid_reg_offset = 0; 738 unsigned int periph_offset = 0; 739 unsigned int resource_id = 0; 740 uint32_t cid_to_check = 0; 741 unsigned int reg_id = 0; 742 bool priv_check = true; 743 bool sec_check = true; 744 uint32_t privcfgr = 0; 745 uint32_t seccfgr = 0; 746 uint32_t cidcfgr = 0; 747 748 assert(rifsc_base); 749 750 if (!firewall || firewall->arg_count != 1) 751 return TEE_ERROR_BAD_PARAMETERS; 752 753 /* 754 * Peripheral configuration, we assume the configuration is as 755 * follows: 756 * firewall->args[0]: RIF configuration to check 757 */ 758 resource_id = firewall->args[0] & RIF_PER_ID_MASK; 759 if (resource_id >= RIMU_ID_OFFSET) 760 return TEE_SUCCESS; 761 762 reg_id = resource_id / _PERIPH_IDS_PER_REG; 763 periph_offset = resource_id % _PERIPH_IDS_PER_REG; 764 cid_reg_offset = _OFFSET_PERX_CIDCFGR * resource_id; 765 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + 766 cid_reg_offset); 767 seccfgr = io_read32(rifsc_base + _RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); 768 privcfgr = io_read32(rifsc_base + _RIFSC_RISC_PRIVCFGR0 + 0x4 * reg_id); 769 sec_check = (BIT(RIF_SEC_SHIFT) & firewall->args[0]) != 0; 770 priv_check = (BIT(RIF_PRIV_SHIFT) & firewall->args[0]) != 0; 771 cid_to_check = (firewall->args[0] & RIF_SCID_MASK) >> RIF_SCID_SHIFT; 772 773 if (!sec_check && seccfgr & BIT(periph_offset)) 774 return TEE_ERROR_ACCESS_DENIED; 775 776 if (!priv_check && (privcfgr & BIT(periph_offset))) 777 return TEE_ERROR_ACCESS_DENIED; 778 779 if (!(cidcfgr & _CIDCFGR_CFEN)) 780 return TEE_SUCCESS; 781 782 if ((cidcfgr & _CIDCFGR_SEMEN && 783 !stm32_rif_semaphore_enabled_and_ok(cidcfgr, cid_to_check)) || 784 (!(cidcfgr & _CIDCFGR_SEMEN) && 785 !stm32_rif_scid_ok(cidcfgr, RIFSC_RISC_CIDCFGR_SCID_MASK, 786 cid_to_check))) 787 return TEE_ERROR_BAD_PARAMETERS; 788 789 return TEE_SUCCESS; 790 } 791 792 static TEE_Result stm32_rifsc_acquire_access(struct firewall_query *firewall) 793 { 794 uintptr_t rifsc_base = rifsc_pdata.base; 795 unsigned int cid_reg_offset = 0; 796 unsigned int periph_offset = 0; 797 unsigned int resource_id = 0; 798 unsigned int reg_id = 0; 799 uint32_t cidcfgr = 0; 800 uint32_t seccfgr = 0; 801 802 assert(rifsc_base); 803 804 if (!firewall || !firewall->arg_count) 805 return TEE_ERROR_BAD_PARAMETERS; 806 807 /* 808 * Peripheral configuration, we assume the configuration is as 809 * follows: 810 * firewall->args[0]: Firewall ID of the resource to acquire 811 */ 812 resource_id = firewall->args[0] & RIF_PER_ID_MASK; 813 if (resource_id >= RIMU_ID_OFFSET) 814 return TEE_SUCCESS; 815 816 reg_id = resource_id / _PERIPH_IDS_PER_REG; 817 periph_offset = resource_id % _PERIPH_IDS_PER_REG; 818 819 cid_reg_offset = _OFFSET_PERX_CIDCFGR * resource_id; 820 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + 821 cid_reg_offset); 822 823 seccfgr = io_read32(rifsc_base + _RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); 824 if (!(seccfgr & BIT(periph_offset))) 825 return TEE_ERROR_ACCESS_DENIED; 826 827 /* Only check CID attributes */ 828 if (!(cidcfgr & _CIDCFGR_CFEN)) 829 return TEE_SUCCESS; 830 831 if (cidcfgr & _CIDCFGR_SEMEN) { 832 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 833 return TEE_ERROR_BAD_PARAMETERS; 834 835 /* Take the semaphore, static CID is irrelevant here */ 836 return stm32_rif_acquire_semaphore(rifsc_base + 837 _RIFSC_RISC_PER0_SEMCR + 838 cid_reg_offset, 839 MAX_CID_SUPPORTED); 840 } 841 842 if (!stm32_rif_scid_ok(cidcfgr, RIFSC_RISC_CIDCFGR_SCID_MASK, RIF_CID1)) 843 return TEE_ERROR_ACCESS_DENIED; 844 845 return TEE_SUCCESS; 846 } 847 848 static TEE_Result stm32_rifsc_set_config(struct firewall_query *firewall) 849 { 850 struct rimu_cfg rimu = { }; 851 unsigned int id = 0; 852 uint32_t conf = 0; 853 854 if (!firewall || firewall->arg_count != 1) 855 return TEE_ERROR_BAD_PARAMETERS; 856 857 /* 858 * Peripheral configuration, we assume the configuration is as 859 * follows: 860 * firewall->args[0]: RIF configuration to set 861 */ 862 id = firewall->args[0] & RIF_PER_ID_MASK; 863 conf = firewall->args[0]; 864 865 if (id < RIMU_ID_OFFSET) { 866 struct risup_cfg risup = { }; 867 uint32_t cidcfgr = 0; 868 869 risup.id = id; 870 risup.sec = (BIT(RIF_SEC_SHIFT) & conf) != 0; 871 risup.priv = (BIT(RIF_PRIV_SHIFT) & conf) != 0; 872 risup.lock = (BIT(RIF_LOCK_SHIFT) & conf) != 0; 873 risup.cid_attr = _RIF_FLD_GET(RIF_PERx_CID, conf); 874 875 if (!rifsc_pdata.is_tdcid) { 876 cidcfgr = io_read32(rifsc_pdata.base + 877 _OFFSET_PERX_CIDCFGR * risup.id + 878 _RIFSC_RISC_PER0_CIDCFGR); 879 880 if (cidcfgr != risup.cid_attr) 881 return TEE_ERROR_BAD_PARAMETERS; 882 } 883 884 DMSG("Setting config for peripheral: %u, %s, %s, cid attr: %#"PRIx32", %s", 885 id, risup.sec ? "Secure" : "Non secure", 886 risup.priv ? "Privileged" : "Non privileged", 887 risup.cid_attr, risup.lock ? "Locked" : "Unlocked"); 888 889 return stm32_risup_cfg(&rifsc_pdata, &risup); 890 } 891 892 if (!rifsc_pdata.is_tdcid) 893 return TEE_ERROR_ACCESS_DENIED; 894 895 rimu.id = _RIF_FLD_GET(RIMUPROT_RIMC_M_ID, conf) - RIMU_ID_OFFSET; 896 rimu.attr = _RIF_FLD_GET(RIMUPROT_RIMC_ATTRx, conf); 897 898 return stm32_rimu_cfg(&rifsc_pdata, &rimu); 899 } 900 901 static void stm32_rifsc_release_access(struct firewall_query *firewall) 902 { 903 uintptr_t rifsc_base = rifsc_pdata.base; 904 uint32_t cidcfgr = 0; 905 uint32_t id = 0; 906 907 assert(rifsc_base && firewall && firewall->arg_count); 908 909 id = firewall->args[0]; 910 911 if (id >= RIMU_ID_OFFSET) 912 return; 913 914 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + 915 _OFFSET_PERX_CIDCFGR * id); 916 917 /* Only thing possible is to release a semaphore taken by OP-TEE CID */ 918 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 919 if (stm32_rif_release_semaphore(rifsc_base + 920 _RIFSC_RISC_PER0_SEMCR + 921 id * _OFFSET_PERX_CIDCFGR, 922 MAX_CID_SUPPORTED)) 923 panic("Could not release the RIF semaphore"); 924 } 925 926 static TEE_Result stm32_rifsc_sem_pm_suspend(void) 927 { 928 unsigned int i = 0; 929 930 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 931 uint32_t semcfgr = io_read32(rifsc_pdata.base + 932 _RIFSC_RISC_PER0_SEMCR + 933 _OFFSET_PERX_CIDCFGR * i); 934 struct risup_cfg *risup = rifsc_pdata.risup + i; 935 936 /* Save semaphores that were taken by the CID1 */ 937 risup->pm_sem = semcfgr & _SEMCR_MUTEX && 938 ((semcfgr & _SEMCR_SEMCID_MASK) >> 939 _SEMCR_SEMCID_SHIFT) == RIF_CID1; 940 941 FMSG("RIF semaphore %s for ID: %"PRIu32, 942 risup->pm_sem ? "SAVED" : "NOT SAVED", risup->id); 943 } 944 945 return TEE_SUCCESS; 946 } 947 948 static TEE_Result stm32_rifsc_sem_pm_resume(void) 949 { 950 TEE_Result res = TEE_ERROR_GENERIC; 951 unsigned int i = 0; 952 953 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 954 struct risup_cfg *risup = rifsc_pdata.risup + i; 955 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 956 uintptr_t offset = sizeof(uint32_t) * 957 (risup->id / _PERIPH_IDS_PER_REG); 958 uintptr_t perih_offset = risup->id % _PERIPH_IDS_PER_REG; 959 uint32_t seccgfr = io_read32(rifsc_pdata.base + 960 _RIFSC_RISC_SECCFGR0 + offset); 961 uint32_t privcgfr = io_read32(rifsc_pdata.base + 962 _RIFSC_RISC_PRIVCFGR0 + offset); 963 uint32_t lockcfgr = io_read32(rifsc_pdata.base + 964 _RIFSC_RISC_RCFGLOCKR0 + offset); 965 966 /* Update RISUPs fields */ 967 risup->cid_attr = io_read32(rifsc_pdata.base + 968 _RIFSC_RISC_PER0_CIDCFGR + 969 cidcfgr_offset); 970 risup->sec = (seccgfr & BIT(perih_offset)) != 0; 971 risup->priv = (privcgfr & BIT(perih_offset)) != 0; 972 risup->lock = (lockcfgr & BIT(perih_offset)) != 0; 973 974 /* Acquire available appropriate semaphores */ 975 if (!stm32_rif_semaphore_enabled_and_ok(risup->cid_attr, 976 RIF_CID1) || 977 !risup->pm_sem) 978 continue; 979 980 res = stm32_rif_acquire_semaphore(rifsc_pdata.base + 981 _RIFSC_RISC_PER0_SEMCR + 982 cidcfgr_offset, 983 MAX_CID_SUPPORTED); 984 if (res) { 985 EMSG("Could not acquire semaphore for resource %"PRIu32, 986 risup->id); 987 return TEE_ERROR_ACCESS_DENIED; 988 } 989 } 990 991 return TEE_SUCCESS; 992 } 993 994 static TEE_Result 995 stm32_rifsc_sem_pm(enum pm_op op, unsigned int pm_hint, 996 const struct pm_callback_handle *pm_handle __unused) 997 { 998 TEE_Result res = TEE_ERROR_GENERIC; 999 1000 if (pm_hint != PM_HINT_CONTEXT_STATE) 1001 return TEE_SUCCESS; 1002 1003 if (op == PM_OP_RESUME) 1004 res = stm32_rifsc_sem_pm_resume(); 1005 else 1006 res = stm32_rifsc_sem_pm_suspend(); 1007 1008 return res; 1009 } 1010 1011 TEE_Result stm32_rifsc_check_tdcid(bool *tdcid_state) 1012 { 1013 if (!rifsc_pdata.base) 1014 return TEE_ERROR_DEFER_DRIVER_INIT; 1015 1016 if (((io_read32(rifsc_pdata.base + _RIFSC_RIMC_CR) & 1017 _RIFSC_RIMC_CR_TDCID_MASK)) == (RIF_CID1 << _CIDCFGR_SCID_SHIFT)) 1018 *tdcid_state = true; 1019 else 1020 *tdcid_state = false; 1021 1022 return TEE_SUCCESS; 1023 } 1024 1025 static const struct firewall_controller_ops firewall_ops = { 1026 .set_conf = stm32_rifsc_set_config, 1027 .check_access = stm32_rifsc_check_access, 1028 .acquire_access = stm32_rifsc_acquire_access, 1029 .release_access = stm32_rifsc_release_access, 1030 }; 1031 1032 /** 1033 * stm32_rifsc_dt_probe_bus() - Add bus device tree subnodes that are accessible 1034 * by OP-TEE and secure to the driver probe list. This is used at boot time 1035 * only, as a sanity check between device tree and firewalls hardware 1036 * configurations to prevent undesired accesses when access to a device is not 1037 * authorized. This function tries to acquire access to every resource entries 1038 * listed in the access-controllers property of each of the subnodes. It panics 1039 * if it fails to do so. When CFG_INSECURE is enabled, platform can bypass this 1040 * access control test for specific devices assigned to non-secure world and 1041 * used by OP-TEE, such as an UART console device. 1042 * 1043 * @fdt: FDT to work on 1044 * @node: RIFSC node 1045 * @ctrl: RIFSC firewall controller reference 1046 */ 1047 static TEE_Result 1048 stm32_rifsc_dt_probe_bus(const void *fdt, int node, 1049 struct firewall_controller *ctrl __maybe_unused) 1050 { 1051 TEE_Result res = TEE_ERROR_GENERIC; 1052 struct firewall_query *fw = NULL; 1053 int subnode = 0; 1054 1055 DMSG("Populating %s firewall bus", ctrl->name); 1056 1057 fdt_for_each_subnode(subnode, fdt, node) { 1058 unsigned int i = 0; 1059 1060 if (fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED) 1061 continue; 1062 1063 if (IS_ENABLED(CFG_INSECURE) && 1064 stm32mp_allow_probe_shared_device(fdt, subnode)) { 1065 DMSG("Skipping firewall attributes check for %s", 1066 fdt_get_name(fdt, subnode, NULL)); 1067 goto skip_check; 1068 } 1069 1070 DMSG("Acquiring firewall access for %s when probing bus", 1071 fdt_get_name(fdt, subnode, NULL)); 1072 1073 do { 1074 /* 1075 * The access-controllers property is mandatory for 1076 * firewall bus devices 1077 */ 1078 res = firewall_dt_get_by_index(fdt, subnode, i, &fw); 1079 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 1080 /* Stop when nothing more to parse */ 1081 break; 1082 } else if (res) { 1083 EMSG("%s: Error on node %s: %#"PRIx32, 1084 ctrl->name, 1085 fdt_get_name(fdt, subnode, NULL), res); 1086 panic(); 1087 } 1088 1089 res = firewall_acquire_access(fw); 1090 if (res) { 1091 EMSG("%s: %s not accessible: %#"PRIx32, 1092 ctrl->name, 1093 fdt_get_name(fdt, subnode, NULL), res); 1094 panic(); 1095 } 1096 1097 firewall_put(fw); 1098 i++; 1099 } while (true); 1100 1101 skip_check: 1102 res = dt_driver_maybe_add_probe_node(fdt, subnode); 1103 if (res) { 1104 EMSG("Failed on node %s with %#"PRIx32, 1105 fdt_get_name(fdt, subnode, NULL), res); 1106 panic(); 1107 } 1108 } 1109 1110 return TEE_SUCCESS; 1111 } 1112 1113 static TEE_Result stm32_rifsc_probe(const void *fdt, int node, 1114 const void *compat_data __unused) 1115 { 1116 struct firewall_controller *controller = NULL; 1117 TEE_Result res = TEE_ERROR_GENERIC; 1118 1119 res = stm32_rifsc_parse_fdt(fdt, node, &rifsc_pdata); 1120 if (res) { 1121 EMSG("Could not parse RIFSC node, res = %#"PRIx32, res); 1122 panic(); 1123 } 1124 1125 if (!rifsc_pdata.drv_data) 1126 stm32_rifsc_get_driverdata(&rifsc_pdata); 1127 1128 res = stm32_risup_setup(&rifsc_pdata); 1129 if (res) { 1130 EMSG("Could not setup RISUPs, res = %#"PRIx32, res); 1131 panic(); 1132 } 1133 1134 if (rifsc_pdata.is_tdcid) { 1135 res = stm32_rimu_setup(&rifsc_pdata); 1136 if (res) { 1137 EMSG("Could not setup RIMUs, res = %#"PRIx32, res); 1138 panic(); 1139 } 1140 1141 #if defined(CFG_STM32MP25) 1142 res = stm32_risal_setup(&rifsc_pdata); 1143 if (res) 1144 panic(); 1145 #endif /* CFG_STM32MP25 */ 1146 } 1147 1148 res = stm32_rifsc_glock_config(fdt, node, &rifsc_pdata); 1149 if (res) 1150 panic("Couldn't lock RIFSC configuration"); 1151 1152 controller = calloc(1, sizeof(*controller)); 1153 if (!controller) 1154 panic(); 1155 1156 controller->name = "RIFSC"; 1157 controller->priv = &rifsc_pdata; 1158 controller->ops = &firewall_ops; 1159 1160 res = firewall_dt_controller_register(fdt, node, controller); 1161 if (res) 1162 panic(); 1163 1164 res = stm32_rifsc_dt_probe_bus(fdt, node, controller); 1165 if (res) 1166 panic(); 1167 1168 register_pm_core_service_cb(stm32_rifsc_sem_pm, NULL, 1169 "stm32-rifsc-semaphores"); 1170 1171 return TEE_SUCCESS; 1172 } 1173 1174 static const struct dt_device_match rifsc_match_table[] = { 1175 { .compatible = "st,stm32mp25-rifsc" }, 1176 { } 1177 }; 1178 1179 DEFINE_DT_DRIVER(rifsc_dt_driver) = { 1180 .name = "stm32-rifsc", 1181 .match_table = rifsc_match_table, 1182 .probe = stm32_rifsc_probe, 1183 }; 1184