1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <drivers/stm32_rif.h> 7 #include <drivers/stm32mp_dt_bindings.h> 8 #include <dt-bindings/firewall/stm32mp25-rif.h> 9 #include <io.h> 10 #include <kernel/boot.h> 11 #include <kernel/dt.h> 12 #include <kernel/dt_driver.h> 13 #include <kernel/panic.h> 14 #include <kernel/pm.h> 15 #include <libfdt.h> 16 #include <mm/core_memprot.h> 17 #include <tee_api_defines.h> 18 #include <trace.h> 19 #include <util.h> 20 21 /* RIFSC offset register */ 22 #define _RIFSC_RISC_SECCFGR0 U(0x10) 23 #define _RIFSC_RISC_PRIVCFGR0 U(0x30) 24 #define _RIFSC_RISC_RCFGLOCKR0 U(0x50) 25 #define _RIFSC_RISC_PER0_CIDCFGR U(0x100) 26 #define _RIFSC_RISC_PER0_SEMCR U(0x104) 27 #define _RIFSC_RIMC_CR U(0xC00) 28 #define _RIFSC_RIMC_ATTR0 U(0xC10) 29 30 #define _RIFSC_HWCFGR3 U(0xFE8) 31 #define _RIFSC_HWCFGR2 U(0xFEC) 32 #define _RIFSC_HWCFGR1 U(0xFF0) 33 #define _RIFSC_VERR U(0xFF4) 34 35 /* RIFSC_HWCFGR2 register fields */ 36 #define _RIFSC_HWCFGR2_CFG1_MASK GENMASK_32(15, 0) 37 #define _RIFSC_HWCFGR2_CFG1_SHIFT U(0) 38 #define _RIFSC_HWCFGR2_CFG2_MASK GENMASK_32(23, 16) 39 #define _RIFSC_HWCFGR2_CFG2_SHIFT U(16) 40 #define _RIFSC_HWCFGR2_CFG3_MASK GENMASK_32(31, 24) 41 #define _RIFSC_HWCFGR2_CFG3_SHIFT U(24) 42 43 /* RIFSC_HWCFGR1 register fields */ 44 #define _RIFSC_HWCFGR1_CFG1_MASK GENMASK_32(3, 0) 45 #define _RIFSC_HWCFGR1_CFG1_SHIFT U(0) 46 #define _RIFSC_HWCFGR1_CFG2_MASK GENMASK_32(7, 4) 47 #define _RIFSC_HWCFGR1_CFG2_SHIFT U(4) 48 #define _RIFSC_HWCFGR1_CFG3_MASK GENMASK_32(11, 8) 49 #define _RIFSC_HWCFGR1_CFG3_SHIFT U(8) 50 #define _RIFSC_HWCFGR1_CFG4_MASK GENMASK_32(15, 12) 51 #define _RIFSC_HWCFGR1_CFG4_SHIFT U(12) 52 #define _RIFSC_HWCFGR1_CFG5_MASK GENMASK_32(19, 16) 53 #define _RIFSC_HWCFGR1_CFG5_SHIFT U(16) 54 #define _RIFSC_HWCFGR1_CFG6_MASK GENMASK_32(23, 20) 55 #define _RIFSC_HWCFGR1_CFG6_SHIFT U(20) 56 57 /* 58 * RISC_CR register fields 59 */ 60 #define _RIFSC_RISC_CR_GLOCK BIT(0) 61 62 /* 63 * RIMC_CR register fields 64 */ 65 #define _RIFSC_RIMC_CR_GLOCK BIT(0) 66 #define _RIFSC_RIMC_CR_TDCID_MASK GENMASK_32(6, 4) 67 68 /* RIFSC_VERR register fields */ 69 #define _RIFSC_VERR_MINREV_MASK GENMASK_32(3, 0) 70 #define _RIFSC_VERR_MINREV_SHIFT U(0) 71 #define _RIFSC_VERR_MAJREV_MASK GENMASK_32(7, 4) 72 #define _RIFSC_VERR_MAJREV_SHIFT U(4) 73 74 /* Periph id per register */ 75 #define _PERIPH_IDS_PER_REG U(32) 76 #define _OFFSET_PERX_CIDCFGR U(0x8) 77 78 #define RIFSC_RISC_CFEN_MASK BIT(0) 79 #define RIFSC_RISC_SEM_EN_MASK BIT(1) 80 #define RIFSC_RISC_SCID_MASK GENMASK_32(6, 4) 81 #define RIFSC_RISC_SEC_MASK BIT(8) 82 #define RIFSC_RISC_PRIV_MASK BIT(9) 83 #define RIFSC_RISC_LOCK_MASK BIT(10) 84 #define RIFSC_RISC_SEML_MASK GENMASK_32(23, 16) 85 #define RIFSC_RISC_PER_ID_MASK GENMASK_32(31, 24) 86 87 #define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \ 88 RIFSC_RISC_SEM_EN_MASK | \ 89 RIFSC_RISC_SCID_MASK | \ 90 RIFSC_RISC_SEML_MASK) 91 92 #define RIFSC_RIMC_MODE_MASK BIT(2) 93 #define RIFSC_RIMC_MCID_MASK GENMASK_32(6, 4) 94 #define RIFSC_RIMC_MSEC_MASK BIT(8) 95 #define RIFSC_RIMC_MPRIV_MASK BIT(9) 96 #define RIFSC_RIMC_M_ID_MASK GENMASK_32(23, 16) 97 98 #define RIFSC_RIMC_ATTRx_MASK (RIFSC_RIMC_MODE_MASK | \ 99 RIFSC_RIMC_MCID_MASK | \ 100 RIFSC_RIMC_MSEC_MASK | \ 101 RIFSC_RIMC_MPRIV_MASK) 102 103 /* max entries */ 104 #define MAX_RIMU U(16) 105 #define MAX_RISUP U(128) 106 107 #define _RIF_FLD_GET(field, value) (((uint32_t)(value) & \ 108 (field ## _MASK)) >>\ 109 (field ## _SHIFT)) 110 111 struct risup_cfg { 112 uint32_t cid_attr; 113 uint32_t id; 114 bool sec; 115 bool priv; 116 bool lock; 117 bool pm_sem; 118 }; 119 120 struct rimu_cfg { 121 uint32_t id; 122 uint32_t attr; 123 }; 124 125 struct rifsc_driver_data { 126 bool rif_en; 127 bool sec_en; 128 bool priv_en; 129 uint8_t nb_rimu; 130 uint8_t nb_risup; 131 uint8_t nb_risal; 132 uint8_t version; 133 }; 134 135 struct rifsc_platdata { 136 uintptr_t base; 137 struct rifsc_driver_data *drv_data; 138 struct risup_cfg *risup; 139 unsigned int nrisup; 140 struct rimu_cfg *rimu; 141 unsigned int nrimu; 142 }; 143 144 /* There is only 1 instance of the RIFSC subsystem */ 145 static struct rifsc_driver_data rifsc_drvdata; 146 static struct rifsc_platdata rifsc_pdata; 147 148 static void stm32_rifsc_get_driverdata(struct rifsc_platdata *pdata) 149 { 150 uint32_t regval = 0; 151 152 regval = io_read32(pdata->base + _RIFSC_HWCFGR1); 153 rifsc_drvdata.rif_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG1, regval) != 0; 154 rifsc_drvdata.sec_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG2, regval) != 0; 155 rifsc_drvdata.priv_en = _RIF_FLD_GET(_RIFSC_HWCFGR1_CFG3, regval) != 0; 156 157 regval = io_read32(pdata->base + _RIFSC_HWCFGR2); 158 rifsc_drvdata.nb_risup = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG1, regval); 159 rifsc_drvdata.nb_rimu = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG2, regval); 160 rifsc_drvdata.nb_risal = _RIF_FLD_GET(_RIFSC_HWCFGR2_CFG3, regval); 161 162 pdata->drv_data = &rifsc_drvdata; 163 164 rifsc_drvdata.version = io_read8(pdata->base + _RIFSC_VERR); 165 166 DMSG("RIFSC version %"PRIu32".%"PRIu32, 167 _RIF_FLD_GET(_RIFSC_VERR_MAJREV, rifsc_drvdata.version), 168 _RIF_FLD_GET(_RIFSC_VERR_MINREV, rifsc_drvdata.version)); 169 170 DMSG("HW cap: enabled[rif:sec:priv]:[%s:%s:%s] nb[risup|rimu|risal]:[%"PRIu8",%"PRIu8",%"PRIu8"]", 171 rifsc_drvdata.rif_en ? "true" : "false", 172 rifsc_drvdata.sec_en ? "true" : "false", 173 rifsc_drvdata.priv_en ? "true" : "false", 174 rifsc_drvdata.nb_risup, 175 rifsc_drvdata.nb_rimu, 176 rifsc_drvdata.nb_risal); 177 } 178 179 static TEE_Result stm32_rifsc_glock_config(const void *fdt, int node, 180 struct rifsc_platdata *pdata) 181 { 182 const fdt32_t *cuint = NULL; 183 uint32_t glock_conf = 0; 184 int len = 0; 185 186 cuint = fdt_getprop(fdt, node, "st,glocked", &len); 187 if (!cuint) { 188 DMSG("No global lock on RIF configuration"); 189 return TEE_SUCCESS; 190 } 191 assert(len == sizeof(uint32_t)); 192 193 glock_conf = fdt32_to_cpu(*cuint); 194 195 if (glock_conf & RIFSC_RIMU_GLOCK) { 196 DMSG("Setting global lock on RIMU configuration"); 197 198 io_setbits32(pdata->base + _RIFSC_RIMC_CR, 199 _RIFSC_RIMC_CR_GLOCK); 200 201 if (!(io_read32(pdata->base + _RIFSC_RIMC_CR) & 202 _RIFSC_RIMC_CR_GLOCK)) 203 return TEE_ERROR_ACCESS_DENIED; 204 } 205 206 if (glock_conf & RIFSC_RISUP_GLOCK) { 207 DMSG("Setting global lock on RISUP configuration"); 208 209 io_setbits32(pdata->base, _RIFSC_RISC_CR_GLOCK); 210 211 if (!(io_read32(pdata->base) & _RIFSC_RISC_CR_GLOCK)) 212 return TEE_ERROR_ACCESS_DENIED; 213 } 214 215 return TEE_SUCCESS; 216 } 217 218 static TEE_Result stm32_rifsc_dt_conf_risup(const void *fdt, int node, 219 struct rifsc_platdata *pdata) 220 { 221 const fdt32_t *conf_list = NULL; 222 unsigned int i = 0; 223 int len = 0; 224 225 conf_list = fdt_getprop(fdt, node, "st,protreg", &len); 226 if (!conf_list) { 227 DMSG("No RISUP configuration in DT"); 228 return TEE_ERROR_ITEM_NOT_FOUND; 229 } 230 assert(!(len % sizeof(uint32_t))); 231 232 pdata->nrisup = len / sizeof(uint32_t); 233 pdata->risup = calloc(pdata->nrisup, sizeof(*pdata->risup)); 234 if (!pdata->risup) 235 return TEE_ERROR_OUT_OF_MEMORY; 236 237 for (i = 0; i < pdata->nrisup; i++) { 238 uint32_t value = fdt32_to_cpu(conf_list[i]); 239 struct risup_cfg *risup = pdata->risup + i; 240 241 risup->id = _RIF_FLD_GET(RIFSC_RISC_PER_ID, value); 242 risup->sec = _RIF_FLD_GET(RIFSC_RISC_SEC, value) != 0; 243 risup->priv = _RIF_FLD_GET(RIFSC_RISC_PRIV, value) != 0; 244 risup->lock = _RIF_FLD_GET(RIFSC_RISC_LOCK, value) != 0; 245 risup->cid_attr = _RIF_FLD_GET(RIFSC_RISC_PERx_CID, value); 246 } 247 248 return TEE_SUCCESS; 249 } 250 251 static TEE_Result stm32_rifsc_dt_conf_rimu(const void *fdt, int node, 252 struct rifsc_platdata *pdata) 253 { 254 const fdt32_t *conf_list = NULL; 255 unsigned int i = 0; 256 int len = 0; 257 258 conf_list = fdt_getprop(fdt, node, "st,rimu", &len); 259 if (!conf_list) { 260 DMSG("No RIMU configuration in DT"); 261 return TEE_ERROR_ITEM_NOT_FOUND; 262 } 263 assert(!(len % sizeof(uint32_t))); 264 265 pdata->nrimu = len / sizeof(uint32_t); 266 pdata->rimu = calloc(pdata->nrimu, sizeof(*pdata->rimu)); 267 if (!pdata->rimu) 268 return TEE_ERROR_OUT_OF_MEMORY; 269 270 for (i = 0; i < pdata->nrimu; i++) { 271 uint32_t value = fdt32_to_cpu(*conf_list); 272 struct rimu_cfg *rimu = pdata->rimu + i; 273 274 rimu->id = _RIF_FLD_GET(RIFSC_RIMC_M_ID, value); 275 rimu->attr = _RIF_FLD_GET(RIFSC_RIMC_ATTRx, value); 276 } 277 278 return TEE_SUCCESS; 279 } 280 281 static TEE_Result stm32_rifsc_parse_fdt(const void *fdt, int node, 282 struct rifsc_platdata *pdata) 283 { 284 TEE_Result res = TEE_ERROR_GENERIC; 285 struct io_pa_va base = { }; 286 size_t reg_size = 0; 287 288 base.pa = fdt_reg_base_address(fdt, node); 289 if (base.pa == DT_INFO_INVALID_REG) 290 return TEE_ERROR_BAD_PARAMETERS; 291 292 reg_size = fdt_reg_size(fdt, node); 293 if (reg_size == DT_INFO_INVALID_REG_SIZE) 294 return TEE_ERROR_BAD_PARAMETERS; 295 296 pdata->base = io_pa_or_va_secure(&base, reg_size); 297 298 res = stm32_rifsc_dt_conf_risup(fdt, node, pdata); 299 if (res) 300 return res; 301 302 return stm32_rifsc_dt_conf_rimu(fdt, node, pdata); 303 } 304 305 static TEE_Result stm32_risup_cfg(struct rifsc_platdata *pdata, 306 struct risup_cfg *risup) 307 { 308 uintptr_t offset = sizeof(uint32_t) * (risup->id / _PERIPH_IDS_PER_REG); 309 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 310 struct rifsc_driver_data *drv_data = pdata->drv_data; 311 uint32_t shift = risup->id % _PERIPH_IDS_PER_REG; 312 TEE_Result res = TEE_ERROR_GENERIC; 313 314 if (!risup || risup->id >= drv_data->nb_risup) 315 return TEE_ERROR_BAD_PARAMETERS; 316 317 if (drv_data->sec_en) 318 io_clrsetbits32(pdata->base + _RIFSC_RISC_SECCFGR0 + offset, 319 BIT(shift), SHIFT_U32(risup->sec, shift)); 320 321 if (drv_data->priv_en) 322 io_clrsetbits32(pdata->base + _RIFSC_RISC_PRIVCFGR0 + offset, 323 BIT(shift), SHIFT_U32(risup->priv, shift)); 324 325 if (drv_data->rif_en) 326 io_write32(pdata->base + _RIFSC_RISC_PER0_CIDCFGR + 327 cidcfgr_offset, risup->cid_attr); 328 329 /* Lock configuration for this RISUP */ 330 if (risup->lock) { 331 DMSG("Locking RIF conf for peripheral %"PRIu32, risup->id); 332 io_setbits32(pdata->base + _RIFSC_RISC_RCFGLOCKR0 + offset, 333 BIT(shift)); 334 } 335 336 /* Take semaphore if the resource is in semaphore mode and secured */ 337 if (!stm32_rif_semaphore_enabled_and_ok(risup->cid_attr, RIF_CID1) || 338 !(io_read32(pdata->base + _RIFSC_RISC_SECCFGR0 + offset) & 339 BIT(shift))) { 340 res = stm32_rif_release_semaphore(pdata->base + 341 _RIFSC_RISC_PER0_SEMCR + 342 cidcfgr_offset, 343 MAX_CID_SUPPORTED); 344 if (res) { 345 EMSG("Couldn't release semaphore for resource %"PRIu32, 346 risup->id); 347 return TEE_ERROR_ACCESS_DENIED; 348 } 349 } else { 350 res = stm32_rif_acquire_semaphore(pdata->base + 351 _RIFSC_RISC_PER0_SEMCR + 352 cidcfgr_offset, 353 MAX_CID_SUPPORTED); 354 if (res) { 355 EMSG("Couldn't acquire semaphore for resource %"PRIu32, 356 risup->id); 357 return TEE_ERROR_ACCESS_DENIED; 358 } 359 } 360 361 return TEE_SUCCESS; 362 } 363 364 static TEE_Result stm32_risup_setup(struct rifsc_platdata *pdata) 365 { 366 struct rifsc_driver_data *drv_data = pdata->drv_data; 367 TEE_Result res = TEE_ERROR_GENERIC; 368 unsigned int i = 0; 369 370 for (i = 0; i < pdata->nrisup && i < drv_data->nb_risup; i++) { 371 struct risup_cfg *risup = pdata->risup + i; 372 373 res = stm32_risup_cfg(pdata, risup); 374 if (res) { 375 EMSG("risup cfg(%d/%d) error", i + 1, pdata->nrisup); 376 return res; 377 } 378 } 379 380 return TEE_SUCCESS; 381 } 382 383 static TEE_Result stm32_rimu_cfg(struct rifsc_platdata *pdata, 384 struct rimu_cfg *rimu) 385 { 386 uintptr_t offset = _RIFSC_RIMC_ATTR0 + (sizeof(uint32_t) * rimu->id); 387 struct rifsc_driver_data *drv_data = pdata->drv_data; 388 389 if (!rimu || rimu->id >= drv_data->nb_rimu) 390 return TEE_ERROR_BAD_PARAMETERS; 391 392 if (drv_data->rif_en) 393 io_write32(pdata->base + offset, rimu->attr); 394 395 return TEE_SUCCESS; 396 } 397 398 static TEE_Result stm32_rimu_setup(struct rifsc_platdata *pdata) 399 { 400 struct rifsc_driver_data *drv_data = pdata->drv_data; 401 TEE_Result res = TEE_ERROR_GENERIC; 402 unsigned int i = 0; 403 404 for (i = 0; i < pdata->nrimu && i < drv_data->nb_rimu; i++) { 405 struct rimu_cfg *rimu = pdata->rimu + i; 406 407 res = stm32_rimu_cfg(pdata, rimu); 408 if (res) { 409 EMSG("rimu cfg(%d/%d) error", i + 1, pdata->nrimu); 410 return res; 411 } 412 } 413 414 return TEE_SUCCESS; 415 } 416 417 static TEE_Result stm32_rifsc_sem_pm_suspend(void) 418 { 419 unsigned int i = 0; 420 421 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 422 uint32_t semcfgr = io_read32(rifsc_pdata.base + 423 _RIFSC_RISC_PER0_SEMCR + 424 _OFFSET_PERX_CIDCFGR * i); 425 struct risup_cfg *risup = rifsc_pdata.risup + i; 426 427 /* Save semaphores that were taken by the CID1 */ 428 risup->pm_sem = semcfgr & _SEMCR_MUTEX && 429 ((semcfgr & _SEMCR_SEMCID_MASK) >> 430 _SEMCR_SEMCID_SHIFT) == RIF_CID1; 431 432 FMSG("RIF semaphore %s for ID: %"PRIu32, 433 risup->pm_sem ? "SAVED" : "NOT SAVED", risup->id); 434 } 435 436 return TEE_SUCCESS; 437 } 438 439 static TEE_Result stm32_rifsc_sem_pm_resume(void) 440 { 441 TEE_Result res = TEE_ERROR_GENERIC; 442 unsigned int i = 0; 443 444 for (i = 0; i < rifsc_pdata.nrisup && i < rifsc_drvdata.nb_risup; i++) { 445 struct risup_cfg *risup = rifsc_pdata.risup + i; 446 uintptr_t cidcfgr_offset = _OFFSET_PERX_CIDCFGR * risup->id; 447 uintptr_t offset = sizeof(uint32_t) * 448 (risup->id / _PERIPH_IDS_PER_REG); 449 uintptr_t perih_offset = risup->id % _PERIPH_IDS_PER_REG; 450 uint32_t seccgfr = io_read32(rifsc_pdata.base + 451 _RIFSC_RISC_SECCFGR0 + offset); 452 uint32_t privcgfr = io_read32(rifsc_pdata.base + 453 _RIFSC_RISC_PRIVCFGR0 + offset); 454 uint32_t lockcfgr = io_read32(rifsc_pdata.base + 455 _RIFSC_RISC_RCFGLOCKR0 + offset); 456 457 /* Update RISUPs fields */ 458 risup->cid_attr = io_read32(rifsc_pdata.base + 459 _RIFSC_RISC_PER0_CIDCFGR + 460 cidcfgr_offset); 461 risup->sec = (seccgfr & BIT(perih_offset)) != 0; 462 risup->priv = (privcgfr & BIT(perih_offset)) != 0; 463 risup->lock = (lockcfgr & BIT(perih_offset)) != 0; 464 465 /* Acquire available appropriate semaphores */ 466 if (!stm32_rif_semaphore_enabled_and_ok(risup->cid_attr, 467 RIF_CID1) || 468 !risup->pm_sem) 469 continue; 470 471 res = stm32_rif_acquire_semaphore(rifsc_pdata.base + 472 _RIFSC_RISC_PER0_SEMCR + 473 cidcfgr_offset, 474 MAX_CID_SUPPORTED); 475 if (res) { 476 EMSG("Could not acquire semaphore for resource %"PRIu32, 477 risup->id); 478 return TEE_ERROR_ACCESS_DENIED; 479 } 480 } 481 482 return TEE_SUCCESS; 483 } 484 485 static TEE_Result 486 stm32_rifsc_sem_pm(enum pm_op op, unsigned int pm_hint, 487 const struct pm_callback_handle *pm_handle __unused) 488 { 489 TEE_Result res = TEE_ERROR_GENERIC; 490 491 if (pm_hint != PM_HINT_CONTEXT_STATE) 492 return TEE_SUCCESS; 493 494 if (op == PM_OP_RESUME) 495 res = stm32_rifsc_sem_pm_resume(); 496 else 497 res = stm32_rifsc_sem_pm_suspend(); 498 499 return res; 500 } 501 502 TEE_Result stm32_rifsc_check_tdcid(bool *tdcid_state) 503 { 504 if (!rifsc_pdata.base) 505 return TEE_ERROR_DEFER_DRIVER_INIT; 506 507 if (((io_read32(rifsc_pdata.base + _RIFSC_RIMC_CR) & 508 _RIFSC_RIMC_CR_TDCID_MASK)) == (RIF_CID1 << SCID_SHIFT)) 509 *tdcid_state = true; 510 else 511 *tdcid_state = false; 512 513 return TEE_SUCCESS; 514 } 515 516 static TEE_Result stm32_rifsc_probe(const void *fdt, int node, 517 const void *compat_data __unused) 518 { 519 TEE_Result res = TEE_ERROR_GENERIC; 520 521 res = stm32_rifsc_parse_fdt(fdt, node, &rifsc_pdata); 522 if (res) { 523 EMSG("Could not parse RIFSC node, res = %#"PRIx32, res); 524 panic(); 525 } 526 527 if (!rifsc_pdata.drv_data) 528 stm32_rifsc_get_driverdata(&rifsc_pdata); 529 530 res = stm32_risup_setup(&rifsc_pdata); 531 if (res) { 532 EMSG("Could not setup RISUPs, res = %#"PRIx32, res); 533 panic(); 534 } 535 536 res = stm32_rimu_setup(&rifsc_pdata); 537 if (res) { 538 EMSG("Could not setup RIMUs, res = %#"PRIx32, res); 539 panic(); 540 } 541 542 res = stm32_rifsc_glock_config(fdt, node, &rifsc_pdata); 543 if (res) 544 panic("Couldn't lock RIFSC configuration"); 545 546 if (IS_ENABLED(CFG_PM)) 547 register_pm_core_service_cb(stm32_rifsc_sem_pm, NULL, 548 "stm32-rifsc-semaphores"); 549 550 return TEE_SUCCESS; 551 } 552 553 static const struct dt_device_match rifsc_match_table[] = { 554 { .compatible = "st,stm32mp25-rifsc" }, 555 { } 556 }; 557 558 DEFINE_DT_DRIVER(rifsc_dt_driver) = { 559 .name = "stm32-rifsc", 560 .match_table = rifsc_match_table, 561 .probe = stm32_rifsc_probe, 562 }; 563