1*b6a44cc5Sleisen /* SPDX-License-Identifier: BSD-2-Clause */ 2*b6a44cc5Sleisen /* 3*b6a44cc5Sleisen * Copyright (c) 2024 HiSilicon Limited. 4*b6a44cc5Sleisen */ 5*b6a44cc5Sleisen #ifndef _HPRE_MAIN_H 6*b6a44cc5Sleisen #define _HPRE_MAIN_H 7*b6a44cc5Sleisen 8*b6a44cc5Sleisen #include "hisi_qm.h" 9*b6a44cc5Sleisen 10*b6a44cc5Sleisen #define HPRE_BAR_BASE 0x150000000 11*b6a44cc5Sleisen #define HPRE_BAR_SIZE 0x400000 12*b6a44cc5Sleisen #define HPRE_SQE_SIZE 64 13*b6a44cc5Sleisen #define HPRE_SQE_LOG2_SIZE 6 14*b6a44cc5Sleisen #define HPRE_SQE_SM2_KSEL_SHIFT 1 15*b6a44cc5Sleisen #define HPRE_SQE_BD_RSV2_SHIFT 7 16*b6a44cc5Sleisen #define HPRE_HW_TASK_INIT 0x1 17*b6a44cc5Sleisen #define HPRE_HW_TASK_DONE 0x3 18*b6a44cc5Sleisen #define TASK_LENGTH(len) ((len) / 8 - 1) 19*b6a44cc5Sleisen #define BITS_TO_BYTES(len) (((len) + 7) / 8) 20*b6a44cc5Sleisen #define BYTES_TO_BITS(len) ((len) * 8) 21*b6a44cc5Sleisen 22*b6a44cc5Sleisen #define HPRE_ETYPE_SHIFT 5 23*b6a44cc5Sleisen #define HPRE_ETYPE_MASK 0x7ff 24*b6a44cc5Sleisen #define HPRE_ETYPE1_SHIFT 16 25*b6a44cc5Sleisen #define HPRE_ETYPE1_MASK 0x3fff 26*b6a44cc5Sleisen #define HPRE_DONE_SHIFT 30 27*b6a44cc5Sleisen #define HPRE_DONE_MASK 0x3 28*b6a44cc5Sleisen #define HPRE_TASK_ETYPE(w0) (((w0) >> HPRE_ETYPE_SHIFT) & HPRE_ETYPE_MASK) 29*b6a44cc5Sleisen #define HPRE_TASK_ETYPE1(w0) (((w0) >> HPRE_ETYPE1_SHIFT) & HPRE_ETYPE1_MASK) 30*b6a44cc5Sleisen #define HPRE_TASK_DONE(w0) (((w0) >> HPRE_DONE_SHIFT) & HPRE_DONE_MASK) 31*b6a44cc5Sleisen 32*b6a44cc5Sleisen struct hpre_sqe { 33*b6a44cc5Sleisen /* 34*b6a44cc5Sleisen * alg : 5 35*b6a44cc5Sleisen * etype : 11 36*b6a44cc5Sleisen * etype1 : 14 37*b6a44cc5Sleisen * done : 2 38*b6a44cc5Sleisen */ 39*b6a44cc5Sleisen uint32_t w0; 40*b6a44cc5Sleisen 41*b6a44cc5Sleisen uint8_t task_len1; 42*b6a44cc5Sleisen uint8_t task_len2; 43*b6a44cc5Sleisen uint8_t mrttest_num; 44*b6a44cc5Sleisen /* 45*b6a44cc5Sleisen * uwkey_enb : 1 46*b6a44cc5Sleisen * sm2_ksel : 1 47*b6a44cc5Sleisen * sva_bypass : 1 48*b6a44cc5Sleisen * sva_status : 4 49*b6a44cc5Sleisen * bd_rsv2 : 1 50*b6a44cc5Sleisen */ 51*b6a44cc5Sleisen uint8_t ext1; 52*b6a44cc5Sleisen 53*b6a44cc5Sleisen uint64_t key; 54*b6a44cc5Sleisen uint64_t in; 55*b6a44cc5Sleisen uint64_t out; 56*b6a44cc5Sleisen uint64_t tag; 57*b6a44cc5Sleisen 58*b6a44cc5Sleisen uint16_t sm2enc_klen; 59*b6a44cc5Sleisen /* 60*b6a44cc5Sleisen * uwkey_sel : 4 61*b6a44cc5Sleisen * uwkey_wrap_num : 3 62*b6a44cc5Sleisen * rsvd2 : 9 63*b6a44cc5Sleisen */ 64*b6a44cc5Sleisen uint16_t ext2; 65*b6a44cc5Sleisen 66*b6a44cc5Sleisen uint64_t kek_key; 67*b6a44cc5Sleisen uint32_t rsv[3]; 68*b6a44cc5Sleisen }; 69*b6a44cc5Sleisen 70*b6a44cc5Sleisen enum hpre_alg_type { 71*b6a44cc5Sleisen HPRE_ALG_NC_NCRT = 0x0, 72*b6a44cc5Sleisen HPRE_ALG_NC_CRT = 0x1, 73*b6a44cc5Sleisen HPRE_ALG_KG_STD = 0x2, 74*b6a44cc5Sleisen HPRE_ALG_KG_CRT = 0x3, 75*b6a44cc5Sleisen HPRE_ALG_DH_G2 = 0x4, 76*b6a44cc5Sleisen HPRE_ALG_DH = 0x5, 77*b6a44cc5Sleisen HPRE_ALG_ECDH_MULTIPLY = 0xD, 78*b6a44cc5Sleisen HPRE_ALG_ECDSA_SIGN = 0xE, 79*b6a44cc5Sleisen HPRE_ALG_ECDSA_VERF = 0xF, 80*b6a44cc5Sleisen HPRE_ALG_X_DH_MULTIPLY = 0x10, 81*b6a44cc5Sleisen HPRE_ALG_SM2_KEY_GEN = 0x11, 82*b6a44cc5Sleisen HPRE_ALG_SM2_SIGN = 0x12, 83*b6a44cc5Sleisen HPRE_ALG_SM2_VERF = 0x13, 84*b6a44cc5Sleisen HPRE_ALG_SM2_ENC = 0x14, 85*b6a44cc5Sleisen HPRE_ALG_SM2_DEC = 0x15 86*b6a44cc5Sleisen }; 87*b6a44cc5Sleisen 88*b6a44cc5Sleisen uint32_t hpre_init(void); 89*b6a44cc5Sleisen struct hisi_qp *hpre_create_qp(uint8_t sq_type); 90*b6a44cc5Sleisen enum hisi_drv_status hpre_bin_from_crypto_bin(uint8_t *dst, const uint8_t *src, 91*b6a44cc5Sleisen uint32_t bsize, uint32_t dsize); 92*b6a44cc5Sleisen enum hisi_drv_status hpre_bin_to_crypto_bin(uint8_t *dst, const uint8_t *src, 93*b6a44cc5Sleisen uint32_t bsize, uint32_t dsize); 94*b6a44cc5Sleisen 95*b6a44cc5Sleisen #endif 96