164d3c0c2SOlivier Masseifeq ($(CFG_NXP_CAAM),y) 264d3c0c2SOlivier Masse# CAAM Debug: define 3x32 bits value (same bit used to debug a module) 364d3c0c2SOlivier Masse# CFG_DBG_CAAM_TRACE Module print trace 464d3c0c2SOlivier Masse# CFG_DBG_CAAM_DESC Module descriptor dump 564d3c0c2SOlivier Masse# CFG_DBG_CAAM_BUF Module buffer dump 664d3c0c2SOlivier Masse# 764d3c0c2SOlivier Masse# DBG_HAL BIT32(0) // HAL trace 864d3c0c2SOlivier Masse# DBG_CTRL BIT32(1) // Controller trace 964d3c0c2SOlivier Masse# DBG_MEM BIT32(2) // Memory utility trace 1064d3c0c2SOlivier Masse# DBG_SGT BIT32(3) // Scatter Gather trace 1164d3c0c2SOlivier Masse# DBG_PWR BIT32(4) // Power trace 1264d3c0c2SOlivier Masse# DBG_JR BIT32(5) // Job Ring trace 1364d3c0c2SOlivier Masse# DBG_RNG BIT32(6) // RNG trace 1464d3c0c2SOlivier Masse# DBG_HASH BIT32(7) // Hash trace 1564d3c0c2SOlivier Masse# DBG_RSA BIT32(8) // RSA trace 1664d3c0c2SOlivier Masse# DBG_CIPHER BIT32(9) // Cipher trace 1764d3c0c2SOlivier Masse# DBG_BLOB BIT32(10) // BLOB trace 1864d3c0c2SOlivier Masse# DBG_DMAOBJ BIT32(11) // DMA Object Trace 1964d3c0c2SOlivier Masse# DBG_ECC BIT32(12) // ECC trace 2064d3c0c2SOlivier Masse# DBG_DH BIT32(13) // DH Trace 2164d3c0c2SOlivier Masse# DBG_DSA BIT32(14) // DSA trace 22d538d293SClement Faure# DBG_MP BIT32(15) // MP trace 23faaf0c59SOlivier Masse# DBG_AE BIT32(17) // AE trace 2464d3c0c2SOlivier MasseCFG_DBG_CAAM_TRACE ?= 0x2 2564d3c0c2SOlivier MasseCFG_DBG_CAAM_DESC ?= 0x0 2664d3c0c2SOlivier MasseCFG_DBG_CAAM_BUF ?= 0x0 2764d3c0c2SOlivier Masse 28de7aa18dSClement Faure# CAAM default drivers 29de7aa18dSClement Faurecaam-drivers = RNG BLOB 30de7aa18dSClement Faure 31de7aa18dSClement Faure# CAAM default drivers connected to the HW crypto API 32*95eea104SOlivier Massecaam-crypto-drivers = CIPHER HASH HMAC CMAC AE_CCM 33de7aa18dSClement Faure 3464d3c0c2SOlivier Masseifneq (,$(filter $(PLATFORM_FLAVOR),ls1012ardb ls1043ardb ls1046ardb)) 3564d3c0c2SOlivier Masse$(call force, CFG_CAAM_BIG_ENDIAN,y) 3664d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x10000) 3764d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,2) 3864d3c0c2SOlivier Masse$(call force, CFG_JR_INT,105) 39de7aa18dSClement Faure$(call force, CFG_CAAM_SGT_ALIGN,4) 40de7aa18dSClement Faure$(call force, CFG_CAAM_64BIT,y) 4164d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V1,y) 42de7aa18dSClement Faure$(call force, CFG_CAAM_ITR,n) 43*95eea104SOlivier Massecaam-crypto-drivers += RSA DSA ECC DH MATH AE_GCM 4464d3c0c2SOlivier Masseelse ifneq (,$(filter $(PLATFORM_FLAVOR),ls1088ardb ls2088ardb ls1028ardb)) 4564d3c0c2SOlivier Masse$(call force, CFG_CAAM_LITTLE_ENDIAN,y) 4664d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x10000) 4764d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,2) 4864d3c0c2SOlivier Masse$(call force, CFG_JR_INT,174) 4964d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V2,y) 50de7aa18dSClement Faure$(call force, CFG_CAAM_SGT_ALIGN,4) 51de7aa18dSClement Faure$(call force, CFG_CAAM_64BIT,y) 52de7aa18dSClement Faure$(call force, CFG_CAAM_ITR,n) 53*95eea104SOlivier Massecaam-crypto-drivers += RSA DSA ECC DH MATH AE_GCM 5464d3c0c2SOlivier Masseelse ifneq (,$(filter $(PLATFORM_FLAVOR),lx2160aqds lx2160ardb)) 5564d3c0c2SOlivier Masse$(call force, CFG_CAAM_LITTLE_ENDIAN,y) 5664d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x10000) 5764d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,2) 5864d3c0c2SOlivier Masse$(call force, CFG_JR_INT, 174) 5964d3c0c2SOlivier Masse$(call force, CFG_NB_JOBS_QUEUE, 80) 6064d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V2,y) 61de7aa18dSClement Faure$(call force, CFG_CAAM_SGT_ALIGN,4) 62de7aa18dSClement Faure$(call force, CFG_CAAM_64BIT,y) 63de7aa18dSClement Faure$(call force, CFG_CAAM_ITR,n) 64*95eea104SOlivier Massecaam-crypto-drivers += RSA DSA ECC DH MATH AE_GCM 6564d3c0c2SOlivier Masseelse ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist) $(mx8qx-flavorlist))) 6664d3c0c2SOlivier Masse$(call force, CFG_CAAM_SIZE_ALIGN,4) 6764d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x10000) 6864d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,3) 6964d3c0c2SOlivier Masse$(call force, CFG_JR_INT,486) 7064d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V1,y) 71*95eea104SOlivier Massecaam-crypto-drivers += RSA DSA ECC DH MATH AE_GCM 7221f58962SClement Faureelse ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist))) 7321f58962SClement Faure$(call force, CFG_CAAM_SIZE_ALIGN,4) 7421f58962SClement Faure$(call force, CFG_JR_BLOCK_SIZE,0x10000) 75b21f1220SClement Faure$(call force, CFG_JR_INDEX,3) 760b1eafdeSClement Faure$(call force, CFG_JR_INT,356) 7721f58962SClement Faure$(call force, CFG_NXP_CAAM_SGT_V1,y) 7821f58962SClement Faure$(call force, CFG_CAAM_JR_DISABLE_NODE,n) 79*95eea104SOlivier Massecaam-crypto-drivers += RSA DSA ECC DH MATH AE_GCM 80de7aa18dSClement Faureelse ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist) $(mx8mn-flavorlist) \ 81de7aa18dSClement Faure $(mx8mp-flavorlist) $(mx8mq-flavorlist))) 8264d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x1000) 8364d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,2) 8464d3c0c2SOlivier Masse$(call force, CFG_JR_INT,146) 8564d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V1,y) 86de7aa18dSClement Faure$(call force, CFG_JR_HAB_INDEX,0) 8791e9a1b5SSahil Malhotra# There is a limitation on i.MX8M platforms regarding ECDSA Sign/Verify 8891e9a1b5SSahil Malhotra# Size of Class 2 Context register is 40bytes, because of which sign/verify 8991e9a1b5SSahil Malhotra# of a hash of more than 40bytes fails. So a workaround is implemented for 9091e9a1b5SSahil Malhotra# this issue, controlled by CFG_NXP_CAAM_C2_CTX_REG_WA flag. 9191e9a1b5SSahil Malhotra$(call force, CFG_NXP_CAAM_C2_CTX_REG_WA,y) 92280dd882SClement Faurecaam-drivers += MP DEK 93*95eea104SOlivier Massecaam-crypto-drivers += RSA DSA ECC DH MATH AE_GCM 9464d3c0c2SOlivier Masseelse ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist))) 9564d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x1000) 9664d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,2) 9764d3c0c2SOlivier Masse$(call force, CFG_JR_INT,114) 9864d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V1,y) 9964d3c0c2SOlivier Masse$(call force, CFG_CAAM_ITR,n) 100*95eea104SOlivier Massecaam-crypto-drivers += AE_GCM 10164d3c0c2SOlivier Masseelse ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist))) 10264d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x1000) 10364d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,0) 10464d3c0c2SOlivier Masse$(call force, CFG_JR_INT,137) 10564d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V1,y) 10664d3c0c2SOlivier Masse$(call force, CFG_CAAM_ITR,n) 107*95eea104SOlivier Massecaam-crypto-drivers += AE_GCM 108de7aa18dSClement Faureelse ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist) $(mx7d-flavorlist) \ 109de7aa18dSClement Faure $(mx7s-flavorlist))) 110de7aa18dSClement Faure$(call force, CFG_JR_BLOCK_SIZE,0x1000) 111de7aa18dSClement Faure$(call force, CFG_JR_INDEX,0) 112de7aa18dSClement Faure$(call force, CFG_JR_INT,137) 113de7aa18dSClement Faure$(call force, CFG_NXP_CAAM_SGT_V1,y) 114de7aa18dSClement Faurecaam-drivers += MP 115*95eea104SOlivier Massecaam-crypto-drivers += RSA DSA ECC DH MATH AE_GCM 116de7aa18dSClement Faureelse ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist) $(mx6qp-flavorlist) \ 117de7aa18dSClement Faure $(mx6sx-flavorlist) $(mx6d-flavorlist) $(mx6dl-flavorlist) \ 118de7aa18dSClement Faure $(mx6s-flavorlist) $(mx8ulp-flavorlist))) 11964d3c0c2SOlivier Masse$(call force, CFG_JR_BLOCK_SIZE,0x1000) 12064d3c0c2SOlivier Masse$(call force, CFG_JR_INDEX,0) 12164d3c0c2SOlivier Masse$(call force, CFG_JR_INT,137) 12264d3c0c2SOlivier Masse$(call force, CFG_NXP_CAAM_SGT_V1,y) 12364d3c0c2SOlivier Masseelse 12464d3c0c2SOlivier Masse$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)") 12564d3c0c2SOlivier Masseendif 12664d3c0c2SOlivier Masse 127de7aa18dSClement Faure# Disable the i.MX CAAM driver 128de7aa18dSClement Faure$(call force,CFG_IMX_CAAM,n,Mandated by CFG_NXP_CAAM) 12964d3c0c2SOlivier Masse 130de7aa18dSClement Faure# CAAM buffer alignment size 131de7aa18dSClement FaureCFG_CAAM_SIZE_ALIGN ?= 1 13264d3c0c2SOlivier Masse 133de7aa18dSClement Faure# Default padding number for SGT allocation 13464d3c0c2SOlivier MasseCFG_CAAM_SGT_ALIGN ?= 1 13564d3c0c2SOlivier Masse 136de7aa18dSClement Faure# Enable job ring interruption 137de7aa18dSClement FaureCFG_CAAM_ITR ?= y 138de7aa18dSClement Faure 139de7aa18dSClement Faure# Keep the CFG_JR_INDEX as secure at runtime 140de7aa18dSClement FaureCFG_NXP_CAAM_RUNTIME_JR ?= y 141de7aa18dSClement Faure 142de7aa18dSClement Faure# Define the RSA Private Key Format used by the CAAM 143de7aa18dSClement Faure# Format #1: (n, d) 144de7aa18dSClement Faure# Format #2: (p, q, d) 145de7aa18dSClement Faure# Format #3: (p, q, dp, dq, qp) 146de7aa18dSClement FaureCFG_NXP_CAAM_RSA_KEY_FORMAT ?= 3 147de7aa18dSClement Faure 148de7aa18dSClement Faure# Disable device tree status of the secure job ring 149de7aa18dSClement FaureCFG_CAAM_JR_DISABLE_NODE ?= y 150de7aa18dSClement Faure 1511495f6c4SClement Faure# Define the default CAAM private key encryption generation and the bignum 1521495f6c4SClement Faure# maximum size needed. 1531495f6c4SClement Faure# CAAM_KEY_PLAIN_TEXT -> 4096 bits 154cf865357SSahil Malhotra# CAAM_KEY_BLACK_ECB|CCM -> 4576 bits 155cf865357SSahil Malhotra# 4096 (RSA Max key size) + 12 * 8 (Header serialization) + 156cf865357SSahil Malhotra# 48 * 8 (Black blob overhead in bytes) = 4576 bits 157cf865357SSahil MalhotraCFG_CORE_BIGNUM_MAX_BITS ?= 4576 1581495f6c4SClement Faure 159ba7db6e0SSahil Malhotra# CAAM RNG Prediction Resistance 160ba7db6e0SSahil Malhotra# When this flag is y, the CAAM RNG is reseeded on every random number request. 161ba7db6e0SSahil Malhotra# In this case the performance is drastically reduced. 162ba7db6e0SSahil MalhotraCFG_CAAM_RNG_RUNTIME_PR ?= n 163ba7db6e0SSahil Malhotra 164de7aa18dSClement Faure# Enable CAAM non-crypto drivers 165de7aa18dSClement Faure$(foreach drv, $(caam-drivers), $(eval CFG_NXP_CAAM_$(drv)_DRV ?= y)) 166de7aa18dSClement Faure 1677a5015ddSRouven Czerwinski# Prefer CAAM HWRNG over PRNG seeded by CAAM 168de7aa18dSClement Faureifeq ($(CFG_NXP_CAAM_RNG_DRV), y) 1697a5015ddSRouven CzerwinskiCFG_WITH_SOFTWARE_PRNG ?= n 170de7aa18dSClement Faureendif 17164d3c0c2SOlivier Masse 172280dd882SClement Faure# DEK driver requires the SM driver to be enabled 173280dd882SClement Faureifeq ($(CFG_NXP_CAAM_DEK_DRV), y) 174280dd882SClement Faure$(call force, CFG_NXP_CAAM_SM_DRV,y,Mandated by CFG_NXP_CAAM_DEK_DRV) 175280dd882SClement Faureendif 176280dd882SClement Faure 17764d3c0c2SOlivier Masseifeq ($(CFG_CRYPTO_DRIVER), y) 17864d3c0c2SOlivier MasseCFG_CRYPTO_DRIVER_DEBUG ?= 0 17964d3c0c2SOlivier Masse 180de7aa18dSClement Faure# Enable CAAM Crypto drivers 181de7aa18dSClement Faure$(foreach drv, $(caam-crypto-drivers), $(eval CFG_NXP_CAAM_$(drv)_DRV ?= y)) 18264d3c0c2SOlivier Masse 183de7aa18dSClement Faure# Enable MAC crypto driver 184de7aa18dSClement Faureifeq ($(call cfg-one-enabled,CFG_NXP_CAAM_HMAC_DRV CFG_NXP_CAAM_CMAC_DRV),y) 185de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_MAC,y,Mandated by CFG_NXP_CAAM_HMAC/CMAC_DRV) 18664d3c0c2SOlivier Masseendif 18764d3c0c2SOlivier Masse 188de7aa18dSClement Faure# Enable CIPHER crypto driver 189de7aa18dSClement Faureifeq ($(CFG_NXP_CAAM_CIPHER_DRV), y) 190de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_CIPHER,y,Mandated by CFG_NXP_CAAM_CIPHER_DRV) 191d538d293SClement Faureendif 192d538d293SClement Faure 193faaf0c59SOlivier Masse# Enable AE crypto driver 194*95eea104SOlivier Masseifeq ($(call cfg-one-enabled,CFG_NXP_CAAM_AE_CCM_DRV CFG_NXP_CAAM_AE_GCM_DRV),y) 195*95eea104SOlivier Masse$(call force, CFG_CRYPTO_DRV_AUTHENC,y,Mandated by CFG_NXP_CAAM_AE_CCM/GCM_DRV) 196faaf0c59SOlivier Masseendif 197faaf0c59SOlivier Masse 198de7aa18dSClement Faure# Enable HASH crypto driver 199de7aa18dSClement Faureifeq ($(CFG_NXP_CAAM_HASH_DRV), y) 200de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_HASH,y,Mandated by CFG_NXP_CAAM_HASH_DRV) 201de7aa18dSClement Faureendif 20264d3c0c2SOlivier Masse 203de7aa18dSClement Faure# Enable RSA crypto driver 204de7aa18dSClement Faureifeq ($(CFG_NXP_CAAM_RSA_DRV), y) 205de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_RSA,y,Mandated by CFG_NXP_CAAM_RSA_DRV) 206de7aa18dSClement Faureendif 207de7aa18dSClement Faure 208de7aa18dSClement Faure# Enable ECC crypto driver 209de7aa18dSClement Faureifeq ($(CFG_NXP_CAAM_ECC_DRV), y) 210de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_ECC,y,Mandated by CFG_NXP_CAAM_ECC_DRV) 211de7aa18dSClement Faureendif 212de7aa18dSClement Faure 213de7aa18dSClement Faure# Enable DSA crypto driver 214de7aa18dSClement Faureifeq ($(CFG_NXP_CAAM_DSA_DRV), y) 215de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_DSA,y,Mandated by CFG_NXP_CAAM_DSA_DRV) 216de7aa18dSClement Faureendif 217de7aa18dSClement Faure 218de7aa18dSClement Faure# Enable DH crypto driver 219de7aa18dSClement Faureifeq ($(CFG_NXP_CAAM_DH_DRV), y) 220de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_DH,y,Mandated by CFG_NXP_CAAM_DH_DRV) 221de7aa18dSClement Faureendif 222de7aa18dSClement Faure 223de7aa18dSClement Faure# Enable ACIPHER crypto driver 224de7aa18dSClement Faureifeq ($(call cfg-one-enabled,CFG_CRYPTO_DRV_RSA CFG_CRYPTO_DRV_ECC \ 225de7aa18dSClement Faure CFG_CRYPTO_DRV_DSA CFG_CRYPTO_DRV_DH),y) 226de7aa18dSClement Faure$(call force, CFG_CRYPTO_DRV_ACIPHER,y,Mandated by CFG_CRYPTO_DRV_{RSA|ECC|DSA|DH}) 227de7aa18dSClement Faureendif 22864d3c0c2SOlivier Masse 22964d3c0c2SOlivier Masseendif # CFG_CRYPTO_DRIVER 23064d3c0c2SOlivier Masseendif # CFG_NXP_CAAM 231