1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0+) 2 /* 3 * Copyright (C) 2018-2022, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32mp1_rcc.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <drivers/stm32_shared_io.h> 12 #include <drivers/stm32mp_dt_bindings.h> 13 #include <initcall.h> 14 #include <io.h> 15 #include <keep.h> 16 #include <kernel/dt.h> 17 #include <kernel/boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/spinlock.h> 20 #include <libfdt.h> 21 #include <platform_config.h> 22 #include <stdio.h> 23 #include <stm32_util.h> 24 #include <trace.h> 25 #include <util.h> 26 27 /* Identifiers for root oscillators */ 28 enum stm32mp_osc_id { 29 OSC_HSI, 30 OSC_HSE, 31 OSC_CSI, 32 OSC_LSI, 33 OSC_LSE, 34 OSC_I2S_CKIN, 35 OSC_USB_PHY_48, 36 NB_OSC, 37 _UNKNOWN_OSC_ID = 0xffU 38 }; 39 40 /* Identifiers for parent clocks */ 41 enum stm32mp1_parent_id { 42 _HSI, 43 _HSE, 44 _CSI, 45 _LSI, 46 _LSE, 47 _I2S_CKIN, 48 _USB_PHY_48, 49 _HSI_KER, 50 _HSE_KER, 51 _HSE_KER_DIV2, 52 _HSE_RTC, 53 _CSI_KER, 54 _PLL1_P, 55 _PLL1_Q, 56 _PLL1_R, 57 _PLL2_P, 58 _PLL2_Q, 59 _PLL2_R, 60 _PLL3_P, 61 _PLL3_Q, 62 _PLL3_R, 63 _PLL4_P, 64 _PLL4_Q, 65 _PLL4_R, 66 _ACLK, 67 _PCLK1, 68 _PCLK2, 69 _PCLK3, 70 _PCLK4, 71 _PCLK5, 72 _HCLK5, 73 _HCLK6, 74 _HCLK2, 75 _CK_PER, 76 _CK_MPU, 77 _CK_MCU, 78 _PARENT_NB, 79 _UNKNOWN_ID = 0xff, 80 }; 81 82 /* 83 * Identifiers for parent clock selectors. 84 * This enum lists only the parent clocks we are interested in. 85 */ 86 enum stm32mp1_parent_sel { 87 _STGEN_SEL, 88 _I2C35_SEL, 89 _I2C46_SEL, 90 _SPI6_SEL, 91 _USART1_SEL, 92 _RNG1_SEL, 93 _UART6_SEL, 94 _UART24_SEL, 95 _UART35_SEL, 96 _UART78_SEL, 97 _AXISS_SEL, 98 _MCUSS_SEL, 99 _USBPHY_SEL, 100 _USBO_SEL, 101 _RTC_SEL, 102 _MPU_SEL, 103 _PARENT_SEL_NB, 104 _UNKNOWN_SEL = 0xff, 105 }; 106 107 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 108 [_HSE] = CK_HSE, 109 [_HSI] = CK_HSI, 110 [_CSI] = CK_CSI, 111 [_LSE] = CK_LSE, 112 [_LSI] = CK_LSI, 113 [_I2S_CKIN] = _UNKNOWN_ID, 114 [_USB_PHY_48] = _UNKNOWN_ID, 115 [_HSI_KER] = CK_HSI, 116 [_HSE_KER] = CK_HSE, 117 [_HSE_KER_DIV2] = CK_HSE_DIV2, 118 [_HSE_RTC] = _UNKNOWN_ID, 119 [_CSI_KER] = CK_CSI, 120 [_PLL1_P] = PLL1_P, 121 [_PLL1_Q] = PLL1_Q, 122 [_PLL1_R] = PLL1_R, 123 [_PLL2_P] = PLL2_P, 124 [_PLL2_Q] = PLL2_Q, 125 [_PLL2_R] = PLL2_R, 126 [_PLL3_P] = PLL3_P, 127 [_PLL3_Q] = PLL3_Q, 128 [_PLL3_R] = PLL3_R, 129 [_PLL4_P] = PLL4_P, 130 [_PLL4_Q] = PLL4_Q, 131 [_PLL4_R] = PLL4_R, 132 [_ACLK] = CK_AXI, 133 [_PCLK1] = CK_AXI, 134 [_PCLK2] = CK_AXI, 135 [_PCLK3] = CK_AXI, 136 [_PCLK4] = CK_AXI, 137 [_PCLK5] = CK_AXI, 138 [_HCLK5] = CK_AXI, 139 [_HCLK6] = CK_AXI, 140 [_HCLK2] = CK_AXI, 141 [_CK_PER] = CK_PER, 142 [_CK_MPU] = CK_MPU, 143 [_CK_MCU] = CK_MCU, 144 }; 145 146 static enum stm32mp1_parent_id osc_id2parent_id(enum stm32mp_osc_id osc_id) 147 { 148 assert(osc_id >= OSC_HSI && osc_id < NB_OSC); 149 COMPILE_TIME_ASSERT((int)OSC_HSI == (int)_HSI && 150 (int)OSC_HSE == (int)_HSE && 151 (int)OSC_CSI == (int)_CSI && 152 (int)OSC_LSI == (int)_LSI && 153 (int)OSC_LSE == (int)_LSE && 154 (int)OSC_I2S_CKIN == (int)_I2S_CKIN && 155 (int)OSC_USB_PHY_48 == (int)_USB_PHY_48); 156 157 return (enum stm32mp1_parent_id)osc_id; 158 } 159 160 static enum stm32mp1_parent_id clock_id2parent_id(unsigned long id) 161 { 162 size_t n = 0; 163 164 COMPILE_TIME_ASSERT(STM32MP1_LAST_CLK < _UNKNOWN_ID); 165 166 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++) 167 if (parent_id_clock_id[n] == id) 168 return (enum stm32mp1_parent_id)n; 169 170 return _UNKNOWN_ID; 171 } 172 173 /* Identifiers for PLLs and their configuration resources */ 174 enum stm32mp1_pll_id { 175 _PLL1, 176 _PLL2, 177 _PLL3, 178 _PLL4, 179 _PLL_NB 180 }; 181 182 enum stm32mp1_div_id { 183 _DIV_P, 184 _DIV_Q, 185 _DIV_R, 186 _DIV_NB, 187 }; 188 189 enum stm32mp1_plltype { 190 PLL_800, 191 PLL_1600, 192 PLL_TYPE_NB 193 }; 194 195 /* 196 * Clock generic gates clocks which state is controlled by a single RCC bit 197 * 198 * @offset: RCC register byte offset from RCC base where clock is controlled 199 * @bit: Bit position in the RCC 32bit register 200 * @clock_id: Identifier used for the clock in the clock driver API 201 * @set_clr: Non-null if and only-if RCC register is a CLEAR/SET register 202 * (CLEAR register is at offset RCC_MP_ENCLRR_OFFSET from SET register) 203 * @secure: One of N_S or SEC, defined below 204 * @sel: _UNKNOWN_ID (fixed parent) or reference to parent clock selector 205 * (8bit storage of ID from enum stm32mp1_parent_sel) 206 * @fixed: _UNKNOWN_ID (selectable paranet) or reference to parent clock 207 * (8bit storage of ID from enum stm32mp1_parent_id) 208 */ 209 struct stm32mp1_clk_gate { 210 uint16_t offset; 211 uint8_t bit; 212 uint8_t clock_id; 213 uint8_t set_clr; 214 uint8_t secure; 215 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 216 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 217 }; 218 219 /* Parent clock selection: select register info, parent clocks references */ 220 struct stm32mp1_clk_sel { 221 uint16_t offset; 222 uint8_t src; 223 uint8_t msk; 224 uint8_t nb_parent; 225 const uint8_t *parent; 226 }; 227 228 #define REFCLK_SIZE 4 229 /* PLL control: type, control register offsets, up-to-4 selectable parent */ 230 struct stm32mp1_clk_pll { 231 enum stm32mp1_plltype plltype; 232 uint16_t rckxselr; 233 uint16_t pllxcfgr1; 234 uint16_t pllxcfgr2; 235 uint16_t pllxfracr; 236 uint16_t pllxcr; 237 uint16_t pllxcsgr; 238 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 239 }; 240 241 #define N_S 0 /* Non-secure can access RCC interface */ 242 #define SEC 1 /* RCC[TZEN] protects RCC interface */ 243 244 /* Clocks with selectable source and not set/clr register access */ 245 #define _CLK_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 246 { \ 247 .offset = (_offset), \ 248 .bit = (_bit), \ 249 .clock_id = (_clock_id), \ 250 .set_clr = 0, \ 251 .secure = (_sec), \ 252 .sel = (_parent_sel), \ 253 .fixed = _UNKNOWN_ID, \ 254 } 255 256 /* Clocks with fixed source and not set/clr register access */ 257 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 258 { \ 259 .offset = (_offset), \ 260 .bit = (_bit), \ 261 .clock_id = (_clock_id), \ 262 .set_clr = 0, \ 263 .secure = (_sec), \ 264 .sel = _UNKNOWN_SEL, \ 265 .fixed = (_parent), \ 266 } 267 268 /* Clocks with selectable source and set/clr register access */ 269 #define _CLK_SC_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 270 { \ 271 .offset = (_offset), \ 272 .bit = (_bit), \ 273 .clock_id = (_clock_id), \ 274 .set_clr = 1, \ 275 .secure = (_sec), \ 276 .sel = (_parent_sel), \ 277 .fixed = _UNKNOWN_ID, \ 278 } 279 280 /* Clocks with fixed source and set/clr register access */ 281 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 282 { \ 283 .offset = (_offset), \ 284 .bit = (_bit), \ 285 .clock_id = (_clock_id), \ 286 .set_clr = 1, \ 287 .secure = (_sec), \ 288 .sel = _UNKNOWN_SEL, \ 289 .fixed = (_parent), \ 290 } 291 292 /* 293 * Clocks with selectable source and set/clr register access 294 * and enable bit position defined by a label (argument _bit) 295 */ 296 #define _CLK_SC2_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 297 { \ 298 .offset = (_offset), \ 299 .clock_id = (_clock_id), \ 300 .bit = _offset ## _ ## _bit ## _POS, \ 301 .set_clr = 1, \ 302 .secure = (_sec), \ 303 .sel = (_parent_sel), \ 304 .fixed = _UNKNOWN_ID, \ 305 } 306 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 307 { \ 308 .offset = (_offset), \ 309 .clock_id = (_clock_id), \ 310 .bit = _offset ## _ ## _bit ## _POS, \ 311 .set_clr = 1, \ 312 .secure = (_sec), \ 313 .sel = _UNKNOWN_SEL, \ 314 .fixed = (_parent), \ 315 } 316 317 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ 318 [(idx)] = { \ 319 .offset = (_offset), \ 320 .src = (_src), \ 321 .msk = (_mask), \ 322 .parent = (_parent), \ 323 .nb_parent = ARRAY_SIZE(_parent) \ 324 } 325 326 #define _CLK_PLL(_idx, _type, _off1, _off2, _off3, _off4, \ 327 _off5, _off6, _p1, _p2, _p3, _p4) \ 328 [(_idx)] = { \ 329 .plltype = (_type), \ 330 .rckxselr = (_off1), \ 331 .pllxcfgr1 = (_off2), \ 332 .pllxcfgr2 = (_off3), \ 333 .pllxfracr = (_off4), \ 334 .pllxcr = (_off5), \ 335 .pllxcsgr = (_off6), \ 336 .refclk[0] = (_p1), \ 337 .refclk[1] = (_p2), \ 338 .refclk[2] = (_p3), \ 339 .refclk[3] = (_p4), \ 340 } 341 342 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 343 344 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 345 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 346 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 347 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 348 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 356 357 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, SPI6EN, SPI6_K, _SPI6_SEL), 358 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C4EN, I2C4_K, _I2C46_SEL), 359 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C6EN, I2C6_K, _I2C46_SEL), 360 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, USART1EN, USART1_K, _USART1_SEL), 361 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, RTCAPBEN, RTCAPB, _PCLK5), 362 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC1EN, TZC1, _PCLK5), 363 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC2EN, TZC2, _PCLK5), 364 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZPCEN, TZPC, _PCLK5), 365 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, IWDG1APBEN, IWDG1, _PCLK5), 366 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, BSECEN, BSEC, _PCLK5), 367 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, STGENEN, STGEN_K, _STGEN_SEL), 368 369 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5), 370 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5), 371 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5), 372 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL), 373 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _HCLK5), 374 375 _CLK_SC2_FIXED(SEC, RCC_MP_TZAHB6ENSETR, MDMA, MDMA, _HCLK6), 376 377 _CLK_SELEC(SEC, RCC_BDCR, RCC_BDCR_RTCCKEN_POS, RTC, _RTC_SEL), 378 379 /* Non-secure clocks */ 380 #ifdef CFG_WITH_NSEC_I2CS 381 _CLK_SC2_SELEC(N_S, RCC_MP_APB1ENSETR, I2C5EN, I2C5_K, _I2C35_SEL), 382 #endif 383 384 #ifdef CFG_WITH_NSEC_GPIOS 385 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_ID), 386 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_ID), 387 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_ID), 388 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_ID), 389 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_ID), 390 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_ID), 391 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_ID), 392 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_ID), 393 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_ID), 394 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_ID), 395 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_ID), 396 #endif 397 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 398 #ifdef CFG_WITH_NSEC_UARTS 399 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 400 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 401 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 402 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 403 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 404 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 405 #endif 406 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 407 #ifdef CFG_WITH_NSEC_UARTS 408 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 409 #endif 410 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 411 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 412 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 413 414 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 415 }; 416 DECLARE_KEEP_PAGER(stm32mp1_clk_gate); 417 418 const uint8_t stm32mp1_clk_on[] = { 419 CK_HSE, CK_CSI, CK_LSI, CK_LSE, CK_HSI, CK_HSE_DIV2, 420 PLL1_P, PLL1_Q, PLL1_R, PLL2_P, PLL2_Q, PLL2_R, PLL3_P, PLL3_Q, PLL3_R, 421 CK_AXI, CK_MPU, CK_MCU, 422 }; 423 424 /* Parents for secure aware clocks in the xxxSELR value ordering */ 425 static const uint8_t stgen_parents[] = { 426 _HSI_KER, _HSE_KER 427 }; 428 429 #ifdef CFG_WITH_NSEC_I2CS 430 static const uint8_t i2c35_parents[] = { 431 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 432 }; 433 #endif 434 435 static const uint8_t i2c46_parents[] = { 436 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 437 }; 438 439 static const uint8_t spi6_parents[] = { 440 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 441 }; 442 443 static const uint8_t usart1_parents[] = { 444 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 445 }; 446 447 static const uint8_t rng1_parents[] = { 448 _CSI, _PLL4_R, _LSE, _LSI 449 }; 450 451 static const uint8_t mpu_parents[] = { 452 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 453 }; 454 455 /* Parents for (some) non-secure clocks */ 456 #ifdef CFG_WITH_NSEC_UARTS 457 static const uint8_t uart6_parents[] = { 458 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 459 }; 460 461 static const uint8_t uart234578_parents[] = { 462 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 463 }; 464 #endif 465 466 static const uint8_t axiss_parents[] = { 467 _HSI, _HSE, _PLL2_P 468 }; 469 470 static const uint8_t mcuss_parents[] = { 471 _HSI, _HSE, _CSI, _PLL3_P 472 }; 473 474 static const uint8_t rtc_parents[] = { 475 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 476 }; 477 478 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 479 /* Secure aware clocks */ 480 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 481 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 482 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), 483 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), 484 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), 485 _CLK_PARENT(_RTC_SEL, RCC_BDCR, 16, 0x3, rtc_parents), 486 _CLK_PARENT(_MPU_SEL, RCC_MPCKSELR, 0, 0x3, mpu_parents), 487 /* Always non-secure clocks (maybe used in some way in secure world) */ 488 #ifdef CFG_WITH_NSEC_I2CS 489 _CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), 490 #endif 491 #ifdef CFG_WITH_NSEC_UARTS 492 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 493 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), 494 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), 495 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), 496 #endif 497 _CLK_PARENT(_AXISS_SEL, RCC_ASSCKSELR, 0, 0x3, axiss_parents), 498 _CLK_PARENT(_MCUSS_SEL, RCC_MSSCKSELR, 0, 0x3, mcuss_parents), 499 }; 500 501 /* PLLNCFGR2 register divider by output */ 502 static const uint8_t pllncfgr2[_DIV_NB] = { 503 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 504 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 505 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 506 }; 507 508 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 509 _CLK_PLL(_PLL1, PLL_1600, 510 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 511 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 512 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 513 _CLK_PLL(_PLL2, PLL_1600, 514 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 515 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 516 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 517 _CLK_PLL(_PLL3, PLL_800, 518 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 519 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 520 OSC_HSI, OSC_HSE, OSC_CSI, _UNKNOWN_OSC_ID), 521 _CLK_PLL(_PLL4, PLL_800, 522 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 523 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 524 OSC_HSI, OSC_HSE, OSC_CSI, OSC_I2S_CKIN), 525 }; 526 527 /* Prescaler table lookups for clock computation */ 528 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 529 static const uint8_t stm32mp1_mcu_div[16] = { 530 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 531 }; 532 533 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 534 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 535 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 536 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 537 0, 1, 2, 3, 4, 4, 4, 4 538 }; 539 540 /* div = /1 /2 /3 /4 */ 541 static const uint8_t stm32mp1_axi_div[8] = { 542 1, 2, 3, 4, 4, 4, 4, 4 543 }; 544 545 static const char __maybe_unused *const stm32mp1_clk_parent_name[_PARENT_NB] = { 546 [_HSI] = "HSI", 547 [_HSE] = "HSE", 548 [_CSI] = "CSI", 549 [_LSI] = "LSI", 550 [_LSE] = "LSE", 551 [_I2S_CKIN] = "I2S_CKIN", 552 [_HSI_KER] = "HSI_KER", 553 [_HSE_KER] = "HSE_KER", 554 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 555 [_HSE_RTC] = "HSE_RTC", 556 [_CSI_KER] = "CSI_KER", 557 [_PLL1_P] = "PLL1_P", 558 [_PLL1_Q] = "PLL1_Q", 559 [_PLL1_R] = "PLL1_R", 560 [_PLL2_P] = "PLL2_P", 561 [_PLL2_Q] = "PLL2_Q", 562 [_PLL2_R] = "PLL2_R", 563 [_PLL3_P] = "PLL3_P", 564 [_PLL3_Q] = "PLL3_Q", 565 [_PLL3_R] = "PLL3_R", 566 [_PLL4_P] = "PLL4_P", 567 [_PLL4_Q] = "PLL4_Q", 568 [_PLL4_R] = "PLL4_R", 569 [_ACLK] = "ACLK", 570 [_PCLK1] = "PCLK1", 571 [_PCLK2] = "PCLK2", 572 [_PCLK3] = "PCLK3", 573 [_PCLK4] = "PCLK4", 574 [_PCLK5] = "PCLK5", 575 [_HCLK2] = "HCLK2", 576 [_HCLK5] = "HCLK5", 577 [_HCLK6] = "HCLK6", 578 [_CK_PER] = "CK_PER", 579 [_CK_MPU] = "CK_MPU", 580 [_CK_MCU] = "CK_MCU", 581 [_USB_PHY_48] = "USB_PHY_48", 582 }; 583 584 /* 585 * Oscillator frequency in Hz. This array shall be initialized 586 * according to platform. 587 */ 588 static unsigned long stm32mp1_osc[NB_OSC]; 589 590 static unsigned long osc_frequency(enum stm32mp_osc_id idx) 591 { 592 if (idx >= ARRAY_SIZE(stm32mp1_osc)) { 593 DMSG("clk id %d not found", idx); 594 return 0; 595 } 596 597 return stm32mp1_osc[idx]; 598 } 599 600 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 601 { 602 return &stm32mp1_clk_gate[idx]; 603 } 604 605 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 606 { 607 return &stm32mp1_clk_sel[idx]; 608 } 609 610 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 611 { 612 return &stm32mp1_clk_pll[idx]; 613 } 614 615 static int stm32mp1_clk_get_gated_id(unsigned long id) 616 { 617 unsigned int i = 0; 618 619 for (i = 0; i < NB_GATES; i++) 620 if (gate_ref(i)->clock_id == id) 621 return i; 622 623 DMSG("clk id %lu not found", id); 624 return -1; 625 } 626 627 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 628 { 629 return (enum stm32mp1_parent_sel)gate_ref(i)->sel; 630 } 631 632 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 633 { 634 return (enum stm32mp1_parent_id)gate_ref(i)->fixed; 635 } 636 637 static int stm32mp1_clk_get_parent(unsigned long id) 638 { 639 const struct stm32mp1_clk_sel *sel = NULL; 640 enum stm32mp1_parent_id parent_id = 0; 641 uint32_t p_sel = 0; 642 int i = 0; 643 enum stm32mp1_parent_id p = _UNKNOWN_ID; 644 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 645 vaddr_t rcc_base = stm32_rcc_base(); 646 647 parent_id = clock_id2parent_id(id); 648 if (parent_id != _UNKNOWN_ID) 649 return (int)parent_id; 650 651 i = stm32mp1_clk_get_gated_id(id); 652 if (i < 0) 653 panic(); 654 655 p = stm32mp1_clk_get_fixed_parent(i); 656 if (p < _PARENT_NB) 657 return (int)p; 658 659 s = stm32mp1_clk_get_sel(i); 660 if (s == _UNKNOWN_SEL) 661 return -1; 662 if (s >= _PARENT_SEL_NB) 663 panic(); 664 665 sel = clk_sel_ref(s); 666 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & sel->msk; 667 if (p_sel < sel->nb_parent) 668 return (int)sel->parent[p_sel]; 669 670 DMSG("No parent selected for clk %lu", id); 671 return -1; 672 } 673 674 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 675 { 676 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr); 677 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 678 679 return osc_frequency(pll->refclk[src]); 680 } 681 682 /* 683 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 684 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 685 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 686 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 687 */ 688 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 689 { 690 unsigned long refclk = 0; 691 unsigned long fvco = 0; 692 uint32_t cfgr1 = 0; 693 uint32_t fracr = 0; 694 uint32_t divm = 0; 695 uint32_t divn = 0; 696 697 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); 698 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); 699 700 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT; 701 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 702 703 refclk = stm32mp1_pll_get_fref(pll); 704 705 /* 706 * With FRACV : 707 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 708 * Without FRACV 709 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 710 */ 711 if (fracr & RCC_PLLNFRACR_FRACLE) { 712 unsigned long long numerator = 0; 713 unsigned long long denominator = 0; 714 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 715 RCC_PLLNFRACR_FRACV_SHIFT; 716 717 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 718 numerator = refclk * numerator; 719 denominator = ((unsigned long long)divm + 1U) << 13; 720 fvco = (unsigned long)(numerator / denominator); 721 } else { 722 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 723 } 724 725 return fvco; 726 } 727 728 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 729 enum stm32mp1_div_id div_id) 730 { 731 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 732 unsigned long dfout = 0; 733 uint32_t cfgr2 = 0; 734 uint32_t divy = 0; 735 736 if (div_id >= _DIV_NB) 737 return 0; 738 739 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); 740 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 741 742 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 743 744 return dfout; 745 } 746 747 static unsigned long get_clock_rate(enum stm32mp1_parent_id p) 748 { 749 uint32_t reg = 0; 750 unsigned long clock = 0; 751 vaddr_t rcc_base = stm32_rcc_base(); 752 753 switch (p) { 754 case _CK_MPU: 755 /* MPU sub system */ 756 reg = io_read32(rcc_base + RCC_MPCKSELR); 757 switch (reg & RCC_SELR_SRC_MASK) { 758 case RCC_MPCKSELR_HSI: 759 clock = osc_frequency(OSC_HSI); 760 break; 761 case RCC_MPCKSELR_HSE: 762 clock = osc_frequency(OSC_HSE); 763 break; 764 case RCC_MPCKSELR_PLL: 765 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 766 break; 767 case RCC_MPCKSELR_PLL_MPUDIV: 768 reg = io_read32(rcc_base + RCC_MPCKDIVR); 769 if (reg & RCC_MPUDIV_MASK) 770 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> 771 stm32mp1_mpu_div[reg & RCC_MPUDIV_MASK]; 772 else 773 clock = 0; 774 break; 775 default: 776 break; 777 } 778 break; 779 /* AXI sub system */ 780 case _ACLK: 781 case _HCLK2: 782 case _HCLK5: 783 case _HCLK6: 784 case _PCLK4: 785 case _PCLK5: 786 reg = io_read32(rcc_base + RCC_ASSCKSELR); 787 switch (reg & RCC_SELR_SRC_MASK) { 788 case RCC_ASSCKSELR_HSI: 789 clock = osc_frequency(OSC_HSI); 790 break; 791 case RCC_ASSCKSELR_HSE: 792 clock = osc_frequency(OSC_HSE); 793 break; 794 case RCC_ASSCKSELR_PLL: 795 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 796 break; 797 default: 798 break; 799 } 800 801 /* System clock divider */ 802 reg = io_read32(rcc_base + RCC_AXIDIVR); 803 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 804 805 switch (p) { 806 case _PCLK4: 807 reg = io_read32(rcc_base + RCC_APB4DIVR); 808 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 809 break; 810 case _PCLK5: 811 reg = io_read32(rcc_base + RCC_APB5DIVR); 812 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 813 break; 814 default: 815 break; 816 } 817 break; 818 /* MCU sub system */ 819 case _CK_MCU: 820 case _PCLK1: 821 case _PCLK2: 822 case _PCLK3: 823 reg = io_read32(rcc_base + RCC_MSSCKSELR); 824 switch (reg & RCC_SELR_SRC_MASK) { 825 case RCC_MSSCKSELR_HSI: 826 clock = osc_frequency(OSC_HSI); 827 break; 828 case RCC_MSSCKSELR_HSE: 829 clock = osc_frequency(OSC_HSE); 830 break; 831 case RCC_MSSCKSELR_CSI: 832 clock = osc_frequency(OSC_CSI); 833 break; 834 case RCC_MSSCKSELR_PLL: 835 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 836 break; 837 default: 838 break; 839 } 840 841 /* MCU clock divider */ 842 reg = io_read32(rcc_base + RCC_MCUDIVR); 843 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 844 845 switch (p) { 846 case _PCLK1: 847 reg = io_read32(rcc_base + RCC_APB1DIVR); 848 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 849 break; 850 case _PCLK2: 851 reg = io_read32(rcc_base + RCC_APB2DIVR); 852 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 853 break; 854 case _PCLK3: 855 reg = io_read32(rcc_base + RCC_APB3DIVR); 856 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 857 break; 858 case _CK_MCU: 859 default: 860 break; 861 } 862 break; 863 case _CK_PER: 864 reg = io_read32(rcc_base + RCC_CPERCKSELR); 865 switch (reg & RCC_SELR_SRC_MASK) { 866 case RCC_CPERCKSELR_HSI: 867 clock = osc_frequency(OSC_HSI); 868 break; 869 case RCC_CPERCKSELR_HSE: 870 clock = osc_frequency(OSC_HSE); 871 break; 872 case RCC_CPERCKSELR_CSI: 873 clock = osc_frequency(OSC_CSI); 874 break; 875 default: 876 break; 877 } 878 break; 879 case _HSI: 880 case _HSI_KER: 881 clock = osc_frequency(OSC_HSI); 882 break; 883 case _CSI: 884 case _CSI_KER: 885 clock = osc_frequency(OSC_CSI); 886 break; 887 case _HSE: 888 case _HSE_KER: 889 clock = osc_frequency(OSC_HSE); 890 break; 891 case _HSE_KER_DIV2: 892 clock = osc_frequency(OSC_HSE) >> 1; 893 break; 894 case _HSE_RTC: 895 clock = osc_frequency(OSC_HSE); 896 clock /= (io_read32(rcc_base + RCC_RTCDIVR) & 897 RCC_DIVR_DIV_MASK) + 1; 898 break; 899 case _LSI: 900 clock = osc_frequency(OSC_LSI); 901 break; 902 case _LSE: 903 clock = osc_frequency(OSC_LSE); 904 break; 905 /* PLL */ 906 case _PLL1_P: 907 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 908 break; 909 case _PLL1_Q: 910 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 911 break; 912 case _PLL1_R: 913 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 914 break; 915 case _PLL2_P: 916 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 917 break; 918 case _PLL2_Q: 919 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 920 break; 921 case _PLL2_R: 922 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 923 break; 924 case _PLL3_P: 925 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 926 break; 927 case _PLL3_Q: 928 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 929 break; 930 case _PLL3_R: 931 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 932 break; 933 case _PLL4_P: 934 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 935 break; 936 case _PLL4_Q: 937 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 938 break; 939 case _PLL4_R: 940 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 941 break; 942 /* Other */ 943 case _USB_PHY_48: 944 clock = osc_frequency(OSC_USB_PHY_48); 945 break; 946 default: 947 break; 948 } 949 950 return clock; 951 } 952 953 static void __clk_enable(const struct stm32mp1_clk_gate *gate) 954 { 955 vaddr_t base = stm32_rcc_base(); 956 uint32_t bit = BIT(gate->bit); 957 958 if (gate->set_clr) 959 io_write32(base + gate->offset, bit); 960 else 961 io_setbits32_stm32shregs(base + gate->offset, bit); 962 963 FMSG("Clock %u has been enabled", gate->clock_id); 964 } 965 966 static void __clk_disable(const struct stm32mp1_clk_gate *gate) 967 { 968 vaddr_t base = stm32_rcc_base(); 969 uint32_t bit = BIT(gate->bit); 970 971 if (gate->set_clr) 972 io_write32(base + gate->offset + RCC_MP_ENCLRR_OFFSET, bit); 973 else 974 io_clrbits32_stm32shregs(base + gate->offset, bit); 975 976 FMSG("Clock %u has been disabled", gate->clock_id); 977 } 978 979 static long get_timer_rate(long parent_rate, unsigned int apb_bus) 980 { 981 uint32_t timgxpre = 0; 982 uint32_t apbxdiv = 0; 983 vaddr_t rcc_base = stm32_rcc_base(); 984 985 switch (apb_bus) { 986 case 1: 987 apbxdiv = io_read32(rcc_base + RCC_APB1DIVR) & 988 RCC_APBXDIV_MASK; 989 timgxpre = io_read32(rcc_base + RCC_TIMG1PRER) & 990 RCC_TIMGXPRER_TIMGXPRE; 991 break; 992 case 2: 993 apbxdiv = io_read32(rcc_base + RCC_APB2DIVR) & 994 RCC_APBXDIV_MASK; 995 timgxpre = io_read32(rcc_base + RCC_TIMG2PRER) & 996 RCC_TIMGXPRER_TIMGXPRE; 997 break; 998 default: 999 panic(); 1000 break; 1001 } 1002 1003 if (apbxdiv == 0) 1004 return parent_rate; 1005 1006 return parent_rate * (timgxpre + 1) * 2; 1007 } 1008 1009 static unsigned long _stm32_clock_get_rate(unsigned long id) 1010 { 1011 enum stm32mp1_parent_id p = _UNKNOWN_ID; 1012 unsigned long rate = 0; 1013 1014 p = stm32mp1_clk_get_parent(id); 1015 if (p < 0) 1016 return 0; 1017 1018 rate = get_clock_rate(p); 1019 1020 if ((id >= TIM2_K) && (id <= TIM14_K)) 1021 rate = get_timer_rate(rate, 1); 1022 1023 if ((id >= TIM1_K) && (id <= TIM17_K)) 1024 rate = get_timer_rate(rate, 2); 1025 1026 return rate; 1027 } 1028 1029 /* 1030 * Get the parent ID of the target parent clock, or -1 if no parent found. 1031 */ 1032 static enum stm32mp1_parent_id get_parent_id_parent(enum stm32mp1_parent_id id) 1033 { 1034 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 1035 enum stm32mp1_pll_id pll_id = _PLL_NB; 1036 uint32_t p_sel = 0; 1037 1038 switch (id) { 1039 case _ACLK: 1040 case _HCLK5: 1041 case _HCLK6: 1042 case _PCLK4: 1043 case _PCLK5: 1044 s = _AXISS_SEL; 1045 break; 1046 case _PLL1_P: 1047 case _PLL1_Q: 1048 case _PLL1_R: 1049 pll_id = _PLL1; 1050 break; 1051 case _PLL2_P: 1052 case _PLL2_Q: 1053 case _PLL2_R: 1054 pll_id = _PLL2; 1055 break; 1056 case _PLL3_P: 1057 case _PLL3_Q: 1058 case _PLL3_R: 1059 pll_id = _PLL3; 1060 break; 1061 case _PLL4_P: 1062 case _PLL4_Q: 1063 case _PLL4_R: 1064 pll_id = _PLL4; 1065 break; 1066 case _PCLK1: 1067 case _PCLK2: 1068 case _HCLK2: 1069 case _CK_PER: 1070 case _CK_MPU: 1071 case _CK_MCU: 1072 case _USB_PHY_48: 1073 /* We do not expected to access these */ 1074 panic(); 1075 break; 1076 default: 1077 /* Other parents have no parent */ 1078 return -1; 1079 } 1080 1081 if (s != _UNKNOWN_SEL) { 1082 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 1083 vaddr_t rcc_base = stm32_rcc_base(); 1084 1085 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & 1086 sel->msk; 1087 1088 if (p_sel < sel->nb_parent) 1089 return sel->parent[p_sel]; 1090 } else { 1091 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1092 1093 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & 1094 RCC_SELR_REFCLK_SRC_MASK; 1095 1096 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) 1097 return osc_id2parent_id(pll->refclk[p_sel]); 1098 } 1099 1100 FMSG("No parent found for %s", stm32mp1_clk_parent_name[id]); 1101 return -1; 1102 } 1103 1104 /* We are only interested in knowing if PLL3 shall be secure or not */ 1105 static void secure_parent_clocks(enum stm32mp1_parent_id parent_id) 1106 { 1107 enum stm32mp1_parent_id grandparent_id = _UNKNOWN_ID; 1108 1109 switch (parent_id) { 1110 case _ACLK: 1111 case _HCLK2: 1112 case _HCLK5: 1113 case _HCLK6: 1114 case _PCLK4: 1115 case _PCLK5: 1116 /* Intermediate clock mux or clock, go deeper in clock tree */ 1117 break; 1118 case _HSI: 1119 case _HSI_KER: 1120 case _LSI: 1121 case _CSI: 1122 case _CSI_KER: 1123 case _HSE: 1124 case _HSE_KER: 1125 case _HSE_KER_DIV2: 1126 case _HSE_RTC: 1127 case _LSE: 1128 case _PLL1_P: 1129 case _PLL1_Q: 1130 case _PLL1_R: 1131 case _PLL2_P: 1132 case _PLL2_Q: 1133 case _PLL2_R: 1134 /* Always secure clocks, no need to go further */ 1135 return; 1136 case _PLL3_P: 1137 case _PLL3_Q: 1138 case _PLL3_R: 1139 /* PLL3 is a shared resource, registered and don't go further */ 1140 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 1141 return; 1142 default: 1143 DMSG("Cannot lookup parent clock %s", 1144 stm32mp1_clk_parent_name[parent_id]); 1145 panic(); 1146 } 1147 1148 grandparent_id = get_parent_id_parent(parent_id); 1149 if (grandparent_id >= 0) 1150 secure_parent_clocks(grandparent_id); 1151 } 1152 1153 void stm32mp_register_clock_parents_secure(unsigned long clock_id) 1154 { 1155 enum stm32mp1_parent_id parent_id = stm32mp1_clk_get_parent(clock_id); 1156 1157 if (parent_id < 0) { 1158 DMSG("No parent for clock %lu", clock_id); 1159 return; 1160 } 1161 1162 secure_parent_clocks(parent_id); 1163 } 1164 1165 static const char *stm32mp_osc_node_label[NB_OSC] = { 1166 [OSC_LSI] = "clk-lsi", 1167 [OSC_LSE] = "clk-lse", 1168 [OSC_HSI] = "clk-hsi", 1169 [OSC_HSE] = "clk-hse", 1170 [OSC_CSI] = "clk-csi", 1171 [OSC_I2S_CKIN] = "i2s_ckin", 1172 [OSC_USB_PHY_48] = "ck_usbo_48m" 1173 }; 1174 1175 static unsigned int clk_freq_prop(const void *fdt, int node) 1176 { 1177 const fdt32_t *cuint = NULL; 1178 int ret = 0; 1179 1180 /* Disabled clocks report null rate */ 1181 if (_fdt_get_status(fdt, node) == DT_STATUS_DISABLED) 1182 return 0; 1183 1184 cuint = fdt_getprop(fdt, node, "clock-frequency", &ret); 1185 if (!cuint) 1186 panic(); 1187 1188 return fdt32_to_cpu(*cuint); 1189 } 1190 1191 static void get_osc_freq_from_dt(const void *fdt) 1192 { 1193 enum stm32mp_osc_id idx = _UNKNOWN_OSC_ID; 1194 int clk_node = fdt_path_offset(fdt, "/clocks"); 1195 1196 if (clk_node < 0) 1197 panic(); 1198 1199 COMPILE_TIME_ASSERT((int)OSC_HSI == 0); 1200 for (idx = OSC_HSI; idx < NB_OSC; idx++) { 1201 const char *name = stm32mp_osc_node_label[idx]; 1202 int subnode = 0; 1203 1204 fdt_for_each_subnode(subnode, fdt, clk_node) { 1205 const char *cchar = NULL; 1206 int ret = 0; 1207 1208 cchar = fdt_get_name(fdt, subnode, &ret); 1209 if (!cchar) 1210 panic(); 1211 1212 if (strncmp(cchar, name, (size_t)ret) == 0) { 1213 stm32mp1_osc[idx] = clk_freq_prop(fdt, subnode); 1214 1215 DMSG("Osc %s: %lu Hz", name, stm32mp1_osc[idx]); 1216 break; 1217 } 1218 } 1219 1220 if (!stm32mp1_osc[idx]) 1221 DMSG("Osc %s: no frequency info", name); 1222 } 1223 } 1224 1225 static void enable_static_secure_clocks(void) 1226 { 1227 unsigned int idx = 0; 1228 const unsigned long secure_enable[] = { 1229 DDRC1, DDRC1LP, DDRC2, DDRC2LP, DDRPHYC, DDRPHYCLP, DDRCAPB, 1230 AXIDCG, DDRPHYCAPB, DDRPHYCAPBLP, TZPC, TZC1, TZC2, STGEN_K, 1231 BSEC, 1232 }; 1233 1234 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++) { 1235 clk_enable(stm32mp_rcc_clock_id_to_clk(secure_enable[idx])); 1236 stm32mp_register_clock_parents_secure(secure_enable[idx]); 1237 } 1238 1239 if (CFG_TEE_CORE_NB_CORE > 1) 1240 clk_enable(stm32mp_rcc_clock_id_to_clk(RTCAPB)); 1241 } 1242 1243 static void __maybe_unused enable_rcc_tzen(void) 1244 { 1245 io_setbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1246 } 1247 1248 static void __maybe_unused disable_rcc_tzen(void) 1249 { 1250 IMSG("RCC is non-secure"); 1251 io_clrbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1252 } 1253 1254 static TEE_Result stm32mp1_clk_fdt_init(const void *fdt, int node) 1255 { 1256 unsigned int i = 0; 1257 int len = 0; 1258 int ignored = 0; 1259 1260 get_osc_freq_from_dt(fdt); 1261 1262 /* 1263 * OP-TEE core is not in charge of configuring clock parenthood. 1264 * This is expected from an earlier boot stage. Modifying the clock 1265 * tree parenthood here may jeopardize already configured clocks. 1266 * The sequence below ignores such DT directives with a friendly 1267 * debug trace. 1268 */ 1269 if (fdt_getprop(fdt, node, "st,clksrc", &len)) { 1270 DMSG("Ignore source clocks configuration from DT"); 1271 ignored++; 1272 } 1273 if (fdt_getprop(fdt, node, "st,clkdiv", &len)) { 1274 DMSG("Ignore clock divisors configuration from DT"); 1275 ignored++; 1276 } 1277 if (fdt_getprop(fdt, node, "st,pkcs", &len)) { 1278 DMSG("Ignore peripheral clocks tree configuration from DT"); 1279 ignored++; 1280 } 1281 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1282 char name[] = "st,pll@X"; 1283 1284 snprintf(name, sizeof(name), "st,pll@%d", i); 1285 node = fdt_subnode_offset(fdt, node, name); 1286 if (node < 0) 1287 continue; 1288 1289 if (fdt_getprop(fdt, node, "cfg", &len) || 1290 fdt_getprop(fdt, node, "frac", &len)) { 1291 DMSG("Ignore PLL%u configurations from DT", i); 1292 ignored++; 1293 } 1294 } 1295 1296 if (ignored != 0) 1297 IMSG("DT clock tree configurations were ignored"); 1298 1299 return TEE_SUCCESS; 1300 } 1301 1302 /* 1303 * Conversion between clk references and clock gates and clock on internals 1304 * 1305 * stm32mp1_clk first cells follow stm32mp1_clk_gate[] ordering. 1306 * stm32mp1_clk last cells follow stm32mp1_clk_on[] ordering. 1307 */ 1308 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) + 1309 ARRAY_SIZE(stm32mp1_clk_on)]; 1310 1311 #define CLK_ON_INDEX_OFFSET ((int)ARRAY_SIZE(stm32mp1_clk_gate)) 1312 1313 static bool clk_is_gate(struct clk *clk) 1314 { 1315 int clk_index = clk - stm32mp1_clk; 1316 1317 assert(clk_index >= 0 && clk_index < (int)ARRAY_SIZE(stm32mp1_clk)); 1318 return clk_index < CLK_ON_INDEX_OFFSET; 1319 } 1320 1321 static unsigned long clk_to_clock_id(struct clk *clk) 1322 { 1323 int gate_index = clk - stm32mp1_clk; 1324 int on_index = gate_index - CLK_ON_INDEX_OFFSET; 1325 1326 if (clk_is_gate(clk)) 1327 return stm32mp1_clk_gate[gate_index].clock_id; 1328 1329 return stm32mp1_clk_on[on_index]; 1330 } 1331 1332 static const struct stm32mp1_clk_gate *clk_to_gate_ref(struct clk *clk) 1333 { 1334 int gate_index = clk - stm32mp1_clk; 1335 1336 assert(clk_is_gate(clk)); 1337 1338 return stm32mp1_clk_gate + gate_index; 1339 } 1340 1341 static int clock_id_to_gate_index(unsigned long clock_id) 1342 { 1343 size_t n = 0; 1344 1345 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++) 1346 if (stm32mp1_clk_gate[n].clock_id == clock_id) 1347 return n; 1348 1349 return -1; 1350 } 1351 1352 static int clock_id_to_always_on_index(unsigned long clock_id) 1353 { 1354 size_t n = 0; 1355 1356 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++) 1357 if (stm32mp1_clk_on[n] == clock_id) 1358 return n; 1359 1360 return -1; 1361 } 1362 1363 static struct clk *clock_id_to_clk(unsigned long clock_id) 1364 { 1365 int gate_index = clock_id_to_gate_index(clock_id); 1366 int on_index = clock_id_to_always_on_index(clock_id); 1367 1368 if (gate_index >= 0) 1369 return stm32mp1_clk + gate_index; 1370 1371 if (on_index >= 0) 1372 return stm32mp1_clk + CLK_ON_INDEX_OFFSET + on_index; 1373 1374 return NULL; 1375 } 1376 1377 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id) 1378 { 1379 return clock_id_to_clk(clock_id); 1380 } 1381 1382 #if (CFG_TEE_CORE_LOG_LEVEL >= TRACE_DEBUG) && defined(CFG_TEE_CORE_DEBUG) 1383 struct clk_name { 1384 unsigned int clock_id; 1385 const char *name; 1386 }; 1387 1388 #define CLOCK_NAME(_binding, _name) \ 1389 { .clock_id = (_binding), .name = (_name) } 1390 1391 /* Store names only for some clocks */ 1392 const struct clk_name exposed_clk_name[] = { 1393 /* Clocks used by platform drivers not yet probed from DT */ 1394 CLOCK_NAME(CK_DBG, "dbg"), 1395 CLOCK_NAME(CK_MCU, "mcu"), 1396 CLOCK_NAME(RTCAPB, "rtcapb"), 1397 CLOCK_NAME(BKPSRAM, "bkpsram"), 1398 CLOCK_NAME(RTC, "rtc"), 1399 CLOCK_NAME(CRYP1, "crpy1"), 1400 CLOCK_NAME(SYSCFG, "syscfg"), 1401 CLOCK_NAME(GPIOA, "gpioa"), 1402 CLOCK_NAME(GPIOB, "gpiob"), 1403 CLOCK_NAME(GPIOC, "gpioc"), 1404 CLOCK_NAME(GPIOD, "gpiod"), 1405 CLOCK_NAME(GPIOE, "gpioe"), 1406 CLOCK_NAME(GPIOF, "gpiof"), 1407 CLOCK_NAME(GPIOG, "gpiog"), 1408 CLOCK_NAME(GPIOH, "gpioh"), 1409 CLOCK_NAME(GPIOI, "gpioi"), 1410 CLOCK_NAME(GPIOJ, "gpioj"), 1411 CLOCK_NAME(GPIOK, "gpiok"), 1412 CLOCK_NAME(GPIOZ, "gpioz"), 1413 /* Clock exposed by SCMI. SCMI clock fmro DT bindings to come... */ 1414 CLOCK_NAME(CK_HSE, "hse"), 1415 CLOCK_NAME(CK_HSI, "hsi"), 1416 CLOCK_NAME(CK_CSI, "csi"), 1417 CLOCK_NAME(CK_LSE, "lse"), 1418 CLOCK_NAME(CK_LSI, "lsi"), 1419 CLOCK_NAME(PLL2_Q, "pll2q"), 1420 CLOCK_NAME(PLL2_R, "pll2r"), 1421 CLOCK_NAME(PLL3_Q, "pll3q"), 1422 CLOCK_NAME(PLL3_R, "pll3r"), 1423 CLOCK_NAME(CRYP1, "cryp1"), 1424 CLOCK_NAME(HASH1, "hash1"), 1425 CLOCK_NAME(I2C4_K, "i2c4"), 1426 CLOCK_NAME(I2C6_K, "i2c6"), 1427 CLOCK_NAME(IWDG1, "iwdg"), 1428 CLOCK_NAME(RNG1_K, "rng1"), 1429 CLOCK_NAME(SPI6_K, "spi6"), 1430 CLOCK_NAME(USART1_K, "usart1"), 1431 CLOCK_NAME(CK_MCU, "mcu"), 1432 }; 1433 DECLARE_KEEP_PAGER(exposed_clk_name); 1434 1435 static const char *clk_op_get_name(struct clk *clk) 1436 { 1437 unsigned long clock_id = clk_to_clock_id(clk); 1438 size_t n = 0; 1439 1440 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++) 1441 if (exposed_clk_name[n].clock_id == clock_id) 1442 return exposed_clk_name[n].name; 1443 1444 return NULL; 1445 } 1446 #else 1447 static const char *clk_op_get_name(struct clk *clk __unused) 1448 { 1449 return NULL; 1450 } 1451 #endif /*CFG_TEE_CORE_LOG_LEVEL*/ 1452 1453 static unsigned long clk_op_compute_rate(struct clk *clk, 1454 unsigned long parent_rate __unused) 1455 { 1456 return _stm32_clock_get_rate(clk_to_clock_id(clk)); 1457 } 1458 1459 static TEE_Result clk_op_enable(struct clk *clk) 1460 { 1461 if (clk_is_gate(clk)) 1462 __clk_enable(clk_to_gate_ref(clk)); 1463 1464 return TEE_SUCCESS; 1465 } 1466 DECLARE_KEEP_PAGER(clk_op_enable); 1467 1468 static void clk_op_disable(struct clk *clk) 1469 { 1470 if (clk_is_gate(clk)) 1471 __clk_disable(clk_to_gate_ref(clk)); 1472 } 1473 DECLARE_KEEP_PAGER(clk_op_disable); 1474 1475 /* This variable is weak to break its dependency chain when linked as unpaged */ 1476 const struct clk_ops stm32mp1_clk_ops 1477 __weak __relrodata_unpaged("stm32mp1_clk_ops") = { 1478 .enable = clk_op_enable, 1479 .disable = clk_op_disable, 1480 .get_rate = clk_op_compute_rate, 1481 }; 1482 1483 static TEE_Result register_stm32mp1_clocks(void) 1484 { 1485 TEE_Result res = TEE_ERROR_GENERIC; 1486 size_t n = 0; 1487 1488 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk); n++) { 1489 stm32mp1_clk[n].ops = &stm32mp1_clk_ops; 1490 stm32mp1_clk[n].name = clk_op_get_name(stm32mp1_clk + n); 1491 refcount_set(&stm32mp1_clk[n].enabled_count, 0); 1492 1493 res = clk_register(stm32mp1_clk + n); 1494 if (res) 1495 return res; 1496 } 1497 1498 return TEE_SUCCESS; 1499 } 1500 1501 static struct clk *stm32mp1_clk_dt_get_clk(struct dt_driver_phandle_args *pargs, 1502 void *data __unused, TEE_Result *res) 1503 { 1504 unsigned long clock_id = pargs->args[0]; 1505 struct clk *clk = NULL; 1506 1507 *res = TEE_ERROR_BAD_PARAMETERS; 1508 1509 if (pargs->args_count != 1) 1510 return NULL; 1511 1512 clk = clock_id_to_clk(clock_id); 1513 if (!clk) 1514 return NULL; 1515 1516 *res = TEE_SUCCESS; 1517 return clk; 1518 } 1519 1520 /* Non-null reference for compat data */ 1521 static const uint8_t non_secure_rcc; 1522 1523 static TEE_Result stm32mp1_clock_provider_probe(const void *fdt, int offs, 1524 const void *compat_data) 1525 { 1526 TEE_Result res = TEE_ERROR_GENERIC; 1527 1528 if (compat_data == &non_secure_rcc) 1529 disable_rcc_tzen(); 1530 else 1531 enable_rcc_tzen(); 1532 1533 res = stm32mp1_clk_fdt_init(fdt, offs); 1534 if (res) { 1535 EMSG("Failed to initialize clocks from DT: %#"PRIx32, res); 1536 panic(); 1537 } 1538 1539 res = register_stm32mp1_clocks(); 1540 if (res) { 1541 EMSG("Failed to register clocks: %#"PRIx32, res); 1542 panic(); 1543 } 1544 1545 res = clk_dt_register_clk_provider(fdt, offs, stm32mp1_clk_dt_get_clk, 1546 NULL); 1547 if (res) { 1548 EMSG("Failed to register clock provider: %#"PRIx32, res); 1549 panic(); 1550 } 1551 1552 enable_static_secure_clocks(); 1553 1554 return TEE_SUCCESS; 1555 } 1556 1557 static const struct dt_device_match stm32mp1_clock_match_table[] = { 1558 { .compatible = "st,stm32mp1-rcc", .compat_data = &non_secure_rcc, }, 1559 { .compatible = "st,stm32mp1-rcc-secure", }, 1560 { } 1561 }; 1562 1563 DEFINE_DT_DRIVER(stm32mp1_clock_dt_driver) = { 1564 .name = "stm32mp1_clock", 1565 .type = DT_DRIVER_CLK, 1566 .match_table = stm32mp1_clock_match_table, 1567 .probe = stm32mp1_clock_provider_probe, 1568 }; 1569