1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0+) 2 /* 3 * Copyright (C) 2018-2022, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32mp1_rcc.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <drivers/stm32_shared_io.h> 12 #include <drivers/stm32mp_dt_bindings.h> 13 #include <initcall.h> 14 #include <io.h> 15 #include <keep.h> 16 #include <kernel/dt.h> 17 #include <kernel/boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/spinlock.h> 20 #include <libfdt.h> 21 #include <platform_config.h> 22 #include <stdio.h> 23 #include <stm32_util.h> 24 #include <trace.h> 25 #include <util.h> 26 27 /* Identifiers for root oscillators */ 28 enum stm32mp_osc_id { 29 OSC_HSI, 30 OSC_HSE, 31 OSC_CSI, 32 OSC_LSI, 33 OSC_LSE, 34 OSC_I2S_CKIN, 35 OSC_USB_PHY_48, 36 NB_OSC, 37 _UNKNOWN_OSC_ID = 0xffU 38 }; 39 40 /* Identifiers for parent clocks */ 41 enum stm32mp1_parent_id { 42 _HSI, 43 _HSE, 44 _CSI, 45 _LSI, 46 _LSE, 47 _I2S_CKIN, 48 _USB_PHY_48, 49 _HSI_KER, 50 _HSE_KER, 51 _HSE_KER_DIV2, 52 _HSE_RTC, 53 _CSI_KER, 54 _PLL1_P, 55 _PLL1_Q, 56 _PLL1_R, 57 _PLL2_P, 58 _PLL2_Q, 59 _PLL2_R, 60 _PLL3_P, 61 _PLL3_Q, 62 _PLL3_R, 63 _PLL4_P, 64 _PLL4_Q, 65 _PLL4_R, 66 _ACLK, 67 _PCLK1, 68 _PCLK2, 69 _PCLK3, 70 _PCLK4, 71 _PCLK5, 72 _HCLK5, 73 _HCLK6, 74 _HCLK2, 75 _CK_PER, 76 _CK_MPU, 77 _CK_MCU, 78 _PARENT_NB, 79 _UNKNOWN_ID = 0xff, 80 }; 81 82 /* 83 * Identifiers for parent clock selectors. 84 * This enum lists only the parent clocks we are interested in. 85 */ 86 enum stm32mp1_parent_sel { 87 _STGEN_SEL, 88 _I2C46_SEL, 89 _SPI6_SEL, 90 _USART1_SEL, 91 _RNG1_SEL, 92 _UART6_SEL, 93 _UART24_SEL, 94 _UART35_SEL, 95 _UART78_SEL, 96 _AXISS_SEL, 97 _MCUSS_SEL, 98 _USBPHY_SEL, 99 _USBO_SEL, 100 _RTC_SEL, 101 _MPU_SEL, 102 _PARENT_SEL_NB, 103 _UNKNOWN_SEL = 0xff, 104 }; 105 106 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 107 [_HSE] = CK_HSE, 108 [_HSI] = CK_HSI, 109 [_CSI] = CK_CSI, 110 [_LSE] = CK_LSE, 111 [_LSI] = CK_LSI, 112 [_I2S_CKIN] = _UNKNOWN_ID, 113 [_USB_PHY_48] = _UNKNOWN_ID, 114 [_HSI_KER] = CK_HSI, 115 [_HSE_KER] = CK_HSE, 116 [_HSE_KER_DIV2] = CK_HSE_DIV2, 117 [_HSE_RTC] = _UNKNOWN_ID, 118 [_CSI_KER] = CK_CSI, 119 [_PLL1_P] = PLL1_P, 120 [_PLL1_Q] = PLL1_Q, 121 [_PLL1_R] = PLL1_R, 122 [_PLL2_P] = PLL2_P, 123 [_PLL2_Q] = PLL2_Q, 124 [_PLL2_R] = PLL2_R, 125 [_PLL3_P] = PLL3_P, 126 [_PLL3_Q] = PLL3_Q, 127 [_PLL3_R] = PLL3_R, 128 [_PLL4_P] = PLL4_P, 129 [_PLL4_Q] = PLL4_Q, 130 [_PLL4_R] = PLL4_R, 131 [_ACLK] = CK_AXI, 132 [_PCLK1] = CK_AXI, 133 [_PCLK2] = CK_AXI, 134 [_PCLK3] = CK_AXI, 135 [_PCLK4] = CK_AXI, 136 [_PCLK5] = CK_AXI, 137 [_HCLK5] = CK_AXI, 138 [_HCLK6] = CK_AXI, 139 [_HCLK2] = CK_AXI, 140 [_CK_PER] = CK_PER, 141 [_CK_MPU] = CK_MPU, 142 [_CK_MCU] = CK_MCU, 143 }; 144 145 static enum stm32mp1_parent_id osc_id2parent_id(enum stm32mp_osc_id osc_id) 146 { 147 assert(osc_id >= OSC_HSI && osc_id < NB_OSC); 148 COMPILE_TIME_ASSERT((int)OSC_HSI == (int)_HSI && 149 (int)OSC_HSE == (int)_HSE && 150 (int)OSC_CSI == (int)_CSI && 151 (int)OSC_LSI == (int)_LSI && 152 (int)OSC_LSE == (int)_LSE && 153 (int)OSC_I2S_CKIN == (int)_I2S_CKIN && 154 (int)OSC_USB_PHY_48 == (int)_USB_PHY_48); 155 156 return (enum stm32mp1_parent_id)osc_id; 157 } 158 159 static enum stm32mp1_parent_id clock_id2parent_id(unsigned long id) 160 { 161 size_t n = 0; 162 163 COMPILE_TIME_ASSERT(STM32MP1_LAST_CLK < _UNKNOWN_ID); 164 165 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++) 166 if (parent_id_clock_id[n] == id) 167 return (enum stm32mp1_parent_id)n; 168 169 return _UNKNOWN_ID; 170 } 171 172 /* Identifiers for PLLs and their configuration resources */ 173 enum stm32mp1_pll_id { 174 _PLL1, 175 _PLL2, 176 _PLL3, 177 _PLL4, 178 _PLL_NB 179 }; 180 181 enum stm32mp1_div_id { 182 _DIV_P, 183 _DIV_Q, 184 _DIV_R, 185 _DIV_NB, 186 }; 187 188 enum stm32mp1_plltype { 189 PLL_800, 190 PLL_1600, 191 PLL_TYPE_NB 192 }; 193 194 /* 195 * Clock generic gates clocks which state is controlled by a single RCC bit 196 * 197 * @offset: RCC register byte offset from RCC base where clock is controlled 198 * @bit: Bit position in the RCC 32bit register 199 * @clock_id: Identifier used for the clock in the clock driver API 200 * @set_clr: Non-null if and only-if RCC register is a CLEAR/SET register 201 * (CLEAR register is at offset RCC_MP_ENCLRR_OFFSET from SET register) 202 * @secure: One of N_S or SEC, defined below 203 * @sel: _UNKNOWN_ID (fixed parent) or reference to parent clock selector 204 * (8bit storage of ID from enum stm32mp1_parent_sel) 205 * @fixed: _UNKNOWN_ID (selectable paranet) or reference to parent clock 206 * (8bit storage of ID from enum stm32mp1_parent_id) 207 */ 208 struct stm32mp1_clk_gate { 209 uint16_t offset; 210 uint8_t bit; 211 uint8_t clock_id; 212 uint8_t set_clr; 213 uint8_t secure; 214 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 215 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 216 }; 217 218 /* Parent clock selection: select register info, parent clocks references */ 219 struct stm32mp1_clk_sel { 220 uint16_t offset; 221 uint8_t src; 222 uint8_t msk; 223 uint8_t nb_parent; 224 const uint8_t *parent; 225 }; 226 227 #define REFCLK_SIZE 4 228 /* PLL control: type, control register offsets, up-to-4 selectable parent */ 229 struct stm32mp1_clk_pll { 230 enum stm32mp1_plltype plltype; 231 uint16_t rckxselr; 232 uint16_t pllxcfgr1; 233 uint16_t pllxcfgr2; 234 uint16_t pllxfracr; 235 uint16_t pllxcr; 236 uint16_t pllxcsgr; 237 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 238 }; 239 240 #define N_S 0 /* Non-secure can access RCC interface */ 241 #define SEC 1 /* RCC[TZEN] protects RCC interface */ 242 243 /* Clocks with selectable source and not set/clr register access */ 244 #define _CLK_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 245 { \ 246 .offset = (_offset), \ 247 .bit = (_bit), \ 248 .clock_id = (_clock_id), \ 249 .set_clr = 0, \ 250 .secure = (_sec), \ 251 .sel = (_parent_sel), \ 252 .fixed = _UNKNOWN_ID, \ 253 } 254 255 /* Clocks with fixed source and not set/clr register access */ 256 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 257 { \ 258 .offset = (_offset), \ 259 .bit = (_bit), \ 260 .clock_id = (_clock_id), \ 261 .set_clr = 0, \ 262 .secure = (_sec), \ 263 .sel = _UNKNOWN_SEL, \ 264 .fixed = (_parent), \ 265 } 266 267 /* Clocks with selectable source and set/clr register access */ 268 #define _CLK_SC_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 269 { \ 270 .offset = (_offset), \ 271 .bit = (_bit), \ 272 .clock_id = (_clock_id), \ 273 .set_clr = 1, \ 274 .secure = (_sec), \ 275 .sel = (_parent_sel), \ 276 .fixed = _UNKNOWN_ID, \ 277 } 278 279 /* Clocks with fixed source and set/clr register access */ 280 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 281 { \ 282 .offset = (_offset), \ 283 .bit = (_bit), \ 284 .clock_id = (_clock_id), \ 285 .set_clr = 1, \ 286 .secure = (_sec), \ 287 .sel = _UNKNOWN_SEL, \ 288 .fixed = (_parent), \ 289 } 290 291 /* 292 * Clocks with selectable source and set/clr register access 293 * and enable bit position defined by a label (argument _bit) 294 */ 295 #define _CLK_SC2_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 296 { \ 297 .offset = (_offset), \ 298 .clock_id = (_clock_id), \ 299 .bit = _offset ## _ ## _bit ## _POS, \ 300 .set_clr = 1, \ 301 .secure = (_sec), \ 302 .sel = (_parent_sel), \ 303 .fixed = _UNKNOWN_ID, \ 304 } 305 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 306 { \ 307 .offset = (_offset), \ 308 .clock_id = (_clock_id), \ 309 .bit = _offset ## _ ## _bit ## _POS, \ 310 .set_clr = 1, \ 311 .secure = (_sec), \ 312 .sel = _UNKNOWN_SEL, \ 313 .fixed = (_parent), \ 314 } 315 316 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ 317 [(idx)] = { \ 318 .offset = (_offset), \ 319 .src = (_src), \ 320 .msk = (_mask), \ 321 .parent = (_parent), \ 322 .nb_parent = ARRAY_SIZE(_parent) \ 323 } 324 325 #define _CLK_PLL(_idx, _type, _off1, _off2, _off3, _off4, \ 326 _off5, _off6, _p1, _p2, _p3, _p4) \ 327 [(_idx)] = { \ 328 .plltype = (_type), \ 329 .rckxselr = (_off1), \ 330 .pllxcfgr1 = (_off2), \ 331 .pllxcfgr2 = (_off3), \ 332 .pllxfracr = (_off4), \ 333 .pllxcr = (_off5), \ 334 .pllxcsgr = (_off6), \ 335 .refclk[0] = (_p1), \ 336 .refclk[1] = (_p2), \ 337 .refclk[2] = (_p3), \ 338 .refclk[3] = (_p4), \ 339 } 340 341 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 342 343 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 344 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 345 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 346 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 347 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 348 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 355 356 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, SPI6EN, SPI6_K, _SPI6_SEL), 357 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C4EN, I2C4_K, _I2C46_SEL), 358 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C6EN, I2C6_K, _I2C46_SEL), 359 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, USART1EN, USART1_K, _USART1_SEL), 360 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, RTCAPBEN, RTCAPB, _PCLK5), 361 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC1EN, TZC1, _PCLK5), 362 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC2EN, TZC2, _PCLK5), 363 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZPCEN, TZPC, _PCLK5), 364 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, IWDG1APBEN, IWDG1, _PCLK5), 365 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, BSECEN, BSEC, _PCLK5), 366 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, STGENEN, STGEN_K, _STGEN_SEL), 367 368 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5), 369 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5), 370 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5), 371 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL), 372 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _HCLK5), 373 374 _CLK_SC2_FIXED(SEC, RCC_MP_TZAHB6ENSETR, MDMA, MDMA, _HCLK6), 375 376 _CLK_SELEC(SEC, RCC_BDCR, RCC_BDCR_RTCCKEN_POS, RTC, _RTC_SEL), 377 378 /* Non-secure clocks */ 379 #ifdef CFG_WITH_NSEC_GPIOS 380 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_ID), 381 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_ID), 382 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_ID), 383 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_ID), 384 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_ID), 385 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_ID), 386 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_ID), 387 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_ID), 388 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_ID), 389 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_ID), 390 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_ID), 391 #endif 392 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 393 #ifdef CFG_WITH_NSEC_UARTS 394 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 395 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 396 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 397 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 398 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 399 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 400 #endif 401 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 402 #ifdef CFG_WITH_NSEC_UARTS 403 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 404 #endif 405 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 406 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 407 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 408 409 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 410 }; 411 DECLARE_KEEP_PAGER(stm32mp1_clk_gate); 412 413 const uint8_t stm32mp1_clk_on[] = { 414 CK_HSE, CK_CSI, CK_LSI, CK_LSE, CK_HSI, CK_HSE_DIV2, 415 PLL1_P, PLL1_Q, PLL1_R, PLL2_P, PLL2_Q, PLL2_R, PLL3_P, PLL3_Q, PLL3_R, 416 CK_AXI, CK_MPU, CK_MCU, 417 }; 418 419 /* Parents for secure aware clocks in the xxxSELR value ordering */ 420 static const uint8_t stgen_parents[] = { 421 _HSI_KER, _HSE_KER 422 }; 423 424 static const uint8_t i2c46_parents[] = { 425 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 426 }; 427 428 static const uint8_t spi6_parents[] = { 429 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 430 }; 431 432 static const uint8_t usart1_parents[] = { 433 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 434 }; 435 436 static const uint8_t rng1_parents[] = { 437 _CSI, _PLL4_R, _LSE, _LSI 438 }; 439 440 static const uint8_t mpu_parents[] = { 441 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 442 }; 443 444 /* Parents for (some) non-secure clocks */ 445 #ifdef CFG_WITH_NSEC_UARTS 446 static const uint8_t uart6_parents[] = { 447 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 448 }; 449 450 static const uint8_t uart234578_parents[] = { 451 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 452 }; 453 #endif 454 455 static const uint8_t axiss_parents[] = { 456 _HSI, _HSE, _PLL2_P 457 }; 458 459 static const uint8_t mcuss_parents[] = { 460 _HSI, _HSE, _CSI, _PLL3_P 461 }; 462 463 static const uint8_t rtc_parents[] = { 464 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 465 }; 466 467 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 468 /* Secure aware clocks */ 469 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 470 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 471 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), 472 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), 473 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), 474 _CLK_PARENT(_RTC_SEL, RCC_BDCR, 16, 0x3, rtc_parents), 475 _CLK_PARENT(_MPU_SEL, RCC_MPCKSELR, 0, 0x3, mpu_parents), 476 /* Always non-secure clocks (maybe used in some way in secure world) */ 477 #ifdef CFG_WITH_NSEC_UARTS 478 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 479 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), 480 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), 481 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), 482 #endif 483 _CLK_PARENT(_AXISS_SEL, RCC_ASSCKSELR, 0, 0x3, axiss_parents), 484 _CLK_PARENT(_MCUSS_SEL, RCC_MSSCKSELR, 0, 0x3, mcuss_parents), 485 }; 486 487 /* PLLNCFGR2 register divider by output */ 488 static const uint8_t pllncfgr2[_DIV_NB] = { 489 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 490 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 491 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 492 }; 493 494 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 495 _CLK_PLL(_PLL1, PLL_1600, 496 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 497 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 498 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 499 _CLK_PLL(_PLL2, PLL_1600, 500 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 501 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 502 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 503 _CLK_PLL(_PLL3, PLL_800, 504 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 505 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 506 OSC_HSI, OSC_HSE, OSC_CSI, _UNKNOWN_OSC_ID), 507 _CLK_PLL(_PLL4, PLL_800, 508 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 509 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 510 OSC_HSI, OSC_HSE, OSC_CSI, OSC_I2S_CKIN), 511 }; 512 513 /* Prescaler table lookups for clock computation */ 514 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 515 static const uint8_t stm32mp1_mcu_div[16] = { 516 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 517 }; 518 519 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 520 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 521 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 522 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 523 0, 1, 2, 3, 4, 4, 4, 4 524 }; 525 526 /* div = /1 /2 /3 /4 */ 527 static const uint8_t stm32mp1_axi_div[8] = { 528 1, 2, 3, 4, 4, 4, 4, 4 529 }; 530 531 static const char __maybe_unused *const stm32mp1_clk_parent_name[_PARENT_NB] = { 532 [_HSI] = "HSI", 533 [_HSE] = "HSE", 534 [_CSI] = "CSI", 535 [_LSI] = "LSI", 536 [_LSE] = "LSE", 537 [_I2S_CKIN] = "I2S_CKIN", 538 [_HSI_KER] = "HSI_KER", 539 [_HSE_KER] = "HSE_KER", 540 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 541 [_HSE_RTC] = "HSE_RTC", 542 [_CSI_KER] = "CSI_KER", 543 [_PLL1_P] = "PLL1_P", 544 [_PLL1_Q] = "PLL1_Q", 545 [_PLL1_R] = "PLL1_R", 546 [_PLL2_P] = "PLL2_P", 547 [_PLL2_Q] = "PLL2_Q", 548 [_PLL2_R] = "PLL2_R", 549 [_PLL3_P] = "PLL3_P", 550 [_PLL3_Q] = "PLL3_Q", 551 [_PLL3_R] = "PLL3_R", 552 [_PLL4_P] = "PLL4_P", 553 [_PLL4_Q] = "PLL4_Q", 554 [_PLL4_R] = "PLL4_R", 555 [_ACLK] = "ACLK", 556 [_PCLK1] = "PCLK1", 557 [_PCLK2] = "PCLK2", 558 [_PCLK3] = "PCLK3", 559 [_PCLK4] = "PCLK4", 560 [_PCLK5] = "PCLK5", 561 [_HCLK2] = "HCLK2", 562 [_HCLK5] = "HCLK5", 563 [_HCLK6] = "HCLK6", 564 [_CK_PER] = "CK_PER", 565 [_CK_MPU] = "CK_MPU", 566 [_CK_MCU] = "CK_MCU", 567 [_USB_PHY_48] = "USB_PHY_48", 568 }; 569 570 /* 571 * Oscillator frequency in Hz. This array shall be initialized 572 * according to platform. 573 */ 574 static unsigned long stm32mp1_osc[NB_OSC]; 575 576 static unsigned long osc_frequency(enum stm32mp_osc_id idx) 577 { 578 if (idx >= ARRAY_SIZE(stm32mp1_osc)) { 579 DMSG("clk id %d not found", idx); 580 return 0; 581 } 582 583 return stm32mp1_osc[idx]; 584 } 585 586 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 587 { 588 return &stm32mp1_clk_gate[idx]; 589 } 590 591 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 592 { 593 return &stm32mp1_clk_sel[idx]; 594 } 595 596 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 597 { 598 return &stm32mp1_clk_pll[idx]; 599 } 600 601 static int stm32mp1_clk_get_gated_id(unsigned long id) 602 { 603 unsigned int i = 0; 604 605 for (i = 0; i < NB_GATES; i++) 606 if (gate_ref(i)->clock_id == id) 607 return i; 608 609 DMSG("clk id %lu not found", id); 610 return -1; 611 } 612 613 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 614 { 615 return (enum stm32mp1_parent_sel)gate_ref(i)->sel; 616 } 617 618 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 619 { 620 return (enum stm32mp1_parent_id)gate_ref(i)->fixed; 621 } 622 623 static int stm32mp1_clk_get_parent(unsigned long id) 624 { 625 const struct stm32mp1_clk_sel *sel = NULL; 626 enum stm32mp1_parent_id parent_id = 0; 627 uint32_t p_sel = 0; 628 int i = 0; 629 enum stm32mp1_parent_id p = _UNKNOWN_ID; 630 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 631 vaddr_t rcc_base = stm32_rcc_base(); 632 633 parent_id = clock_id2parent_id(id); 634 if (parent_id != _UNKNOWN_ID) 635 return (int)parent_id; 636 637 i = stm32mp1_clk_get_gated_id(id); 638 if (i < 0) 639 panic(); 640 641 p = stm32mp1_clk_get_fixed_parent(i); 642 if (p < _PARENT_NB) 643 return (int)p; 644 645 s = stm32mp1_clk_get_sel(i); 646 if (s == _UNKNOWN_SEL) 647 return -1; 648 if (s >= _PARENT_SEL_NB) 649 panic(); 650 651 sel = clk_sel_ref(s); 652 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & sel->msk; 653 if (p_sel < sel->nb_parent) 654 return (int)sel->parent[p_sel]; 655 656 DMSG("No parent selected for clk %lu", id); 657 return -1; 658 } 659 660 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 661 { 662 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr); 663 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 664 665 return osc_frequency(pll->refclk[src]); 666 } 667 668 /* 669 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 670 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 671 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 672 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 673 */ 674 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 675 { 676 unsigned long refclk = 0; 677 unsigned long fvco = 0; 678 uint32_t cfgr1 = 0; 679 uint32_t fracr = 0; 680 uint32_t divm = 0; 681 uint32_t divn = 0; 682 683 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); 684 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); 685 686 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT; 687 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 688 689 refclk = stm32mp1_pll_get_fref(pll); 690 691 /* 692 * With FRACV : 693 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 694 * Without FRACV 695 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 696 */ 697 if (fracr & RCC_PLLNFRACR_FRACLE) { 698 unsigned long long numerator = 0; 699 unsigned long long denominator = 0; 700 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 701 RCC_PLLNFRACR_FRACV_SHIFT; 702 703 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 704 numerator = refclk * numerator; 705 denominator = ((unsigned long long)divm + 1U) << 13; 706 fvco = (unsigned long)(numerator / denominator); 707 } else { 708 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 709 } 710 711 return fvco; 712 } 713 714 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 715 enum stm32mp1_div_id div_id) 716 { 717 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 718 unsigned long dfout = 0; 719 uint32_t cfgr2 = 0; 720 uint32_t divy = 0; 721 722 if (div_id >= _DIV_NB) 723 return 0; 724 725 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); 726 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 727 728 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 729 730 return dfout; 731 } 732 733 static unsigned long get_clock_rate(enum stm32mp1_parent_id p) 734 { 735 uint32_t reg = 0; 736 unsigned long clock = 0; 737 vaddr_t rcc_base = stm32_rcc_base(); 738 739 switch (p) { 740 case _CK_MPU: 741 /* MPU sub system */ 742 reg = io_read32(rcc_base + RCC_MPCKSELR); 743 switch (reg & RCC_SELR_SRC_MASK) { 744 case RCC_MPCKSELR_HSI: 745 clock = osc_frequency(OSC_HSI); 746 break; 747 case RCC_MPCKSELR_HSE: 748 clock = osc_frequency(OSC_HSE); 749 break; 750 case RCC_MPCKSELR_PLL: 751 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 752 break; 753 case RCC_MPCKSELR_PLL_MPUDIV: 754 reg = io_read32(rcc_base + RCC_MPCKDIVR); 755 if (reg & RCC_MPUDIV_MASK) 756 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> 757 stm32mp1_mpu_div[reg & RCC_MPUDIV_MASK]; 758 else 759 clock = 0; 760 break; 761 default: 762 break; 763 } 764 break; 765 /* AXI sub system */ 766 case _ACLK: 767 case _HCLK2: 768 case _HCLK5: 769 case _HCLK6: 770 case _PCLK4: 771 case _PCLK5: 772 reg = io_read32(rcc_base + RCC_ASSCKSELR); 773 switch (reg & RCC_SELR_SRC_MASK) { 774 case RCC_ASSCKSELR_HSI: 775 clock = osc_frequency(OSC_HSI); 776 break; 777 case RCC_ASSCKSELR_HSE: 778 clock = osc_frequency(OSC_HSE); 779 break; 780 case RCC_ASSCKSELR_PLL: 781 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 782 break; 783 default: 784 break; 785 } 786 787 /* System clock divider */ 788 reg = io_read32(rcc_base + RCC_AXIDIVR); 789 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 790 791 switch (p) { 792 case _PCLK4: 793 reg = io_read32(rcc_base + RCC_APB4DIVR); 794 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 795 break; 796 case _PCLK5: 797 reg = io_read32(rcc_base + RCC_APB5DIVR); 798 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 799 break; 800 default: 801 break; 802 } 803 break; 804 /* MCU sub system */ 805 case _CK_MCU: 806 case _PCLK1: 807 case _PCLK2: 808 case _PCLK3: 809 reg = io_read32(rcc_base + RCC_MSSCKSELR); 810 switch (reg & RCC_SELR_SRC_MASK) { 811 case RCC_MSSCKSELR_HSI: 812 clock = osc_frequency(OSC_HSI); 813 break; 814 case RCC_MSSCKSELR_HSE: 815 clock = osc_frequency(OSC_HSE); 816 break; 817 case RCC_MSSCKSELR_CSI: 818 clock = osc_frequency(OSC_CSI); 819 break; 820 case RCC_MSSCKSELR_PLL: 821 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 822 break; 823 default: 824 break; 825 } 826 827 /* MCU clock divider */ 828 reg = io_read32(rcc_base + RCC_MCUDIVR); 829 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 830 831 switch (p) { 832 case _PCLK1: 833 reg = io_read32(rcc_base + RCC_APB1DIVR); 834 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 835 break; 836 case _PCLK2: 837 reg = io_read32(rcc_base + RCC_APB2DIVR); 838 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 839 break; 840 case _PCLK3: 841 reg = io_read32(rcc_base + RCC_APB3DIVR); 842 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 843 break; 844 case _CK_MCU: 845 default: 846 break; 847 } 848 break; 849 case _CK_PER: 850 reg = io_read32(rcc_base + RCC_CPERCKSELR); 851 switch (reg & RCC_SELR_SRC_MASK) { 852 case RCC_CPERCKSELR_HSI: 853 clock = osc_frequency(OSC_HSI); 854 break; 855 case RCC_CPERCKSELR_HSE: 856 clock = osc_frequency(OSC_HSE); 857 break; 858 case RCC_CPERCKSELR_CSI: 859 clock = osc_frequency(OSC_CSI); 860 break; 861 default: 862 break; 863 } 864 break; 865 case _HSI: 866 case _HSI_KER: 867 clock = osc_frequency(OSC_HSI); 868 break; 869 case _CSI: 870 case _CSI_KER: 871 clock = osc_frequency(OSC_CSI); 872 break; 873 case _HSE: 874 case _HSE_KER: 875 clock = osc_frequency(OSC_HSE); 876 break; 877 case _HSE_KER_DIV2: 878 clock = osc_frequency(OSC_HSE) >> 1; 879 break; 880 case _HSE_RTC: 881 clock = osc_frequency(OSC_HSE); 882 clock /= (io_read32(rcc_base + RCC_RTCDIVR) & 883 RCC_DIVR_DIV_MASK) + 1; 884 break; 885 case _LSI: 886 clock = osc_frequency(OSC_LSI); 887 break; 888 case _LSE: 889 clock = osc_frequency(OSC_LSE); 890 break; 891 /* PLL */ 892 case _PLL1_P: 893 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 894 break; 895 case _PLL1_Q: 896 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 897 break; 898 case _PLL1_R: 899 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 900 break; 901 case _PLL2_P: 902 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 903 break; 904 case _PLL2_Q: 905 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 906 break; 907 case _PLL2_R: 908 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 909 break; 910 case _PLL3_P: 911 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 912 break; 913 case _PLL3_Q: 914 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 915 break; 916 case _PLL3_R: 917 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 918 break; 919 case _PLL4_P: 920 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 921 break; 922 case _PLL4_Q: 923 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 924 break; 925 case _PLL4_R: 926 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 927 break; 928 /* Other */ 929 case _USB_PHY_48: 930 clock = osc_frequency(OSC_USB_PHY_48); 931 break; 932 default: 933 break; 934 } 935 936 return clock; 937 } 938 939 static void __clk_enable(const struct stm32mp1_clk_gate *gate) 940 { 941 vaddr_t base = stm32_rcc_base(); 942 uint32_t bit = BIT(gate->bit); 943 944 if (gate->set_clr) 945 io_write32(base + gate->offset, bit); 946 else 947 io_setbits32_stm32shregs(base + gate->offset, bit); 948 949 FMSG("Clock %u has been enabled", gate->clock_id); 950 } 951 952 static void __clk_disable(const struct stm32mp1_clk_gate *gate) 953 { 954 vaddr_t base = stm32_rcc_base(); 955 uint32_t bit = BIT(gate->bit); 956 957 if (gate->set_clr) 958 io_write32(base + gate->offset + RCC_MP_ENCLRR_OFFSET, bit); 959 else 960 io_clrbits32_stm32shregs(base + gate->offset, bit); 961 962 FMSG("Clock %u has been disabled", gate->clock_id); 963 } 964 965 static long get_timer_rate(long parent_rate, unsigned int apb_bus) 966 { 967 uint32_t timgxpre = 0; 968 uint32_t apbxdiv = 0; 969 vaddr_t rcc_base = stm32_rcc_base(); 970 971 switch (apb_bus) { 972 case 1: 973 apbxdiv = io_read32(rcc_base + RCC_APB1DIVR) & 974 RCC_APBXDIV_MASK; 975 timgxpre = io_read32(rcc_base + RCC_TIMG1PRER) & 976 RCC_TIMGXPRER_TIMGXPRE; 977 break; 978 case 2: 979 apbxdiv = io_read32(rcc_base + RCC_APB2DIVR) & 980 RCC_APBXDIV_MASK; 981 timgxpre = io_read32(rcc_base + RCC_TIMG2PRER) & 982 RCC_TIMGXPRER_TIMGXPRE; 983 break; 984 default: 985 panic(); 986 break; 987 } 988 989 if (apbxdiv == 0) 990 return parent_rate; 991 992 return parent_rate * (timgxpre + 1) * 2; 993 } 994 995 static unsigned long _stm32_clock_get_rate(unsigned long id) 996 { 997 enum stm32mp1_parent_id p = _UNKNOWN_ID; 998 unsigned long rate = 0; 999 1000 p = stm32mp1_clk_get_parent(id); 1001 if (p < 0) 1002 return 0; 1003 1004 rate = get_clock_rate(p); 1005 1006 if ((id >= TIM2_K) && (id <= TIM14_K)) 1007 rate = get_timer_rate(rate, 1); 1008 1009 if ((id >= TIM1_K) && (id <= TIM17_K)) 1010 rate = get_timer_rate(rate, 2); 1011 1012 return rate; 1013 } 1014 1015 /* 1016 * Get the parent ID of the target parent clock, or -1 if no parent found. 1017 */ 1018 static enum stm32mp1_parent_id get_parent_id_parent(enum stm32mp1_parent_id id) 1019 { 1020 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 1021 enum stm32mp1_pll_id pll_id = _PLL_NB; 1022 uint32_t p_sel = 0; 1023 1024 switch (id) { 1025 case _ACLK: 1026 case _HCLK5: 1027 case _HCLK6: 1028 case _PCLK4: 1029 case _PCLK5: 1030 s = _AXISS_SEL; 1031 break; 1032 case _PLL1_P: 1033 case _PLL1_Q: 1034 case _PLL1_R: 1035 pll_id = _PLL1; 1036 break; 1037 case _PLL2_P: 1038 case _PLL2_Q: 1039 case _PLL2_R: 1040 pll_id = _PLL2; 1041 break; 1042 case _PLL3_P: 1043 case _PLL3_Q: 1044 case _PLL3_R: 1045 pll_id = _PLL3; 1046 break; 1047 case _PLL4_P: 1048 case _PLL4_Q: 1049 case _PLL4_R: 1050 pll_id = _PLL4; 1051 break; 1052 case _PCLK1: 1053 case _PCLK2: 1054 case _HCLK2: 1055 case _CK_PER: 1056 case _CK_MPU: 1057 case _CK_MCU: 1058 case _USB_PHY_48: 1059 /* We do not expected to access these */ 1060 panic(); 1061 break; 1062 default: 1063 /* Other parents have no parent */ 1064 return -1; 1065 } 1066 1067 if (s != _UNKNOWN_SEL) { 1068 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 1069 vaddr_t rcc_base = stm32_rcc_base(); 1070 1071 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & 1072 sel->msk; 1073 1074 if (p_sel < sel->nb_parent) 1075 return sel->parent[p_sel]; 1076 } else { 1077 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1078 1079 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & 1080 RCC_SELR_REFCLK_SRC_MASK; 1081 1082 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) 1083 return osc_id2parent_id(pll->refclk[p_sel]); 1084 } 1085 1086 FMSG("No parent found for %s", stm32mp1_clk_parent_name[id]); 1087 return -1; 1088 } 1089 1090 /* We are only interested in knowing if PLL3 shall be secure or not */ 1091 static void secure_parent_clocks(enum stm32mp1_parent_id parent_id) 1092 { 1093 enum stm32mp1_parent_id grandparent_id = _UNKNOWN_ID; 1094 1095 switch (parent_id) { 1096 case _ACLK: 1097 case _HCLK2: 1098 case _HCLK5: 1099 case _HCLK6: 1100 case _PCLK4: 1101 case _PCLK5: 1102 /* Intermediate clock mux or clock, go deeper in clock tree */ 1103 break; 1104 case _HSI: 1105 case _HSI_KER: 1106 case _LSI: 1107 case _CSI: 1108 case _CSI_KER: 1109 case _HSE: 1110 case _HSE_KER: 1111 case _HSE_KER_DIV2: 1112 case _HSE_RTC: 1113 case _LSE: 1114 case _PLL1_P: 1115 case _PLL1_Q: 1116 case _PLL1_R: 1117 case _PLL2_P: 1118 case _PLL2_Q: 1119 case _PLL2_R: 1120 /* Always secure clocks, no need to go further */ 1121 return; 1122 case _PLL3_P: 1123 case _PLL3_Q: 1124 case _PLL3_R: 1125 /* PLL3 is a shared resource, registered and don't go further */ 1126 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 1127 return; 1128 default: 1129 DMSG("Cannot lookup parent clock %s", 1130 stm32mp1_clk_parent_name[parent_id]); 1131 panic(); 1132 } 1133 1134 grandparent_id = get_parent_id_parent(parent_id); 1135 if (grandparent_id >= 0) 1136 secure_parent_clocks(grandparent_id); 1137 } 1138 1139 void stm32mp_register_clock_parents_secure(unsigned long clock_id) 1140 { 1141 enum stm32mp1_parent_id parent_id = stm32mp1_clk_get_parent(clock_id); 1142 1143 if (parent_id < 0) { 1144 DMSG("No parent for clock %lu", clock_id); 1145 return; 1146 } 1147 1148 secure_parent_clocks(parent_id); 1149 } 1150 1151 #ifdef CFG_EMBED_DTB 1152 static const char *stm32mp_osc_node_label[NB_OSC] = { 1153 [OSC_LSI] = "clk-lsi", 1154 [OSC_LSE] = "clk-lse", 1155 [OSC_HSI] = "clk-hsi", 1156 [OSC_HSE] = "clk-hse", 1157 [OSC_CSI] = "clk-csi", 1158 [OSC_I2S_CKIN] = "i2s_ckin", 1159 [OSC_USB_PHY_48] = "ck_usbo_48m" 1160 }; 1161 1162 static unsigned int clk_freq_prop(const void *fdt, int node) 1163 { 1164 const fdt32_t *cuint = NULL; 1165 int ret = 0; 1166 1167 /* Disabled clocks report null rate */ 1168 if (_fdt_get_status(fdt, node) == DT_STATUS_DISABLED) 1169 return 0; 1170 1171 cuint = fdt_getprop(fdt, node, "clock-frequency", &ret); 1172 if (!cuint) 1173 panic(); 1174 1175 return fdt32_to_cpu(*cuint); 1176 } 1177 1178 static void get_osc_freq_from_dt(const void *fdt) 1179 { 1180 enum stm32mp_osc_id idx = _UNKNOWN_OSC_ID; 1181 int clk_node = fdt_path_offset(fdt, "/clocks"); 1182 1183 if (clk_node < 0) 1184 panic(); 1185 1186 COMPILE_TIME_ASSERT((int)OSC_HSI == 0); 1187 for (idx = OSC_HSI; idx < NB_OSC; idx++) { 1188 const char *name = stm32mp_osc_node_label[idx]; 1189 int subnode = 0; 1190 1191 fdt_for_each_subnode(subnode, fdt, clk_node) { 1192 const char *cchar = NULL; 1193 int ret = 0; 1194 1195 cchar = fdt_get_name(fdt, subnode, &ret); 1196 if (!cchar) 1197 panic(); 1198 1199 if (strncmp(cchar, name, (size_t)ret) == 0) { 1200 stm32mp1_osc[idx] = clk_freq_prop(fdt, subnode); 1201 1202 DMSG("Osc %s: %lu Hz", name, stm32mp1_osc[idx]); 1203 break; 1204 } 1205 } 1206 1207 if (!stm32mp1_osc[idx]) 1208 DMSG("Osc %s: no frequency info", name); 1209 } 1210 } 1211 #endif /*CFG_EMBED_DTB*/ 1212 1213 static void enable_static_secure_clocks(void) 1214 { 1215 unsigned int idx = 0; 1216 const unsigned long secure_enable[] = { 1217 DDRC1, DDRC1LP, DDRC2, DDRC2LP, DDRPHYC, DDRPHYCLP, DDRCAPB, 1218 AXIDCG, DDRPHYCAPB, DDRPHYCAPBLP, TZPC, TZC1, TZC2, STGEN_K, 1219 BSEC, 1220 }; 1221 1222 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++) { 1223 clk_enable(stm32mp_rcc_clock_id_to_clk(secure_enable[idx])); 1224 stm32mp_register_clock_parents_secure(secure_enable[idx]); 1225 } 1226 1227 if (CFG_TEE_CORE_NB_CORE > 1) 1228 clk_enable(stm32mp_rcc_clock_id_to_clk(RTCAPB)); 1229 } 1230 1231 static void __maybe_unused enable_rcc_tzen(void) 1232 { 1233 io_setbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1234 } 1235 1236 static void __maybe_unused disable_rcc_tzen(void) 1237 { 1238 IMSG("RCC is non-secure"); 1239 io_clrbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1240 } 1241 1242 #ifdef CFG_EMBED_DTB 1243 static TEE_Result stm32mp1_clk_fdt_init(const void *fdt, int node) 1244 { 1245 unsigned int i = 0; 1246 int len = 0; 1247 int ignored = 0; 1248 1249 get_osc_freq_from_dt(fdt); 1250 1251 /* 1252 * OP-TEE core is not in charge of configuring clock parenthood. 1253 * This is expected from an earlier boot stage. Modifying the clock 1254 * tree parenthood here may jeopardize already configured clocks. 1255 * The sequence below ignores such DT directives with a friendly 1256 * debug trace. 1257 */ 1258 if (fdt_getprop(fdt, node, "st,clksrc", &len)) { 1259 DMSG("Ignore source clocks configuration from DT"); 1260 ignored++; 1261 } 1262 if (fdt_getprop(fdt, node, "st,clkdiv", &len)) { 1263 DMSG("Ignore clock divisors configuration from DT"); 1264 ignored++; 1265 } 1266 if (fdt_getprop(fdt, node, "st,pkcs", &len)) { 1267 DMSG("Ignore peripheral clocks tree configuration from DT"); 1268 ignored++; 1269 } 1270 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1271 char name[] = "st,pll@X"; 1272 1273 snprintf(name, sizeof(name), "st,pll@%d", i); 1274 node = fdt_subnode_offset(fdt, node, name); 1275 if (node < 0) 1276 continue; 1277 1278 if (fdt_getprop(fdt, node, "cfg", &len) || 1279 fdt_getprop(fdt, node, "frac", &len)) { 1280 DMSG("Ignore PLL%u configurations from DT", i); 1281 ignored++; 1282 } 1283 } 1284 1285 if (ignored != 0) 1286 IMSG("DT clock tree configurations were ignored"); 1287 1288 return TEE_SUCCESS; 1289 } 1290 #endif /*CFG_EMBED_DTB*/ 1291 1292 /* 1293 * Conversion between clk references and clock gates and clock on internals 1294 * 1295 * stm32mp1_clk first cells follow stm32mp1_clk_gate[] ordering. 1296 * stm32mp1_clk last cells follow stm32mp1_clk_on[] ordering. 1297 */ 1298 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) + 1299 ARRAY_SIZE(stm32mp1_clk_on)]; 1300 1301 #define CLK_ON_INDEX_OFFSET ((int)ARRAY_SIZE(stm32mp1_clk_gate)) 1302 1303 static bool clk_is_gate(struct clk *clk) 1304 { 1305 int clk_index = clk - stm32mp1_clk; 1306 1307 assert(clk_index >= 0 && clk_index < (int)ARRAY_SIZE(stm32mp1_clk)); 1308 return clk_index < CLK_ON_INDEX_OFFSET; 1309 } 1310 1311 static unsigned long clk_to_clock_id(struct clk *clk) 1312 { 1313 int gate_index = clk - stm32mp1_clk; 1314 int on_index = gate_index - CLK_ON_INDEX_OFFSET; 1315 1316 if (clk_is_gate(clk)) 1317 return stm32mp1_clk_gate[gate_index].clock_id; 1318 1319 return stm32mp1_clk_on[on_index]; 1320 } 1321 1322 static const struct stm32mp1_clk_gate *clk_to_gate_ref(struct clk *clk) 1323 { 1324 int gate_index = clk - stm32mp1_clk; 1325 1326 assert(clk_is_gate(clk)); 1327 1328 return stm32mp1_clk_gate + gate_index; 1329 } 1330 1331 static int clock_id_to_gate_index(unsigned long clock_id) 1332 { 1333 size_t n = 0; 1334 1335 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++) 1336 if (stm32mp1_clk_gate[n].clock_id == clock_id) 1337 return n; 1338 1339 return -1; 1340 } 1341 1342 static int clock_id_to_always_on_index(unsigned long clock_id) 1343 { 1344 size_t n = 0; 1345 1346 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++) 1347 if (stm32mp1_clk_on[n] == clock_id) 1348 return n; 1349 1350 return -1; 1351 } 1352 1353 static struct clk *clock_id_to_clk(unsigned long clock_id) 1354 { 1355 int gate_index = clock_id_to_gate_index(clock_id); 1356 int on_index = clock_id_to_always_on_index(clock_id); 1357 1358 if (gate_index >= 0) 1359 return stm32mp1_clk + gate_index; 1360 1361 if (on_index >= 0) 1362 return stm32mp1_clk + CLK_ON_INDEX_OFFSET + on_index; 1363 1364 return NULL; 1365 } 1366 1367 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id) 1368 { 1369 return clock_id_to_clk(clock_id); 1370 } 1371 1372 #if CFG_TEE_CORE_LOG_LEVEL >= TRACE_DEBUG 1373 struct clk_name { 1374 unsigned int clock_id; 1375 const char *name; 1376 }; 1377 1378 #define CLOCK_NAME(_binding, _name) \ 1379 { .clock_id = (_binding), .name = (_name) } 1380 1381 /* Store names only for some clocks */ 1382 const struct clk_name exposed_clk_name[] = { 1383 /* Clocks used by platform drivers not yet probed from DT */ 1384 CLOCK_NAME(CK_DBG, "dbg"), 1385 CLOCK_NAME(CK_MCU, "mcu"), 1386 CLOCK_NAME(RTCAPB, "rtcapb"), 1387 CLOCK_NAME(BKPSRAM, "bkpsram"), 1388 CLOCK_NAME(RTC, "rtc"), 1389 CLOCK_NAME(CRYP1, "crpy1"), 1390 CLOCK_NAME(SYSCFG, "syscfg"), 1391 CLOCK_NAME(GPIOA, "gpioa"), 1392 CLOCK_NAME(GPIOB, "gpiob"), 1393 CLOCK_NAME(GPIOC, "gpioc"), 1394 CLOCK_NAME(GPIOD, "gpiod"), 1395 CLOCK_NAME(GPIOE, "gpioe"), 1396 CLOCK_NAME(GPIOF, "gpiof"), 1397 CLOCK_NAME(GPIOG, "gpiog"), 1398 CLOCK_NAME(GPIOH, "gpioh"), 1399 CLOCK_NAME(GPIOI, "gpioi"), 1400 CLOCK_NAME(GPIOJ, "gpioj"), 1401 CLOCK_NAME(GPIOK, "gpiok"), 1402 CLOCK_NAME(GPIOZ, "gpioz"), 1403 /* Clock exposed by SCMI. SCMI clock fmro DT bindings to come... */ 1404 CLOCK_NAME(CK_HSE, "hse"), 1405 CLOCK_NAME(CK_HSI, "hsi"), 1406 CLOCK_NAME(CK_CSI, "csi"), 1407 CLOCK_NAME(CK_LSE, "lse"), 1408 CLOCK_NAME(CK_LSI, "lsi"), 1409 CLOCK_NAME(PLL2_Q, "pll2q"), 1410 CLOCK_NAME(PLL2_R, "pll2r"), 1411 CLOCK_NAME(PLL3_Q, "pll3q"), 1412 CLOCK_NAME(PLL3_R, "pll3r"), 1413 CLOCK_NAME(CRYP1, "cryp1"), 1414 CLOCK_NAME(HASH1, "hash1"), 1415 CLOCK_NAME(I2C4_K, "i2c4"), 1416 CLOCK_NAME(I2C6_K, "i2c6"), 1417 CLOCK_NAME(IWDG1, "iwdg"), 1418 CLOCK_NAME(RNG1_K, "rng1"), 1419 CLOCK_NAME(SPI6_K, "spi6"), 1420 CLOCK_NAME(USART1_K, "usart1"), 1421 CLOCK_NAME(CK_MCU, "mcu"), 1422 }; 1423 DECLARE_KEEP_PAGER(exposed_clk_name); 1424 1425 static const char *clk_op_get_name(struct clk *clk) 1426 { 1427 unsigned long clock_id = clk_to_clock_id(clk); 1428 size_t n = 0; 1429 1430 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++) 1431 if (exposed_clk_name[n].clock_id == clock_id) 1432 return exposed_clk_name[n].name; 1433 1434 return NULL; 1435 } 1436 #else 1437 static const char *clk_op_get_name(struct clk *clk __unused) 1438 { 1439 return NULL; 1440 } 1441 #endif /*CFG_TEE_CORE_LOG_LEVEL*/ 1442 1443 static unsigned long clk_op_compute_rate(struct clk *clk, 1444 unsigned long parent_rate __unused) 1445 { 1446 return _stm32_clock_get_rate(clk_to_clock_id(clk)); 1447 } 1448 1449 static TEE_Result clk_op_enable(struct clk *clk) 1450 { 1451 if (clk_is_gate(clk)) 1452 __clk_enable(clk_to_gate_ref(clk)); 1453 1454 return TEE_SUCCESS; 1455 } 1456 DECLARE_KEEP_PAGER(clk_op_enable); 1457 1458 static void clk_op_disable(struct clk *clk) 1459 { 1460 if (clk_is_gate(clk)) 1461 __clk_disable(clk_to_gate_ref(clk)); 1462 } 1463 DECLARE_KEEP_PAGER(clk_op_disable); 1464 1465 /* This variable is weak to break its dependency chain when linked as unpaged */ 1466 const struct clk_ops stm32mp1_clk_ops 1467 __weak __relrodata_unpaged("stm32mp1_clk_ops") = { 1468 .enable = clk_op_enable, 1469 .disable = clk_op_disable, 1470 .get_rate = clk_op_compute_rate, 1471 }; 1472 1473 static TEE_Result register_stm32mp1_clocks(void) 1474 { 1475 TEE_Result res = TEE_ERROR_GENERIC; 1476 size_t n = 0; 1477 1478 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk); n++) { 1479 stm32mp1_clk[n].ops = &stm32mp1_clk_ops; 1480 stm32mp1_clk[n].name = clk_op_get_name(stm32mp1_clk + n); 1481 refcount_set(&stm32mp1_clk[n].enabled_count, 0); 1482 1483 res = clk_register(stm32mp1_clk + n); 1484 if (res) 1485 return res; 1486 } 1487 1488 return TEE_SUCCESS; 1489 } 1490 1491 #ifdef CFG_DRIVERS_CLK_DT 1492 static struct clk *stm32mp1_clk_dt_get_clk(struct dt_driver_phandle_args *pargs, 1493 void *data __unused, TEE_Result *res) 1494 { 1495 unsigned long clock_id = pargs->args[0]; 1496 struct clk *clk = NULL; 1497 1498 *res = TEE_ERROR_BAD_PARAMETERS; 1499 1500 if (pargs->args_count != 1) 1501 return NULL; 1502 1503 clk = clock_id_to_clk(clock_id); 1504 if (!clk) 1505 return NULL; 1506 1507 *res = TEE_SUCCESS; 1508 return clk; 1509 } 1510 1511 /* Non-null reference for compat data */ 1512 static const uint8_t non_secure_rcc; 1513 1514 static TEE_Result stm32mp1_clock_provider_probe(const void *fdt, int offs, 1515 const void *compat_data) 1516 { 1517 TEE_Result res = TEE_ERROR_GENERIC; 1518 1519 if (compat_data == &non_secure_rcc) 1520 disable_rcc_tzen(); 1521 else 1522 enable_rcc_tzen(); 1523 1524 res = stm32mp1_clk_fdt_init(fdt, offs); 1525 if (res) { 1526 EMSG("Failed to initialize clocks from DT: %#"PRIx32, res); 1527 panic(); 1528 } 1529 1530 res = register_stm32mp1_clocks(); 1531 if (res) { 1532 EMSG("Failed to register clocks: %#"PRIx32, res); 1533 panic(); 1534 } 1535 1536 res = clk_dt_register_clk_provider(fdt, offs, stm32mp1_clk_dt_get_clk, 1537 NULL); 1538 if (res) { 1539 EMSG("Failed to register clock provider: %#"PRIx32, res); 1540 panic(); 1541 } 1542 1543 enable_static_secure_clocks(); 1544 1545 return TEE_SUCCESS; 1546 } 1547 1548 static const struct dt_device_match stm32mp1_clock_match_table[] = { 1549 { .compatible = "st,stm32mp1-rcc", .compat_data = &non_secure_rcc, }, 1550 { .compatible = "st,stm32mp1-rcc-secure", }, 1551 { } 1552 }; 1553 1554 DEFINE_DT_DRIVER(stm32mp1_clock_dt_driver) = { 1555 .name = "stm32mp1_clock", 1556 .type = DT_DRIVER_CLK, 1557 .match_table = stm32mp1_clock_match_table, 1558 .probe = stm32mp1_clock_provider_probe, 1559 }; 1560 #else /*CFG_DRIVERS_CLK_DT*/ 1561 static TEE_Result stm32mp1_clk_early_init(void) 1562 { 1563 TEE_Result __maybe_unused res = TEE_ERROR_GENERIC; 1564 1565 res = register_stm32mp1_clocks(); 1566 if (res) { 1567 EMSG("Failed to register clocks: %#"PRIx32, res); 1568 panic(); 1569 } 1570 1571 enable_static_secure_clocks(); 1572 1573 return TEE_SUCCESS; 1574 } 1575 1576 service_init(stm32mp1_clk_early_init); 1577 #endif /*CFG_DRIVERS_CLK_DT*/ 1578