1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0+) 2 /* 3 * Copyright (C) 2018-2022, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/stm32mp1_rcc.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <drivers/stm32_shared_io.h> 12 #include <drivers/stm32mp_dt_bindings.h> 13 #include <initcall.h> 14 #include <io.h> 15 #include <keep.h> 16 #include <kernel/dt.h> 17 #include <kernel/dt_driver.h> 18 #include <kernel/boot.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <libfdt.h> 22 #include <platform_config.h> 23 #include <stdio.h> 24 #include <stm32_util.h> 25 #include <trace.h> 26 #include <util.h> 27 28 /* Identifiers for root oscillators */ 29 enum stm32mp_osc_id { 30 OSC_HSI, 31 OSC_HSE, 32 OSC_CSI, 33 OSC_LSI, 34 OSC_LSE, 35 OSC_I2S_CKIN, 36 OSC_USB_PHY_48, 37 NB_OSC, 38 _UNKNOWN_OSC_ID = 0xffU 39 }; 40 41 /* Identifiers for parent clocks */ 42 enum stm32mp1_parent_id { 43 _HSI, 44 _HSE, 45 _CSI, 46 _LSI, 47 _LSE, 48 _I2S_CKIN, 49 _USB_PHY_48, 50 _HSI_KER, 51 _HSE_KER, 52 _HSE_KER_DIV2, 53 _HSE_RTC, 54 _CSI_KER, 55 _PLL1_P, 56 _PLL1_Q, 57 _PLL1_R, 58 _PLL2_P, 59 _PLL2_Q, 60 _PLL2_R, 61 _PLL3_P, 62 _PLL3_Q, 63 _PLL3_R, 64 _PLL4_P, 65 _PLL4_Q, 66 _PLL4_R, 67 _ACLK, 68 _PCLK1, 69 _PCLK2, 70 _PCLK3, 71 _PCLK4, 72 _PCLK5, 73 _HCLK5, 74 _HCLK6, 75 _HCLK2, 76 _CK_PER, 77 _CK_MPU, 78 _CK_MCU, 79 _PARENT_NB, 80 _UNKNOWN_ID = 0xff, 81 }; 82 83 /* 84 * Identifiers for parent clock selectors. 85 * This enum lists only the parent clocks we are interested in. 86 */ 87 enum stm32mp1_parent_sel { 88 _STGEN_SEL, 89 _I2C35_SEL, 90 _I2C46_SEL, 91 _SPI6_SEL, 92 _USART1_SEL, 93 _RNG1_SEL, 94 _UART6_SEL, 95 _UART24_SEL, 96 _UART35_SEL, 97 _UART78_SEL, 98 _AXISS_SEL, 99 _MCUSS_SEL, 100 _USBPHY_SEL, 101 _USBO_SEL, 102 _RTC_SEL, 103 _MPU_SEL, 104 _PARENT_SEL_NB, 105 _UNKNOWN_SEL = 0xff, 106 }; 107 108 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 109 [_HSE] = CK_HSE, 110 [_HSI] = CK_HSI, 111 [_CSI] = CK_CSI, 112 [_LSE] = CK_LSE, 113 [_LSI] = CK_LSI, 114 [_I2S_CKIN] = _UNKNOWN_ID, 115 [_USB_PHY_48] = _UNKNOWN_ID, 116 [_HSI_KER] = CK_HSI, 117 [_HSE_KER] = CK_HSE, 118 [_HSE_KER_DIV2] = CK_HSE_DIV2, 119 [_HSE_RTC] = _UNKNOWN_ID, 120 [_CSI_KER] = CK_CSI, 121 [_PLL1_P] = PLL1_P, 122 [_PLL1_Q] = PLL1_Q, 123 [_PLL1_R] = PLL1_R, 124 [_PLL2_P] = PLL2_P, 125 [_PLL2_Q] = PLL2_Q, 126 [_PLL2_R] = PLL2_R, 127 [_PLL3_P] = PLL3_P, 128 [_PLL3_Q] = PLL3_Q, 129 [_PLL3_R] = PLL3_R, 130 [_PLL4_P] = PLL4_P, 131 [_PLL4_Q] = PLL4_Q, 132 [_PLL4_R] = PLL4_R, 133 [_ACLK] = CK_AXI, 134 [_PCLK1] = CK_AXI, 135 [_PCLK2] = CK_AXI, 136 [_PCLK3] = CK_AXI, 137 [_PCLK4] = CK_AXI, 138 [_PCLK5] = CK_AXI, 139 [_HCLK5] = CK_AXI, 140 [_HCLK6] = CK_AXI, 141 [_HCLK2] = CK_AXI, 142 [_CK_PER] = CK_PER, 143 [_CK_MPU] = CK_MPU, 144 [_CK_MCU] = CK_MCU, 145 }; 146 147 static enum stm32mp1_parent_id osc_id2parent_id(enum stm32mp_osc_id osc_id) 148 { 149 assert(osc_id >= OSC_HSI && osc_id < NB_OSC); 150 COMPILE_TIME_ASSERT((int)OSC_HSI == (int)_HSI && 151 (int)OSC_HSE == (int)_HSE && 152 (int)OSC_CSI == (int)_CSI && 153 (int)OSC_LSI == (int)_LSI && 154 (int)OSC_LSE == (int)_LSE && 155 (int)OSC_I2S_CKIN == (int)_I2S_CKIN && 156 (int)OSC_USB_PHY_48 == (int)_USB_PHY_48); 157 158 return (enum stm32mp1_parent_id)osc_id; 159 } 160 161 static enum stm32mp1_parent_id clock_id2parent_id(unsigned long id) 162 { 163 size_t n = 0; 164 165 COMPILE_TIME_ASSERT(STM32MP1_LAST_CLK < _UNKNOWN_ID); 166 167 for (n = 0; n < ARRAY_SIZE(parent_id_clock_id); n++) 168 if (parent_id_clock_id[n] == id) 169 return (enum stm32mp1_parent_id)n; 170 171 return _UNKNOWN_ID; 172 } 173 174 /* Identifiers for PLLs and their configuration resources */ 175 enum stm32mp1_pll_id { 176 _PLL1, 177 _PLL2, 178 _PLL3, 179 _PLL4, 180 _PLL_NB 181 }; 182 183 enum stm32mp1_div_id { 184 _DIV_P, 185 _DIV_Q, 186 _DIV_R, 187 _DIV_NB, 188 }; 189 190 enum stm32mp1_plltype { 191 PLL_800, 192 PLL_1600, 193 PLL_TYPE_NB 194 }; 195 196 /* 197 * Clock generic gates clocks which state is controlled by a single RCC bit 198 * 199 * @offset: RCC register byte offset from RCC base where clock is controlled 200 * @bit: Bit position in the RCC 32bit register 201 * @clock_id: Identifier used for the clock in the clock driver API 202 * @set_clr: Non-null if and only-if RCC register is a CLEAR/SET register 203 * (CLEAR register is at offset RCC_MP_ENCLRR_OFFSET from SET register) 204 * @secure: One of N_S or SEC, defined below 205 * @sel: _UNKNOWN_ID (fixed parent) or reference to parent clock selector 206 * (8bit storage of ID from enum stm32mp1_parent_sel) 207 * @fixed: _UNKNOWN_ID (selectable paranet) or reference to parent clock 208 * (8bit storage of ID from enum stm32mp1_parent_id) 209 */ 210 struct stm32mp1_clk_gate { 211 uint16_t offset; 212 uint8_t bit; 213 uint8_t clock_id; 214 uint8_t set_clr; 215 uint8_t secure; 216 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 217 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 218 }; 219 220 /* Parent clock selection: select register info, parent clocks references */ 221 struct stm32mp1_clk_sel { 222 uint16_t offset; 223 uint8_t src; 224 uint8_t msk; 225 uint8_t nb_parent; 226 const uint8_t *parent; 227 }; 228 229 #define REFCLK_SIZE 4 230 /* PLL control: type, control register offsets, up-to-4 selectable parent */ 231 struct stm32mp1_clk_pll { 232 enum stm32mp1_plltype plltype; 233 uint16_t rckxselr; 234 uint16_t pllxcfgr1; 235 uint16_t pllxcfgr2; 236 uint16_t pllxfracr; 237 uint16_t pllxcr; 238 uint16_t pllxcsgr; 239 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 240 }; 241 242 #define N_S 0 /* Non-secure can access RCC interface */ 243 #define SEC 1 /* RCC[TZEN] protects RCC interface */ 244 245 /* Clocks with selectable source and not set/clr register access */ 246 #define _CLK_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 247 { \ 248 .offset = (_offset), \ 249 .bit = (_bit), \ 250 .clock_id = (_clock_id), \ 251 .set_clr = 0, \ 252 .secure = (_sec), \ 253 .sel = (_parent_sel), \ 254 .fixed = _UNKNOWN_ID, \ 255 } 256 257 /* Clocks with fixed source and not set/clr register access */ 258 #define _CLK_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 259 { \ 260 .offset = (_offset), \ 261 .bit = (_bit), \ 262 .clock_id = (_clock_id), \ 263 .set_clr = 0, \ 264 .secure = (_sec), \ 265 .sel = _UNKNOWN_SEL, \ 266 .fixed = (_parent), \ 267 } 268 269 /* Clocks with selectable source and set/clr register access */ 270 #define _CLK_SC_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 271 { \ 272 .offset = (_offset), \ 273 .bit = (_bit), \ 274 .clock_id = (_clock_id), \ 275 .set_clr = 1, \ 276 .secure = (_sec), \ 277 .sel = (_parent_sel), \ 278 .fixed = _UNKNOWN_ID, \ 279 } 280 281 /* Clocks with fixed source and set/clr register access */ 282 #define _CLK_SC_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 283 { \ 284 .offset = (_offset), \ 285 .bit = (_bit), \ 286 .clock_id = (_clock_id), \ 287 .set_clr = 1, \ 288 .secure = (_sec), \ 289 .sel = _UNKNOWN_SEL, \ 290 .fixed = (_parent), \ 291 } 292 293 /* 294 * Clocks with selectable source and set/clr register access 295 * and enable bit position defined by a label (argument _bit) 296 */ 297 #define _CLK_SC2_SELEC(_sec, _offset, _bit, _clock_id, _parent_sel) \ 298 { \ 299 .offset = (_offset), \ 300 .clock_id = (_clock_id), \ 301 .bit = _offset ## _ ## _bit ## _POS, \ 302 .set_clr = 1, \ 303 .secure = (_sec), \ 304 .sel = (_parent_sel), \ 305 .fixed = _UNKNOWN_ID, \ 306 } 307 #define _CLK_SC2_FIXED(_sec, _offset, _bit, _clock_id, _parent) \ 308 { \ 309 .offset = (_offset), \ 310 .clock_id = (_clock_id), \ 311 .bit = _offset ## _ ## _bit ## _POS, \ 312 .set_clr = 1, \ 313 .secure = (_sec), \ 314 .sel = _UNKNOWN_SEL, \ 315 .fixed = (_parent), \ 316 } 317 318 #define _CLK_PARENT(idx, _offset, _src, _mask, _parent) \ 319 [(idx)] = { \ 320 .offset = (_offset), \ 321 .src = (_src), \ 322 .msk = (_mask), \ 323 .parent = (_parent), \ 324 .nb_parent = ARRAY_SIZE(_parent) \ 325 } 326 327 #define _CLK_PLL(_idx, _type, _off1, _off2, _off3, _off4, \ 328 _off5, _off6, _p1, _p2, _p3, _p4) \ 329 [(_idx)] = { \ 330 .plltype = (_type), \ 331 .rckxselr = (_off1), \ 332 .pllxcfgr1 = (_off2), \ 333 .pllxcfgr2 = (_off3), \ 334 .pllxfracr = (_off4), \ 335 .pllxcr = (_off5), \ 336 .pllxcsgr = (_off6), \ 337 .refclk[0] = (_p1), \ 338 .refclk[1] = (_p2), \ 339 .refclk[2] = (_p3), \ 340 .refclk[3] = (_p4), \ 341 } 342 343 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 344 345 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 346 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 347 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 348 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 356 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 357 358 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, SPI6EN, SPI6_K, _SPI6_SEL), 359 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C4EN, I2C4_K, _I2C46_SEL), 360 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, I2C6EN, I2C6_K, _I2C46_SEL), 361 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, USART1EN, USART1_K, _USART1_SEL), 362 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, RTCAPBEN, RTCAPB, _PCLK5), 363 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC1EN, TZC1, _PCLK5), 364 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZC2EN, TZC2, _PCLK5), 365 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, TZPCEN, TZPC, _PCLK5), 366 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, IWDG1APBEN, IWDG1, _PCLK5), 367 _CLK_SC2_FIXED(SEC, RCC_MP_APB5ENSETR, BSECEN, BSEC, _PCLK5), 368 _CLK_SC2_SELEC(SEC, RCC_MP_APB5ENSETR, STGENEN, STGEN_K, _STGEN_SEL), 369 370 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, GPIOZEN, GPIOZ, _HCLK5), 371 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, CRYP1EN, CRYP1, _HCLK5), 372 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, HASH1EN, HASH1, _HCLK5), 373 _CLK_SC2_SELEC(SEC, RCC_MP_AHB5ENSETR, RNG1EN, RNG1_K, _RNG1_SEL), 374 _CLK_SC2_FIXED(SEC, RCC_MP_AHB5ENSETR, BKPSRAMEN, BKPSRAM, _HCLK5), 375 376 _CLK_SC2_FIXED(SEC, RCC_MP_TZAHB6ENSETR, MDMA, MDMA, _HCLK6), 377 378 _CLK_SELEC(SEC, RCC_BDCR, RCC_BDCR_RTCCKEN_POS, RTC, _RTC_SEL), 379 380 /* Non-secure clocks */ 381 #ifdef CFG_WITH_NSEC_I2CS 382 _CLK_SC2_SELEC(N_S, RCC_MP_APB1ENSETR, I2C5EN, I2C5_K, _I2C35_SEL), 383 #endif 384 385 #ifdef CFG_WITH_NSEC_GPIOS 386 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_ID), 387 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_ID), 388 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_ID), 389 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_ID), 390 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_ID), 391 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_ID), 392 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_ID), 393 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_ID), 394 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_ID), 395 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_ID), 396 _CLK_SC_FIXED(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_ID), 397 #endif 398 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 399 #ifdef CFG_WITH_NSEC_UARTS 400 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 401 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 402 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 403 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 404 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 405 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 406 #endif 407 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 408 #ifdef CFG_WITH_NSEC_UARTS 409 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 410 #endif 411 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 412 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 413 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 414 415 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 416 }; 417 DECLARE_KEEP_PAGER(stm32mp1_clk_gate); 418 419 const uint8_t stm32mp1_clk_on[] = { 420 CK_HSE, CK_CSI, CK_LSI, CK_LSE, CK_HSI, CK_HSE_DIV2, 421 PLL1_P, PLL1_Q, PLL1_R, PLL2_P, PLL2_Q, PLL2_R, PLL3_P, PLL3_Q, PLL3_R, 422 CK_AXI, CK_MPU, CK_MCU, 423 }; 424 425 /* Parents for secure aware clocks in the xxxSELR value ordering */ 426 static const uint8_t stgen_parents[] = { 427 _HSI_KER, _HSE_KER 428 }; 429 430 #ifdef CFG_WITH_NSEC_I2CS 431 static const uint8_t i2c35_parents[] = { 432 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 433 }; 434 #endif 435 436 static const uint8_t i2c46_parents[] = { 437 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 438 }; 439 440 static const uint8_t spi6_parents[] = { 441 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 442 }; 443 444 static const uint8_t usart1_parents[] = { 445 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 446 }; 447 448 static const uint8_t rng1_parents[] = { 449 _CSI, _PLL4_R, _LSE, _LSI 450 }; 451 452 static const uint8_t mpu_parents[] = { 453 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 454 }; 455 456 /* Parents for (some) non-secure clocks */ 457 #ifdef CFG_WITH_NSEC_UARTS 458 static const uint8_t uart6_parents[] = { 459 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 460 }; 461 462 static const uint8_t uart234578_parents[] = { 463 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 464 }; 465 #endif 466 467 static const uint8_t axiss_parents[] = { 468 _HSI, _HSE, _PLL2_P 469 }; 470 471 static const uint8_t mcuss_parents[] = { 472 _HSI, _HSE, _CSI, _PLL3_P 473 }; 474 475 static const uint8_t rtc_parents[] = { 476 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 477 }; 478 479 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 480 /* Secure aware clocks */ 481 _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 482 _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 483 _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), 484 _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), 485 _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), 486 _CLK_PARENT(_RTC_SEL, RCC_BDCR, 16, 0x3, rtc_parents), 487 _CLK_PARENT(_MPU_SEL, RCC_MPCKSELR, 0, 0x3, mpu_parents), 488 /* Always non-secure clocks (maybe used in some way in secure world) */ 489 #ifdef CFG_WITH_NSEC_I2CS 490 _CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), 491 #endif 492 #ifdef CFG_WITH_NSEC_UARTS 493 _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 494 _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), 495 _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), 496 _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), 497 #endif 498 _CLK_PARENT(_AXISS_SEL, RCC_ASSCKSELR, 0, 0x3, axiss_parents), 499 _CLK_PARENT(_MCUSS_SEL, RCC_MSSCKSELR, 0, 0x3, mcuss_parents), 500 }; 501 502 /* PLLNCFGR2 register divider by output */ 503 static const uint8_t pllncfgr2[_DIV_NB] = { 504 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 505 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 506 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 507 }; 508 509 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 510 _CLK_PLL(_PLL1, PLL_1600, 511 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 512 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 513 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 514 _CLK_PLL(_PLL2, PLL_1600, 515 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 516 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 517 OSC_HSI, OSC_HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 518 _CLK_PLL(_PLL3, PLL_800, 519 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 520 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 521 OSC_HSI, OSC_HSE, OSC_CSI, _UNKNOWN_OSC_ID), 522 _CLK_PLL(_PLL4, PLL_800, 523 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 524 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 525 OSC_HSI, OSC_HSE, OSC_CSI, OSC_I2S_CKIN), 526 }; 527 528 /* Prescaler table lookups for clock computation */ 529 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 530 static const uint8_t stm32mp1_mcu_div[16] = { 531 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 532 }; 533 534 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 535 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 536 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 537 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 538 0, 1, 2, 3, 4, 4, 4, 4 539 }; 540 541 /* div = /1 /2 /3 /4 */ 542 static const uint8_t stm32mp1_axi_div[8] = { 543 1, 2, 3, 4, 4, 4, 4, 4 544 }; 545 546 static const char __maybe_unused *const stm32mp1_clk_parent_name[_PARENT_NB] = { 547 [_HSI] = "HSI", 548 [_HSE] = "HSE", 549 [_CSI] = "CSI", 550 [_LSI] = "LSI", 551 [_LSE] = "LSE", 552 [_I2S_CKIN] = "I2S_CKIN", 553 [_HSI_KER] = "HSI_KER", 554 [_HSE_KER] = "HSE_KER", 555 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 556 [_HSE_RTC] = "HSE_RTC", 557 [_CSI_KER] = "CSI_KER", 558 [_PLL1_P] = "PLL1_P", 559 [_PLL1_Q] = "PLL1_Q", 560 [_PLL1_R] = "PLL1_R", 561 [_PLL2_P] = "PLL2_P", 562 [_PLL2_Q] = "PLL2_Q", 563 [_PLL2_R] = "PLL2_R", 564 [_PLL3_P] = "PLL3_P", 565 [_PLL3_Q] = "PLL3_Q", 566 [_PLL3_R] = "PLL3_R", 567 [_PLL4_P] = "PLL4_P", 568 [_PLL4_Q] = "PLL4_Q", 569 [_PLL4_R] = "PLL4_R", 570 [_ACLK] = "ACLK", 571 [_PCLK1] = "PCLK1", 572 [_PCLK2] = "PCLK2", 573 [_PCLK3] = "PCLK3", 574 [_PCLK4] = "PCLK4", 575 [_PCLK5] = "PCLK5", 576 [_HCLK2] = "HCLK2", 577 [_HCLK5] = "HCLK5", 578 [_HCLK6] = "HCLK6", 579 [_CK_PER] = "CK_PER", 580 [_CK_MPU] = "CK_MPU", 581 [_CK_MCU] = "CK_MCU", 582 [_USB_PHY_48] = "USB_PHY_48", 583 }; 584 585 /* 586 * Oscillator frequency in Hz. This array shall be initialized 587 * according to platform. 588 */ 589 static unsigned long stm32mp1_osc[NB_OSC]; 590 591 static unsigned long osc_frequency(enum stm32mp_osc_id idx) 592 { 593 if (idx >= ARRAY_SIZE(stm32mp1_osc)) { 594 DMSG("clk id %d not found", idx); 595 return 0; 596 } 597 598 return stm32mp1_osc[idx]; 599 } 600 601 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 602 { 603 return &stm32mp1_clk_gate[idx]; 604 } 605 606 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 607 { 608 return &stm32mp1_clk_sel[idx]; 609 } 610 611 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 612 { 613 return &stm32mp1_clk_pll[idx]; 614 } 615 616 static int stm32mp1_clk_get_gated_id(unsigned long id) 617 { 618 unsigned int i = 0; 619 620 for (i = 0; i < NB_GATES; i++) 621 if (gate_ref(i)->clock_id == id) 622 return i; 623 624 DMSG("clk id %lu not found", id); 625 return -1; 626 } 627 628 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 629 { 630 return (enum stm32mp1_parent_sel)gate_ref(i)->sel; 631 } 632 633 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 634 { 635 return (enum stm32mp1_parent_id)gate_ref(i)->fixed; 636 } 637 638 static int stm32mp1_clk_get_parent(unsigned long id) 639 { 640 const struct stm32mp1_clk_sel *sel = NULL; 641 enum stm32mp1_parent_id parent_id = 0; 642 uint32_t p_sel = 0; 643 int i = 0; 644 enum stm32mp1_parent_id p = _UNKNOWN_ID; 645 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 646 vaddr_t rcc_base = stm32_rcc_base(); 647 648 parent_id = clock_id2parent_id(id); 649 if (parent_id != _UNKNOWN_ID) 650 return (int)parent_id; 651 652 i = stm32mp1_clk_get_gated_id(id); 653 if (i < 0) 654 panic(); 655 656 p = stm32mp1_clk_get_fixed_parent(i); 657 if (p < _PARENT_NB) 658 return (int)p; 659 660 s = stm32mp1_clk_get_sel(i); 661 if (s == _UNKNOWN_SEL) 662 return -1; 663 if (s >= _PARENT_SEL_NB) 664 panic(); 665 666 sel = clk_sel_ref(s); 667 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & sel->msk; 668 if (p_sel < sel->nb_parent) 669 return (int)sel->parent[p_sel]; 670 671 DMSG("No parent selected for clk %lu", id); 672 return -1; 673 } 674 675 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 676 { 677 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr); 678 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 679 680 return osc_frequency(pll->refclk[src]); 681 } 682 683 /* 684 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 685 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 686 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 687 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 688 */ 689 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 690 { 691 unsigned long refclk = 0; 692 unsigned long fvco = 0; 693 uint32_t cfgr1 = 0; 694 uint32_t fracr = 0; 695 uint32_t divm = 0; 696 uint32_t divn = 0; 697 698 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); 699 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); 700 701 divm = (cfgr1 & RCC_PLLNCFGR1_DIVM_MASK) >> RCC_PLLNCFGR1_DIVM_SHIFT; 702 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 703 704 refclk = stm32mp1_pll_get_fref(pll); 705 706 /* 707 * With FRACV : 708 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 709 * Without FRACV 710 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 711 */ 712 if (fracr & RCC_PLLNFRACR_FRACLE) { 713 unsigned long long numerator = 0; 714 unsigned long long denominator = 0; 715 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 716 RCC_PLLNFRACR_FRACV_SHIFT; 717 718 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 719 numerator = refclk * numerator; 720 denominator = ((unsigned long long)divm + 1U) << 13; 721 fvco = (unsigned long)(numerator / denominator); 722 } else { 723 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 724 } 725 726 return fvco; 727 } 728 729 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 730 enum stm32mp1_div_id div_id) 731 { 732 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 733 unsigned long dfout = 0; 734 uint32_t cfgr2 = 0; 735 uint32_t divy = 0; 736 737 if (div_id >= _DIV_NB) 738 return 0; 739 740 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); 741 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 742 743 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 744 745 return dfout; 746 } 747 748 static unsigned long get_clock_rate(enum stm32mp1_parent_id p) 749 { 750 uint32_t reg = 0; 751 unsigned long clock = 0; 752 vaddr_t rcc_base = stm32_rcc_base(); 753 754 switch (p) { 755 case _CK_MPU: 756 /* MPU sub system */ 757 reg = io_read32(rcc_base + RCC_MPCKSELR); 758 switch (reg & RCC_SELR_SRC_MASK) { 759 case RCC_MPCKSELR_HSI: 760 clock = osc_frequency(OSC_HSI); 761 break; 762 case RCC_MPCKSELR_HSE: 763 clock = osc_frequency(OSC_HSE); 764 break; 765 case RCC_MPCKSELR_PLL: 766 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 767 break; 768 case RCC_MPCKSELR_PLL_MPUDIV: 769 reg = io_read32(rcc_base + RCC_MPCKDIVR); 770 if (reg & RCC_MPUDIV_MASK) 771 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P) >> 772 stm32mp1_mpu_div[reg & RCC_MPUDIV_MASK]; 773 else 774 clock = 0; 775 break; 776 default: 777 break; 778 } 779 break; 780 /* AXI sub system */ 781 case _ACLK: 782 case _HCLK2: 783 case _HCLK5: 784 case _HCLK6: 785 case _PCLK4: 786 case _PCLK5: 787 reg = io_read32(rcc_base + RCC_ASSCKSELR); 788 switch (reg & RCC_SELR_SRC_MASK) { 789 case RCC_ASSCKSELR_HSI: 790 clock = osc_frequency(OSC_HSI); 791 break; 792 case RCC_ASSCKSELR_HSE: 793 clock = osc_frequency(OSC_HSE); 794 break; 795 case RCC_ASSCKSELR_PLL: 796 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 797 break; 798 default: 799 break; 800 } 801 802 /* System clock divider */ 803 reg = io_read32(rcc_base + RCC_AXIDIVR); 804 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 805 806 switch (p) { 807 case _PCLK4: 808 reg = io_read32(rcc_base + RCC_APB4DIVR); 809 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 810 break; 811 case _PCLK5: 812 reg = io_read32(rcc_base + RCC_APB5DIVR); 813 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 814 break; 815 default: 816 break; 817 } 818 break; 819 /* MCU sub system */ 820 case _CK_MCU: 821 case _PCLK1: 822 case _PCLK2: 823 case _PCLK3: 824 reg = io_read32(rcc_base + RCC_MSSCKSELR); 825 switch (reg & RCC_SELR_SRC_MASK) { 826 case RCC_MSSCKSELR_HSI: 827 clock = osc_frequency(OSC_HSI); 828 break; 829 case RCC_MSSCKSELR_HSE: 830 clock = osc_frequency(OSC_HSE); 831 break; 832 case RCC_MSSCKSELR_CSI: 833 clock = osc_frequency(OSC_CSI); 834 break; 835 case RCC_MSSCKSELR_PLL: 836 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 837 break; 838 default: 839 break; 840 } 841 842 /* MCU clock divider */ 843 reg = io_read32(rcc_base + RCC_MCUDIVR); 844 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 845 846 switch (p) { 847 case _PCLK1: 848 reg = io_read32(rcc_base + RCC_APB1DIVR); 849 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 850 break; 851 case _PCLK2: 852 reg = io_read32(rcc_base + RCC_APB2DIVR); 853 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 854 break; 855 case _PCLK3: 856 reg = io_read32(rcc_base + RCC_APB3DIVR); 857 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 858 break; 859 case _CK_MCU: 860 default: 861 break; 862 } 863 break; 864 case _CK_PER: 865 reg = io_read32(rcc_base + RCC_CPERCKSELR); 866 switch (reg & RCC_SELR_SRC_MASK) { 867 case RCC_CPERCKSELR_HSI: 868 clock = osc_frequency(OSC_HSI); 869 break; 870 case RCC_CPERCKSELR_HSE: 871 clock = osc_frequency(OSC_HSE); 872 break; 873 case RCC_CPERCKSELR_CSI: 874 clock = osc_frequency(OSC_CSI); 875 break; 876 default: 877 break; 878 } 879 break; 880 case _HSI: 881 case _HSI_KER: 882 clock = osc_frequency(OSC_HSI); 883 break; 884 case _CSI: 885 case _CSI_KER: 886 clock = osc_frequency(OSC_CSI); 887 break; 888 case _HSE: 889 case _HSE_KER: 890 clock = osc_frequency(OSC_HSE); 891 break; 892 case _HSE_KER_DIV2: 893 clock = osc_frequency(OSC_HSE) >> 1; 894 break; 895 case _HSE_RTC: 896 clock = osc_frequency(OSC_HSE); 897 clock /= (io_read32(rcc_base + RCC_RTCDIVR) & 898 RCC_DIVR_DIV_MASK) + 1; 899 break; 900 case _LSI: 901 clock = osc_frequency(OSC_LSI); 902 break; 903 case _LSE: 904 clock = osc_frequency(OSC_LSE); 905 break; 906 /* PLL */ 907 case _PLL1_P: 908 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 909 break; 910 case _PLL1_Q: 911 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 912 break; 913 case _PLL1_R: 914 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 915 break; 916 case _PLL2_P: 917 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 918 break; 919 case _PLL2_Q: 920 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 921 break; 922 case _PLL2_R: 923 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 924 break; 925 case _PLL3_P: 926 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 927 break; 928 case _PLL3_Q: 929 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 930 break; 931 case _PLL3_R: 932 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 933 break; 934 case _PLL4_P: 935 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 936 break; 937 case _PLL4_Q: 938 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 939 break; 940 case _PLL4_R: 941 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 942 break; 943 /* Other */ 944 case _USB_PHY_48: 945 clock = osc_frequency(OSC_USB_PHY_48); 946 break; 947 default: 948 break; 949 } 950 951 return clock; 952 } 953 954 static void __clk_enable(const struct stm32mp1_clk_gate *gate) 955 { 956 vaddr_t base = stm32_rcc_base(); 957 uint32_t bit = BIT(gate->bit); 958 959 if (gate->set_clr) 960 io_write32(base + gate->offset, bit); 961 else 962 io_setbits32_stm32shregs(base + gate->offset, bit); 963 964 FMSG("Clock %u has been enabled", gate->clock_id); 965 } 966 967 static void __clk_disable(const struct stm32mp1_clk_gate *gate) 968 { 969 vaddr_t base = stm32_rcc_base(); 970 uint32_t bit = BIT(gate->bit); 971 972 if (gate->set_clr) 973 io_write32(base + gate->offset + RCC_MP_ENCLRR_OFFSET, bit); 974 else 975 io_clrbits32_stm32shregs(base + gate->offset, bit); 976 977 FMSG("Clock %u has been disabled", gate->clock_id); 978 } 979 980 static long get_timer_rate(long parent_rate, unsigned int apb_bus) 981 { 982 uint32_t timgxpre = 0; 983 uint32_t apbxdiv = 0; 984 vaddr_t rcc_base = stm32_rcc_base(); 985 986 switch (apb_bus) { 987 case 1: 988 apbxdiv = io_read32(rcc_base + RCC_APB1DIVR) & 989 RCC_APBXDIV_MASK; 990 timgxpre = io_read32(rcc_base + RCC_TIMG1PRER) & 991 RCC_TIMGXPRER_TIMGXPRE; 992 break; 993 case 2: 994 apbxdiv = io_read32(rcc_base + RCC_APB2DIVR) & 995 RCC_APBXDIV_MASK; 996 timgxpre = io_read32(rcc_base + RCC_TIMG2PRER) & 997 RCC_TIMGXPRER_TIMGXPRE; 998 break; 999 default: 1000 panic(); 1001 break; 1002 } 1003 1004 if (apbxdiv == 0) 1005 return parent_rate; 1006 1007 return parent_rate * (timgxpre + 1) * 2; 1008 } 1009 1010 static unsigned long _stm32_clock_get_rate(unsigned long id) 1011 { 1012 enum stm32mp1_parent_id p = _UNKNOWN_ID; 1013 unsigned long rate = 0; 1014 1015 p = stm32mp1_clk_get_parent(id); 1016 if (p < 0) 1017 return 0; 1018 1019 rate = get_clock_rate(p); 1020 1021 if ((id >= TIM2_K) && (id <= TIM14_K)) 1022 rate = get_timer_rate(rate, 1); 1023 1024 if ((id >= TIM1_K) && (id <= TIM17_K)) 1025 rate = get_timer_rate(rate, 2); 1026 1027 return rate; 1028 } 1029 1030 /* 1031 * Get the parent ID of the target parent clock, or -1 if no parent found. 1032 */ 1033 static enum stm32mp1_parent_id get_parent_id_parent(enum stm32mp1_parent_id id) 1034 { 1035 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 1036 enum stm32mp1_pll_id pll_id = _PLL_NB; 1037 uint32_t p_sel = 0; 1038 1039 switch (id) { 1040 case _ACLK: 1041 case _HCLK5: 1042 case _HCLK6: 1043 case _PCLK4: 1044 case _PCLK5: 1045 s = _AXISS_SEL; 1046 break; 1047 case _PLL1_P: 1048 case _PLL1_Q: 1049 case _PLL1_R: 1050 pll_id = _PLL1; 1051 break; 1052 case _PLL2_P: 1053 case _PLL2_Q: 1054 case _PLL2_R: 1055 pll_id = _PLL2; 1056 break; 1057 case _PLL3_P: 1058 case _PLL3_Q: 1059 case _PLL3_R: 1060 pll_id = _PLL3; 1061 break; 1062 case _PLL4_P: 1063 case _PLL4_Q: 1064 case _PLL4_R: 1065 pll_id = _PLL4; 1066 break; 1067 case _PCLK1: 1068 case _PCLK2: 1069 case _HCLK2: 1070 case _CK_PER: 1071 case _CK_MPU: 1072 case _CK_MCU: 1073 case _USB_PHY_48: 1074 /* We do not expected to access these */ 1075 panic(); 1076 break; 1077 default: 1078 /* Other parents have no parent */ 1079 return -1; 1080 } 1081 1082 if (s != _UNKNOWN_SEL) { 1083 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 1084 vaddr_t rcc_base = stm32_rcc_base(); 1085 1086 p_sel = (io_read32(rcc_base + sel->offset) >> sel->src) & 1087 sel->msk; 1088 1089 if (p_sel < sel->nb_parent) 1090 return sel->parent[p_sel]; 1091 } else { 1092 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1093 1094 p_sel = io_read32(stm32_rcc_base() + pll->rckxselr) & 1095 RCC_SELR_REFCLK_SRC_MASK; 1096 1097 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) 1098 return osc_id2parent_id(pll->refclk[p_sel]); 1099 } 1100 1101 FMSG("No parent found for %s", stm32mp1_clk_parent_name[id]); 1102 return -1; 1103 } 1104 1105 /* We are only interested in knowing if PLL3 shall be secure or not */ 1106 static void secure_parent_clocks(enum stm32mp1_parent_id parent_id) 1107 { 1108 enum stm32mp1_parent_id grandparent_id = _UNKNOWN_ID; 1109 1110 switch (parent_id) { 1111 case _ACLK: 1112 case _HCLK2: 1113 case _HCLK5: 1114 case _HCLK6: 1115 case _PCLK4: 1116 case _PCLK5: 1117 /* Intermediate clock mux or clock, go deeper in clock tree */ 1118 break; 1119 case _HSI: 1120 case _HSI_KER: 1121 case _LSI: 1122 case _CSI: 1123 case _CSI_KER: 1124 case _HSE: 1125 case _HSE_KER: 1126 case _HSE_KER_DIV2: 1127 case _HSE_RTC: 1128 case _LSE: 1129 case _PLL1_P: 1130 case _PLL1_Q: 1131 case _PLL1_R: 1132 case _PLL2_P: 1133 case _PLL2_Q: 1134 case _PLL2_R: 1135 /* Always secure clocks, no need to go further */ 1136 return; 1137 case _PLL3_P: 1138 case _PLL3_Q: 1139 case _PLL3_R: 1140 /* PLL3 is a shared resource, registered and don't go further */ 1141 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 1142 return; 1143 default: 1144 DMSG("Cannot lookup parent clock %s", 1145 stm32mp1_clk_parent_name[parent_id]); 1146 panic(); 1147 } 1148 1149 grandparent_id = get_parent_id_parent(parent_id); 1150 if (grandparent_id >= 0) 1151 secure_parent_clocks(grandparent_id); 1152 } 1153 1154 void stm32mp_register_clock_parents_secure(unsigned long clock_id) 1155 { 1156 enum stm32mp1_parent_id parent_id = stm32mp1_clk_get_parent(clock_id); 1157 1158 if (parent_id < 0) { 1159 DMSG("No parent for clock %lu", clock_id); 1160 return; 1161 } 1162 1163 secure_parent_clocks(parent_id); 1164 } 1165 1166 static const char *stm32mp_osc_node_label[NB_OSC] = { 1167 [OSC_LSI] = "clk-lsi", 1168 [OSC_LSE] = "clk-lse", 1169 [OSC_HSI] = "clk-hsi", 1170 [OSC_HSE] = "clk-hse", 1171 [OSC_CSI] = "clk-csi", 1172 [OSC_I2S_CKIN] = "i2s_ckin", 1173 [OSC_USB_PHY_48] = "ck_usbo_48m" 1174 }; 1175 1176 static unsigned int clk_freq_prop(const void *fdt, int node) 1177 { 1178 const fdt32_t *cuint = NULL; 1179 int ret = 0; 1180 1181 /* Disabled clocks report null rate */ 1182 if (fdt_get_status(fdt, node) == DT_STATUS_DISABLED) 1183 return 0; 1184 1185 cuint = fdt_getprop(fdt, node, "clock-frequency", &ret); 1186 if (!cuint) 1187 panic(); 1188 1189 return fdt32_to_cpu(*cuint); 1190 } 1191 1192 static void get_osc_freq_from_dt(const void *fdt) 1193 { 1194 enum stm32mp_osc_id idx = _UNKNOWN_OSC_ID; 1195 int clk_node = fdt_path_offset(fdt, "/clocks"); 1196 1197 if (clk_node < 0) 1198 panic(); 1199 1200 COMPILE_TIME_ASSERT((int)OSC_HSI == 0); 1201 for (idx = OSC_HSI; idx < NB_OSC; idx++) { 1202 const char *name = stm32mp_osc_node_label[idx]; 1203 int subnode = 0; 1204 1205 fdt_for_each_subnode(subnode, fdt, clk_node) { 1206 const char *cchar = NULL; 1207 int ret = 0; 1208 1209 cchar = fdt_get_name(fdt, subnode, &ret); 1210 if (!cchar) 1211 panic(); 1212 1213 if (strncmp(cchar, name, (size_t)ret) == 0) { 1214 stm32mp1_osc[idx] = clk_freq_prop(fdt, subnode); 1215 1216 DMSG("Osc %s: %lu Hz", name, stm32mp1_osc[idx]); 1217 break; 1218 } 1219 } 1220 1221 if (!stm32mp1_osc[idx]) 1222 DMSG("Osc %s: no frequency info", name); 1223 } 1224 } 1225 1226 static void enable_static_secure_clocks(void) 1227 { 1228 unsigned int idx = 0; 1229 const unsigned long secure_enable[] = { 1230 DDRC1, DDRC1LP, DDRC2, DDRC2LP, DDRPHYC, DDRPHYCLP, DDRCAPB, 1231 AXIDCG, DDRPHYCAPB, DDRPHYCAPBLP, TZPC, TZC1, TZC2, STGEN_K, 1232 BSEC, 1233 }; 1234 1235 for (idx = 0; idx < ARRAY_SIZE(secure_enable); idx++) { 1236 clk_enable(stm32mp_rcc_clock_id_to_clk(secure_enable[idx])); 1237 stm32mp_register_clock_parents_secure(secure_enable[idx]); 1238 } 1239 1240 if (CFG_TEE_CORE_NB_CORE > 1) 1241 clk_enable(stm32mp_rcc_clock_id_to_clk(RTCAPB)); 1242 } 1243 1244 static void __maybe_unused enable_rcc_tzen(void) 1245 { 1246 io_setbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1247 } 1248 1249 static void __maybe_unused disable_rcc_tzen(void) 1250 { 1251 IMSG("RCC is non-secure"); 1252 io_clrbits32(stm32_rcc_base() + RCC_TZCR, RCC_TZCR_TZEN); 1253 } 1254 1255 static TEE_Result stm32mp1_clk_fdt_init(const void *fdt, int node) 1256 { 1257 unsigned int i = 0; 1258 int len = 0; 1259 int ignored = 0; 1260 1261 get_osc_freq_from_dt(fdt); 1262 1263 /* 1264 * OP-TEE core is not in charge of configuring clock parenthood. 1265 * This is expected from an earlier boot stage. Modifying the clock 1266 * tree parenthood here may jeopardize already configured clocks. 1267 * The sequence below ignores such DT directives with a friendly 1268 * debug trace. 1269 */ 1270 if (fdt_getprop(fdt, node, "st,clksrc", &len)) { 1271 DMSG("Ignore source clocks configuration from DT"); 1272 ignored++; 1273 } 1274 if (fdt_getprop(fdt, node, "st,clkdiv", &len)) { 1275 DMSG("Ignore clock divisors configuration from DT"); 1276 ignored++; 1277 } 1278 if (fdt_getprop(fdt, node, "st,pkcs", &len)) { 1279 DMSG("Ignore peripheral clocks tree configuration from DT"); 1280 ignored++; 1281 } 1282 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1283 char name[] = "st,pll@X"; 1284 1285 snprintf(name, sizeof(name), "st,pll@%d", i); 1286 node = fdt_subnode_offset(fdt, node, name); 1287 if (node < 0) 1288 continue; 1289 1290 if (fdt_getprop(fdt, node, "cfg", &len) || 1291 fdt_getprop(fdt, node, "frac", &len)) { 1292 DMSG("Ignore PLL%u configurations from DT", i); 1293 ignored++; 1294 } 1295 } 1296 1297 if (ignored != 0) 1298 IMSG("DT clock tree configurations were ignored"); 1299 1300 return TEE_SUCCESS; 1301 } 1302 1303 /* 1304 * Conversion between clk references and clock gates and clock on internals 1305 * 1306 * stm32mp1_clk first cells follow stm32mp1_clk_gate[] ordering. 1307 * stm32mp1_clk last cells follow stm32mp1_clk_on[] ordering. 1308 */ 1309 static struct clk stm32mp1_clk[ARRAY_SIZE(stm32mp1_clk_gate) + 1310 ARRAY_SIZE(stm32mp1_clk_on)]; 1311 1312 #define CLK_ON_INDEX_OFFSET ((int)ARRAY_SIZE(stm32mp1_clk_gate)) 1313 1314 static bool clk_is_gate(struct clk *clk) 1315 { 1316 int clk_index = clk - stm32mp1_clk; 1317 1318 assert(clk_index >= 0 && clk_index < (int)ARRAY_SIZE(stm32mp1_clk)); 1319 return clk_index < CLK_ON_INDEX_OFFSET; 1320 } 1321 1322 static unsigned long clk_to_clock_id(struct clk *clk) 1323 { 1324 int gate_index = clk - stm32mp1_clk; 1325 int on_index = gate_index - CLK_ON_INDEX_OFFSET; 1326 1327 if (clk_is_gate(clk)) 1328 return stm32mp1_clk_gate[gate_index].clock_id; 1329 1330 return stm32mp1_clk_on[on_index]; 1331 } 1332 1333 static const struct stm32mp1_clk_gate *clk_to_gate_ref(struct clk *clk) 1334 { 1335 int gate_index = clk - stm32mp1_clk; 1336 1337 assert(clk_is_gate(clk)); 1338 1339 return stm32mp1_clk_gate + gate_index; 1340 } 1341 1342 static int clock_id_to_gate_index(unsigned long clock_id) 1343 { 1344 size_t n = 0; 1345 1346 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_gate); n++) 1347 if (stm32mp1_clk_gate[n].clock_id == clock_id) 1348 return n; 1349 1350 return -1; 1351 } 1352 1353 static int clock_id_to_always_on_index(unsigned long clock_id) 1354 { 1355 size_t n = 0; 1356 1357 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk_on); n++) 1358 if (stm32mp1_clk_on[n] == clock_id) 1359 return n; 1360 1361 return -1; 1362 } 1363 1364 static struct clk *clock_id_to_clk(unsigned long clock_id) 1365 { 1366 int gate_index = clock_id_to_gate_index(clock_id); 1367 int on_index = clock_id_to_always_on_index(clock_id); 1368 1369 if (gate_index >= 0) 1370 return stm32mp1_clk + gate_index; 1371 1372 if (on_index >= 0) 1373 return stm32mp1_clk + CLK_ON_INDEX_OFFSET + on_index; 1374 1375 return NULL; 1376 } 1377 1378 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id) 1379 { 1380 return clock_id_to_clk(clock_id); 1381 } 1382 1383 #if (CFG_TEE_CORE_LOG_LEVEL >= TRACE_DEBUG) && defined(CFG_TEE_CORE_DEBUG) 1384 struct clk_name { 1385 unsigned int clock_id; 1386 const char *name; 1387 }; 1388 1389 #define CLOCK_NAME(_binding, _name) \ 1390 { .clock_id = (_binding), .name = (_name) } 1391 1392 /* Store names only for some clocks */ 1393 const struct clk_name exposed_clk_name[] = { 1394 /* Clocks used by platform drivers not yet probed from DT */ 1395 CLOCK_NAME(CK_DBG, "dbg"), 1396 CLOCK_NAME(CK_MCU, "mcu"), 1397 CLOCK_NAME(RTCAPB, "rtcapb"), 1398 CLOCK_NAME(BKPSRAM, "bkpsram"), 1399 CLOCK_NAME(RTC, "rtc"), 1400 CLOCK_NAME(CRYP1, "crpy1"), 1401 CLOCK_NAME(SYSCFG, "syscfg"), 1402 CLOCK_NAME(GPIOA, "gpioa"), 1403 CLOCK_NAME(GPIOB, "gpiob"), 1404 CLOCK_NAME(GPIOC, "gpioc"), 1405 CLOCK_NAME(GPIOD, "gpiod"), 1406 CLOCK_NAME(GPIOE, "gpioe"), 1407 CLOCK_NAME(GPIOF, "gpiof"), 1408 CLOCK_NAME(GPIOG, "gpiog"), 1409 CLOCK_NAME(GPIOH, "gpioh"), 1410 CLOCK_NAME(GPIOI, "gpioi"), 1411 CLOCK_NAME(GPIOJ, "gpioj"), 1412 CLOCK_NAME(GPIOK, "gpiok"), 1413 CLOCK_NAME(GPIOZ, "gpioz"), 1414 /* Clock exposed by SCMI. SCMI clock fmro DT bindings to come... */ 1415 CLOCK_NAME(CK_HSE, "hse"), 1416 CLOCK_NAME(CK_HSI, "hsi"), 1417 CLOCK_NAME(CK_CSI, "csi"), 1418 CLOCK_NAME(CK_LSE, "lse"), 1419 CLOCK_NAME(CK_LSI, "lsi"), 1420 CLOCK_NAME(PLL2_Q, "pll2q"), 1421 CLOCK_NAME(PLL2_R, "pll2r"), 1422 CLOCK_NAME(PLL3_Q, "pll3q"), 1423 CLOCK_NAME(PLL3_R, "pll3r"), 1424 CLOCK_NAME(CRYP1, "cryp1"), 1425 CLOCK_NAME(HASH1, "hash1"), 1426 CLOCK_NAME(I2C4_K, "i2c4"), 1427 CLOCK_NAME(I2C6_K, "i2c6"), 1428 CLOCK_NAME(IWDG1, "iwdg"), 1429 CLOCK_NAME(RNG1_K, "rng1"), 1430 CLOCK_NAME(SPI6_K, "spi6"), 1431 CLOCK_NAME(USART1_K, "usart1"), 1432 CLOCK_NAME(CK_MCU, "mcu"), 1433 }; 1434 DECLARE_KEEP_PAGER(exposed_clk_name); 1435 1436 static const char *clk_op_get_name(struct clk *clk) 1437 { 1438 unsigned long clock_id = clk_to_clock_id(clk); 1439 size_t n = 0; 1440 1441 for (n = 0; n < ARRAY_SIZE(exposed_clk_name); n++) 1442 if (exposed_clk_name[n].clock_id == clock_id) 1443 return exposed_clk_name[n].name; 1444 1445 return NULL; 1446 } 1447 #else 1448 static const char *clk_op_get_name(struct clk *clk __unused) 1449 { 1450 return NULL; 1451 } 1452 #endif /*CFG_TEE_CORE_LOG_LEVEL*/ 1453 1454 static unsigned long clk_op_compute_rate(struct clk *clk, 1455 unsigned long parent_rate __unused) 1456 { 1457 return _stm32_clock_get_rate(clk_to_clock_id(clk)); 1458 } 1459 1460 static TEE_Result clk_op_enable(struct clk *clk) 1461 { 1462 if (clk_is_gate(clk)) 1463 __clk_enable(clk_to_gate_ref(clk)); 1464 1465 return TEE_SUCCESS; 1466 } 1467 DECLARE_KEEP_PAGER(clk_op_enable); 1468 1469 static void clk_op_disable(struct clk *clk) 1470 { 1471 if (clk_is_gate(clk)) 1472 __clk_disable(clk_to_gate_ref(clk)); 1473 } 1474 DECLARE_KEEP_PAGER(clk_op_disable); 1475 1476 /* This variable is weak to break its dependency chain when linked as unpaged */ 1477 const struct clk_ops stm32mp1_clk_ops 1478 __weak __relrodata_unpaged("stm32mp1_clk_ops") = { 1479 .enable = clk_op_enable, 1480 .disable = clk_op_disable, 1481 .get_rate = clk_op_compute_rate, 1482 }; 1483 1484 static TEE_Result register_stm32mp1_clocks(void) 1485 { 1486 TEE_Result res = TEE_ERROR_GENERIC; 1487 size_t n = 0; 1488 1489 for (n = 0; n < ARRAY_SIZE(stm32mp1_clk); n++) { 1490 stm32mp1_clk[n].ops = &stm32mp1_clk_ops; 1491 stm32mp1_clk[n].name = clk_op_get_name(stm32mp1_clk + n); 1492 refcount_set(&stm32mp1_clk[n].enabled_count, 0); 1493 1494 res = clk_register(stm32mp1_clk + n); 1495 if (res) 1496 return res; 1497 } 1498 1499 return TEE_SUCCESS; 1500 } 1501 1502 static TEE_Result stm32mp1_clk_dt_get_clk(struct dt_pargs *pargs, 1503 void *data __unused, 1504 struct clk **out_clk) 1505 { 1506 unsigned long clock_id = pargs->args[0]; 1507 struct clk *clk = NULL; 1508 1509 if (pargs->args_count != 1) 1510 return TEE_ERROR_BAD_PARAMETERS; 1511 1512 clk = clock_id_to_clk(clock_id); 1513 if (!clk) 1514 return TEE_ERROR_BAD_PARAMETERS; 1515 1516 *out_clk = clk; 1517 1518 return TEE_SUCCESS; 1519 } 1520 1521 /* Non-null reference for compat data */ 1522 static const uint8_t non_secure_rcc; 1523 1524 static TEE_Result stm32mp1_clock_provider_probe(const void *fdt, int offs, 1525 const void *compat_data) 1526 { 1527 TEE_Result res = TEE_ERROR_GENERIC; 1528 1529 if (compat_data == &non_secure_rcc) 1530 disable_rcc_tzen(); 1531 else 1532 enable_rcc_tzen(); 1533 1534 res = stm32mp1_clk_fdt_init(fdt, offs); 1535 if (res) { 1536 EMSG("Failed to initialize clocks from DT: %#"PRIx32, res); 1537 panic(); 1538 } 1539 1540 res = register_stm32mp1_clocks(); 1541 if (res) { 1542 EMSG("Failed to register clocks: %#"PRIx32, res); 1543 panic(); 1544 } 1545 1546 res = clk_dt_register_clk_provider(fdt, offs, stm32mp1_clk_dt_get_clk, 1547 NULL); 1548 if (res) { 1549 EMSG("Failed to register clock provider: %#"PRIx32, res); 1550 panic(); 1551 } 1552 1553 enable_static_secure_clocks(); 1554 1555 return TEE_SUCCESS; 1556 } 1557 1558 static const struct dt_device_match stm32mp1_clock_match_table[] = { 1559 { .compatible = "st,stm32mp1-rcc", .compat_data = &non_secure_rcc, }, 1560 { .compatible = "st,stm32mp1-rcc-secure", }, 1561 { } 1562 }; 1563 1564 DEFINE_DT_DRIVER(stm32mp1_clock_dt_driver) = { 1565 .name = "stm32mp1_clock", 1566 .type = DT_DRIVER_CLK, 1567 .match_table = stm32mp1_clock_match_table, 1568 .probe = stm32mp1_clock_provider_probe, 1569 }; 1570