1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2019 Broadcom. 4 */ 5 6 #include <assert.h> 7 #include <drivers/bcm_sotp.h> 8 #include <initcall.h> 9 #include <io.h> 10 #include <kernel/delay.h> 11 #include <mm/core_memprot.h> 12 #include <platform_config.h> 13 #include <util.h> 14 15 #define SOTP_PROG_CONTROL 0x00 16 #define SOTP_WRDATA_0 0x04 17 #define SOTP_WRDATA_1 0x08 18 #define SOTP_ADDR 0x0c 19 #define SOTP_CTRL_0 0x10 20 #define SOTP_STAT_0 0x18 21 #define SOTP_STATUS_1 0x1c 22 #define SOTP_RDDATA_0 0x20 23 #define SOTP_RDDATA_1 0x24 24 #define SOTP_REGS_SOTP_CHIP_STATES 0x28 25 #define SOTP_REGS_OTP_WR_LOCK 0x38 26 #define SOTP_CHIP_CTRL 0x4c 27 28 #define SOTP_PROG_CONTROL__OTP_CPU_MODE_EN BIT(15) 29 #define SOTP_PROG_CONTROL__OTP_DISABLE_ECC BIT(9) 30 #define SOTP_ADDR__OTP_ROW_ADDR_R 6 31 #define SOTP_PROG_CONTROL__OTP_ECC_WREN BIT(8) 32 #define SOTP_CTRL_0__START 1 33 #define SOTP_STATUS_0__FDONE BIT(3) 34 #define SOTP_STATUS_1__CMD_DONE BIT(1) 35 #define SOTP_STATUS_1__ECC_DET BIT(17) 36 37 #define SOTP_READ 0 38 #define SOTP_ADDR_MASK 0x3ff 39 #define SOTP_TIMEOUT_US 300 40 41 #define SOTP_PROG_WORD 10 42 #define SOTP_STATUS__PROGOK BIT(2) 43 #define SOTP_PROG_ENABLE 2 44 45 #define SOTP_ROW_DATA_MASK UINT32_MAX 46 #define SOTP_ECC_ERR_BITS_MASK GENMASK_64(40, 32) 47 48 #define SOTP_CHIP_CTRL_SW_OVERRIDE_CHIP_STATES 4 49 #define SOTP_CHIP_CTRL_SW_MANU_PROG 5 50 #define SOTP_CHIP_CTRL_SW_CID_PROG 6 51 #define SOTP_CHIP_CTRL_SW_AB_DEVICE 8 52 #define SOTP_CHIP_CTRL_SW_AB_DEV_MODE 9 53 #define CHIP_STATE_UNPROGRAMMED 0x1 54 #define CHIP_STATE_UNASSIGNED 0x2 55 #define CHIP_STATE_DEFAULT (CHIP_STATE_UNASSIGNED | \ 56 CHIP_STATE_UNPROGRAMMED) 57 58 static vaddr_t bcm_sotp_base; 59 60 static TEE_Result otp_status_done_wait(vaddr_t addr, uint32_t bit) 61 { 62 uint64_t timeout = timeout_init_us(SOTP_TIMEOUT_US); 63 64 while (!(io_read32(addr) & bit)) 65 if (timeout_elapsed(timeout)) 66 return TEE_ERROR_BUSY; 67 return TEE_SUCCESS; 68 } 69 70 TEE_Result bcm_iproc_sotp_mem_read(uint32_t row_addr, bool sotp_add_ecc, 71 uint64_t *rdata) 72 { 73 uint64_t read_data = 0; 74 uint32_t reg_val = 0; 75 TEE_Result ret = TEE_SUCCESS; 76 77 assert(bcm_sotp_base); 78 /* Check for FDONE status */ 79 ret = otp_status_done_wait((bcm_sotp_base + SOTP_STAT_0), 80 SOTP_STATUS_0__FDONE); 81 if (ret) { 82 EMSG("FDONE status done wait failed and returned %#"PRIx32, 83 ret); 84 return ret; 85 } 86 87 /* Enable OTP access by CPU */ 88 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), 89 SOTP_PROG_CONTROL__OTP_CPU_MODE_EN); 90 91 /* ROWS does not support ECC */ 92 if (row_addr <= SOTP_NO_ECC_ROWS) 93 sotp_add_ecc = false; 94 95 if (sotp_add_ecc) { 96 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), 97 SOTP_PROG_CONTROL__OTP_DISABLE_ECC); 98 } else { 99 io_setbits32((bcm_sotp_base + SOTP_PROG_CONTROL), 100 SOTP_PROG_CONTROL__OTP_DISABLE_ECC); 101 } 102 103 /* 10 bit row address */ 104 reg_val = (row_addr & SOTP_ADDR_MASK) << SOTP_ADDR__OTP_ROW_ADDR_R; 105 io_write32((bcm_sotp_base + SOTP_ADDR), reg_val); 106 reg_val = SOTP_READ; 107 io_write32((bcm_sotp_base + SOTP_CTRL_0), reg_val); 108 109 /* Start bit to tell SOTP to send command to the OTP controller */ 110 io_setbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); 111 112 /* Wait for SOTP command done to be set */ 113 ret = otp_status_done_wait((bcm_sotp_base + SOTP_STAT_0), 114 SOTP_STATUS_1__CMD_DONE); 115 if (ret) { 116 EMSG("FDONE cmd done wait failed and returned %#"PRIx32, ret); 117 return ret; 118 } 119 120 DMSG("CMD Done"); 121 122 /* Clr Start bit after command done */ 123 io_clrbits32((bcm_sotp_base + SOTP_CTRL_0), SOTP_CTRL_0__START); 124 read_data = io_read32(bcm_sotp_base + SOTP_RDDATA_1); 125 read_data = ((read_data & 0x1ff) << 32); 126 read_data |= io_read32(bcm_sotp_base + SOTP_RDDATA_0); 127 128 reg_val = io_read32(bcm_sotp_base + SOTP_STATUS_1); 129 /* No ECC check till SOTP_NO_ECC_ROWS */ 130 if (row_addr > SOTP_NO_ECC_ROWS && 131 reg_val & SOTP_STATUS_1__ECC_DET) { 132 EMSG("SOTP ECC ERROR Detected ROW %"PRIu32, row_addr); 133 read_data = SOTP_ECC_ERR_DETECT; 134 } 135 136 /* Command done is cleared */ 137 io_setbits32((bcm_sotp_base + SOTP_STATUS_1), SOTP_STATUS_1__CMD_DONE); 138 io_clrbits32((bcm_sotp_base + SOTP_PROG_CONTROL), 139 SOTP_PROG_CONTROL__OTP_CPU_MODE_EN); 140 DMSG("read done"); 141 142 *rdata = read_data; 143 return ret; 144 } 145 146 TEE_Result bcm_iproc_sotp_mem_write(uint32_t row_addr, bool sotp_add_ecc, 147 uint64_t wdata) 148 { 149 uint32_t chip_state = 0; 150 uint32_t chip_ctrl_default = 0; 151 uint32_t chip_ctrl = 0; 152 uint32_t loop = 0; 153 uint8_t prog_array[4] = { 0x0F, 0x04, 0x08, 0x0D }; 154 TEE_Result ret = TEE_SUCCESS; 155 156 assert(bcm_sotp_base); 157 158 chip_state = io_read32(bcm_sotp_base + SOTP_REGS_SOTP_CHIP_STATES); 159 160 if (chip_state & CHIP_STATE_DEFAULT) { 161 chip_ctrl_default = io_read32(bcm_sotp_base + SOTP_CHIP_CTRL); 162 DMSG("SOTP: enable special prog mode"); 163 164 chip_ctrl = BIT(SOTP_CHIP_CTRL_SW_OVERRIDE_CHIP_STATES) | 165 BIT(SOTP_CHIP_CTRL_SW_MANU_PROG) | 166 BIT(SOTP_CHIP_CTRL_SW_CID_PROG) | 167 BIT(SOTP_CHIP_CTRL_SW_AB_DEVICE); 168 169 io_write32(bcm_sotp_base + SOTP_CHIP_CTRL, chip_ctrl); 170 } 171 172 /* Check for FDONE status */ 173 ret = otp_status_done_wait(bcm_sotp_base + SOTP_STAT_0, 174 SOTP_STATUS_0__FDONE); 175 if (ret) { 176 EMSG("FDONE status done wait failed and returned %#"PRIx32, 177 ret); 178 return ret; 179 } 180 181 /* Enable OTP access by CPU */ 182 io_setbits32(bcm_sotp_base + SOTP_PROG_CONTROL, 183 SOTP_PROG_CONTROL__OTP_CPU_MODE_EN); 184 185 if (row_addr <= SOTP_NO_ECC_ROWS) { 186 if (sotp_add_ecc) { 187 io_setbits32(bcm_sotp_base + SOTP_PROG_CONTROL, 188 SOTP_PROG_CONTROL__OTP_ECC_WREN); 189 } else { 190 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, 191 SOTP_PROG_CONTROL__OTP_ECC_WREN); 192 } 193 } else { 194 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, 195 SOTP_PROG_CONTROL__OTP_ECC_WREN); 196 } 197 198 io_write32(bcm_sotp_base + SOTP_CTRL_0, SOTP_PROG_ENABLE << 1); 199 200 /* 201 * In order to avoid unintentional writes/programming of the OTP array, 202 * the OTP Controller must be put into programming mode before it will 203 * accept program commands. This is done by writing 0xF, 0x4, 0x8, 0xD 204 * with program commands prior to starting the actual programming 205 * sequence. 206 */ 207 for (loop = 0; loop < ARRAY_SIZE(prog_array); loop++) { 208 io_write32(bcm_sotp_base + SOTP_WRDATA_0, prog_array[loop]); 209 210 /* Bit to tell SOTP to send command to the OTP controller */ 211 io_setbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); 212 213 /* Wait for SOTP command done to be set */ 214 ret = otp_status_done_wait(bcm_sotp_base + SOTP_STATUS_1, 215 SOTP_STATUS_1__CMD_DONE); 216 if (ret) { 217 EMSG("FDONE cmd done wait failed and returned %"PRIx32, 218 ret); 219 return ret; 220 } 221 222 /* Command done is cleared w1c */ 223 io_setbits32(bcm_sotp_base + SOTP_STATUS_1, 224 SOTP_STATUS_1__CMD_DONE); 225 226 /* Clear Start bit after command done */ 227 io_clrbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); 228 } 229 230 /* Check for PROGOK */ 231 ret = otp_status_done_wait(bcm_sotp_base + SOTP_STAT_0, 232 SOTP_STATUS__PROGOK); 233 if (ret) { 234 EMSG("PROGOK cmd wait failed and returned %#"PRIx32, ret); 235 return ret; 236 } 237 238 /* Set 10 bit row address */ 239 io_write32(bcm_sotp_base + SOTP_ADDR, 240 (row_addr & SOTP_ADDR_MASK) << SOTP_ADDR__OTP_ROW_ADDR_R); 241 242 /* Set SOTP Row data */ 243 io_write32(bcm_sotp_base + SOTP_WRDATA_0, wdata & SOTP_ROW_DATA_MASK); 244 245 /* Set SOTP ECC and error bits */ 246 io_write32(bcm_sotp_base + SOTP_WRDATA_1, 247 (wdata & SOTP_ECC_ERR_BITS_MASK) >> 32); 248 249 /* Set prog_word command */ 250 io_write32(bcm_sotp_base + SOTP_CTRL_0, SOTP_PROG_WORD << 1); 251 252 /* Start bit to tell SOTP to send command to the OTP controller */ 253 io_setbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); 254 255 /* Wait for SOTP command done to be set */ 256 ret = otp_status_done_wait(bcm_sotp_base + SOTP_STATUS_1, 257 SOTP_STATUS_1__CMD_DONE); 258 if (ret) { 259 EMSG("CMD DONE wait failed and returned %#"PRIx32, ret); 260 return ret; 261 } 262 263 /* Command done is cleared w1c */ 264 io_setbits32(bcm_sotp_base + SOTP_STATUS_1, SOTP_STATUS_1__CMD_DONE); 265 266 /* disable OTP access by CPU */ 267 io_clrbits32(bcm_sotp_base + SOTP_PROG_CONTROL, 268 SOTP_PROG_CONTROL__OTP_CPU_MODE_EN); 269 270 /* Clr Start bit after command done */ 271 io_clrbits32(bcm_sotp_base + SOTP_CTRL_0, SOTP_CTRL_0__START); 272 273 if (chip_state & CHIP_STATE_DEFAULT) 274 io_write32(bcm_sotp_base + SOTP_CHIP_CTRL, chip_ctrl_default); 275 276 return TEE_SUCCESS; 277 } 278 279 static TEE_Result bcm_sotp_init(void) 280 { 281 bcm_sotp_base = (vaddr_t)phys_to_virt(SOTP_BASE, MEM_AREA_IO_SEC, 1); 282 283 DMSG("bcm_sotp init done"); 284 return TEE_SUCCESS; 285 } 286 287 service_init(bcm_sotp_init); 288