1 /* 2 * Copyright (C) 2017 Timesys Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <assert.h> 29 #include <drivers/atmel_uart.h> 30 #include <io.h> 31 #include <keep.h> 32 #include <util.h> 33 34 /* Register definitions */ 35 #define ATMEL_UART_CR 0x0000 /* Control Register */ 36 #define ATMEL_UART_MR 0x0004 /* Mode Register */ 37 #define ATMEL_UART_IER 0x0008 /* Interrupt Enable Register */ 38 #define ATMEL_UART_IDR 0x000c /* Interrupt Disable Register */ 39 #define ATMEL_UART_IMR 0x0010 /* Interrupt Mask Register */ 40 #define ATMEL_UART_SR 0x0014 /* Status Register */ 41 #define ATMEL_SR_RXRDY BIT(0) /* Receiver Ready */ 42 #define ATMEL_SR_TXRDY BIT(1) /* Transmitter Ready */ 43 #define ATMEL_SR_TXEMPTY BIT(1) /* Transmitter Ready */ 44 #define ATMEL_UART_RHR 0x0018 /* Receive Holding Register */ 45 #define ATMEL_UART_THR 0x001c /* Transmit Holding Register */ 46 #define ATMEL_UART_BRGR 0x0020 /* Baud Rate Generator Register */ 47 #define ATMEL_UART_CMPR 0x0024 /* Comparison Register */ 48 #define ATMEL_UART_RTOR 0x0028 /* Receiver Time-out Register */ 49 #define ATMEL_UART_WPMR 0x00e4 /* Write Protect Mode Register */ 50 51 static vaddr_t chip_to_base(struct serial_chip *chip) 52 { 53 struct atmel_uart_data *pd = 54 container_of(chip, struct atmel_uart_data, chip); 55 56 return io_pa_or_va(&pd->base); 57 } 58 59 static void atmel_uart_flush(struct serial_chip *chip) 60 { 61 vaddr_t base = chip_to_base(chip); 62 63 while (!(read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY)) 64 ; 65 } 66 67 static int atmel_uart_getchar(struct serial_chip *chip) 68 { 69 vaddr_t base = chip_to_base(chip); 70 71 while (read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY) 72 ; 73 74 return read32(base + ATMEL_UART_RHR); 75 } 76 77 static void atmel_uart_putc(struct serial_chip *chip, int ch) 78 { 79 vaddr_t base = chip_to_base(chip); 80 81 while (!(read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY)) 82 ; 83 84 write32(ch, base + ATMEL_UART_THR); 85 } 86 87 static const struct serial_ops atmel_uart_ops = { 88 .flush = atmel_uart_flush, 89 .getchar = atmel_uart_getchar, 90 .putc = atmel_uart_putc, 91 }; 92 93 void atmel_uart_init(struct atmel_uart_data *pd, paddr_t base) 94 { 95 pd->base.pa = base; 96 pd->chip.ops = &atmel_uart_ops; 97 98 /* 99 * Do nothing, debug uart share with normal world, 100 * everything for uart initialization is done in bootloader. 101 */ 102 } 103