1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2017 Timesys Corporation 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <assert.h> 30 #include <drivers/atmel_uart.h> 31 #include <io.h> 32 #include <keep.h> 33 #include <util.h> 34 35 /* Register definitions */ 36 #define ATMEL_UART_CR 0x0000 /* Control Register */ 37 #define ATMEL_UART_MR 0x0004 /* Mode Register */ 38 #define ATMEL_UART_IER 0x0008 /* Interrupt Enable Register */ 39 #define ATMEL_UART_IDR 0x000c /* Interrupt Disable Register */ 40 #define ATMEL_UART_IMR 0x0010 /* Interrupt Mask Register */ 41 #define ATMEL_UART_SR 0x0014 /* Status Register */ 42 #define ATMEL_SR_RXRDY BIT(0) /* Receiver Ready */ 43 #define ATMEL_SR_TXRDY BIT(1) /* Transmitter Ready */ 44 #define ATMEL_SR_TXEMPTY BIT(1) /* Transmitter Ready */ 45 #define ATMEL_UART_RHR 0x0018 /* Receive Holding Register */ 46 #define ATMEL_UART_THR 0x001c /* Transmit Holding Register */ 47 #define ATMEL_UART_BRGR 0x0020 /* Baud Rate Generator Register */ 48 #define ATMEL_UART_CMPR 0x0024 /* Comparison Register */ 49 #define ATMEL_UART_RTOR 0x0028 /* Receiver Time-out Register */ 50 #define ATMEL_UART_WPMR 0x00e4 /* Write Protect Mode Register */ 51 52 static vaddr_t chip_to_base(struct serial_chip *chip) 53 { 54 struct atmel_uart_data *pd = 55 container_of(chip, struct atmel_uart_data, chip); 56 57 return io_pa_or_va(&pd->base); 58 } 59 60 static void atmel_uart_flush(struct serial_chip *chip) 61 { 62 vaddr_t base = chip_to_base(chip); 63 64 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY)) 65 ; 66 } 67 68 static int atmel_uart_getchar(struct serial_chip *chip) 69 { 70 vaddr_t base = chip_to_base(chip); 71 72 while (io_read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY) 73 ; 74 75 return io_read32(base + ATMEL_UART_RHR); 76 } 77 78 static void atmel_uart_putc(struct serial_chip *chip, int ch) 79 { 80 vaddr_t base = chip_to_base(chip); 81 82 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY)) 83 ; 84 85 io_write32(base + ATMEL_UART_THR, ch); 86 } 87 88 static const struct serial_ops atmel_uart_ops = { 89 .flush = atmel_uart_flush, 90 .getchar = atmel_uart_getchar, 91 .putc = atmel_uart_putc, 92 }; 93 94 void atmel_uart_init(struct atmel_uart_data *pd, paddr_t base) 95 { 96 pd->base.pa = base; 97 pd->chip.ops = &atmel_uart_ops; 98 99 /* 100 * Do nothing, debug uart share with normal world, 101 * everything for uart initialization is done in bootloader. 102 */ 103 } 104