1*d3c37848SAkshay Belsare /* SPDX-License-Identifier: BSD-2-Clause */ 2*d3c37848SAkshay Belsare /* 3*d3c37848SAkshay Belsare * Copyright (C) 2002-2021 Xilinx, Inc. All rights reserved. 4*d3c37848SAkshay Belsare * Copyright (c) 2022 Foundries.io Ltd. (jorge@foundries.io) 5*d3c37848SAkshay Belsare * Copyright (c) 2024-2025, Advanced Micro Devices, Inc. All rights reserved. 6*d3c37848SAkshay Belsare * 7*d3c37848SAkshay Belsare */ 8*d3c37848SAkshay Belsare 9*d3c37848SAkshay Belsare #ifndef __GPIO_PRIVATE_H__ 10*d3c37848SAkshay Belsare #define __GPIO_PRIVATE_H__ 11*d3c37848SAkshay Belsare 12*d3c37848SAkshay Belsare #include <drivers/gpio.h> 13*d3c37848SAkshay Belsare #include <kernel/dt.h> 14*d3c37848SAkshay Belsare #include <stdlib.h> 15*d3c37848SAkshay Belsare #include <tee_api_types.h> 16*d3c37848SAkshay Belsare #include <util.h> 17*d3c37848SAkshay Belsare 18*d3c37848SAkshay Belsare #define GPIO_MAX_BANK 6 19*d3c37848SAkshay Belsare 20*d3c37848SAkshay Belsare #define PS_BANK_MAX 4 21*d3c37848SAkshay Belsare 22*d3c37848SAkshay Belsare #define GPIO_NUM_MAX 16 23*d3c37848SAkshay Belsare 24*d3c37848SAkshay Belsare #define GPIO_UPPER_MASK GENMASK_32(31, 16) 25*d3c37848SAkshay Belsare 26*d3c37848SAkshay Belsare #define DATA_LSW_OFFSET(__bank) (0x000 + 0x8 * (__bank)) 27*d3c37848SAkshay Belsare #define DATA_MSW_OFFSET(__bank) (0x004 + 0x8 * (__bank)) 28*d3c37848SAkshay Belsare #define DATA_RO_OFFSET(__bank) (0x060 + 0x4 * (__bank)) 29*d3c37848SAkshay Belsare #define DIRM_OFFSET(__bank) (0x204 + 0x40 * (__bank)) 30*d3c37848SAkshay Belsare #define OUTEN_OFFSET(__bank) (0x208 + 0x40 * (__bank)) 31*d3c37848SAkshay Belsare #define INTMASK_OFFSET(__bank) (0x20c + 0x40 * (__bank)) 32*d3c37848SAkshay Belsare #define INTEN_OFFSET(__bank) (0x210 + 0x40 * (__bank)) 33*d3c37848SAkshay Belsare #define INTDIS_OFFSET(__bank) (0x214 + 0x40 * (__bank)) 34*d3c37848SAkshay Belsare 35*d3c37848SAkshay Belsare struct amd_gbank_data { 36*d3c37848SAkshay Belsare const char *label; 37*d3c37848SAkshay Belsare uint16_t ngpio; 38*d3c37848SAkshay Belsare uint32_t max_bank; 39*d3c37848SAkshay Belsare uint32_t bank_min[GPIO_MAX_BANK]; 40*d3c37848SAkshay Belsare uint32_t bank_max[GPIO_MAX_BANK]; 41*d3c37848SAkshay Belsare }; 42*d3c37848SAkshay Belsare 43*d3c37848SAkshay Belsare struct amd_gpio_info { 44*d3c37848SAkshay Belsare struct amd_gbank_data *bdata; 45*d3c37848SAkshay Belsare struct gpio_chip chip; 46*d3c37848SAkshay Belsare vaddr_t vbase; 47*d3c37848SAkshay Belsare }; 48*d3c37848SAkshay Belsare 49*d3c37848SAkshay Belsare void amd_gpio_get_bank_and_pin(struct amd_gbank_data *bdata, uint32_t gpio, 50*d3c37848SAkshay Belsare uint32_t *bank, uint32_t *pin); 51*d3c37848SAkshay Belsare TEE_Result amd_gpio_get_dt(struct dt_pargs *pargs, void *data, 52*d3c37848SAkshay Belsare struct gpio **out_gpio); 53*d3c37848SAkshay Belsare 54*d3c37848SAkshay Belsare #endif /* __GPIO_PRIVATE_H__ */ 55