1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2022-2023 NXP 4 */ 5 6 #include <console.h> 7 #include <drivers/aplic.h> 8 #include <drivers/imsic.h> 9 #include <drivers/ns16550.h> 10 #include <drivers/plic.h> 11 #include <kernel/boot.h> 12 #include <kernel/tee_common_otp.h> 13 #include <platform_config.h> 14 15 #ifdef CFG_16550_UART 16 static struct ns16550_data console_data __nex_bss; 17 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART0_BASE, CORE_MMU_PGDIR_SIZE); 18 #endif 19 20 register_ddr(DRAM_BASE, DRAM_SIZE); 21 22 #if defined(CFG_RISCV_APLIC) || defined(CFG_RISCV_APLIC_MSI) 23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APLIC_BASE, 24 APLIC_SIZE); 25 #endif 26 #if defined(CFG_RISCV_APLIC_MSI) && defined(CFG_RISCV_IMSIC) 27 register_phys_mem_pgdir(MEM_AREA_IO_SEC, IMSIC_BASE, 28 IMSIC_SIZE); 29 #endif 30 31 #ifdef CFG_RISCV_PLIC 32 void boot_primary_init_intc(void) 33 { 34 plic_init(PLIC_BASE); 35 } 36 37 void boot_secondary_init_intc(void) 38 { 39 plic_hart_init(); 40 } 41 #endif /* CFG_RISCV_PLIC */ 42 43 #ifdef CFG_RISCV_APLIC 44 void boot_primary_init_intc(void) 45 { 46 aplic_init(APLIC_BASE); 47 } 48 49 void boot_secondary_init_intc(void) 50 { 51 aplic_init_per_hart(); 52 } 53 #endif /* CFG_RISCV_APLIC */ 54 55 #if defined(CFG_RISCV_APLIC_MSI) && defined(CFG_RISCV_IMSIC) 56 void boot_primary_init_intc(void) 57 { 58 aplic_init(APLIC_BASE); 59 imsic_init(IMSIC_BASE); 60 } 61 62 void boot_secondary_init_intc(void) 63 { 64 aplic_init_per_hart(); 65 imsic_init_per_hart(); 66 } 67 #endif 68 69 #ifdef CFG_16550_UART 70 void plat_console_init(void) 71 { 72 ns16550_init(&console_data, UART0_BASE, IO_WIDTH_U8, 0); 73 register_serial_console(&console_data.chip); 74 } 75 #endif 76 77 void interrupt_main_handler(void) 78 { 79 if (IS_ENABLED(CFG_RISCV_PLIC)) 80 plic_it_handle(); 81 else if (IS_ENABLED(CFG_RISCV_APLIC)) 82 aplic_it_handle(); 83 else if (IS_ENABLED(CFG_RISCV_APLIC_MSI) && 84 IS_ENABLED(CFG_RISCV_IMSIC)) 85 imsic_it_handle(); 86 } 87