xref: /optee_os/core/arch/riscv/kernel/csr_detect.S (revision 1868eb206733e931b6c6c2d85d55e646bc8a2496)
1/* SPDX-License-Identifier: BSD-2-Clause */
2/*
3 * Copyright (c) 2024 Andes Technology Corporation
4 */
5
6#include <asm.S>
7#include <riscv.h>
8
9#define DETECT_OP_CSRR		0
10#define DETECT_OP_CSRRW		1
11
12.macro save_and_disable_xie reg
13	csrrw	\reg, CSR_XIE, zero
14.endm
15
16.macro restore_xie reg
17	csrw	CSR_XIE, \reg
18.endm
19
20.macro save_and_replace_xtvec reg, label
21	la	\reg, \label
22	csrrw	\reg, CSR_XTVEC, \reg
23.endm
24
25.macro restore_xtvec reg
26	csrw	CSR_XTVEC, \reg
27.endm
28
29/**
30 * @brief A temporary trap handler to handle an exception during csr detection.
31 *        If csr read/write instruction leads to a trap, CPU will enter this
32 *        function and XRET with a0 = 0, which means the csr is not detected.
33 *        The caller must expect that a0 is used in this function.
34 */
35FUNC csr_detect_trap_vect , :
36	csrr	a0, CSR_XEPC
37	addi	a0, a0, 4
38	csrw	CSR_XEPC, a0
39	mv	a0, zero
40	XRET
41END_FUNC csr_detect_trap_vect
42
43/* Detect CSR by csrr/csrrw instruction. a0=1 if detected, otherwise a0=0 */
44.macro detect_csr csr, op, reg0, reg1, reg2
45	li	a0, 1
46	save_and_disable_xie \reg0
47	save_and_replace_xtvec \reg1, csr_detect_trap_vect
48.if \op == DETECT_OP_CSRR
49	csrr	\reg2, \csr
50.elseif \op == DETECT_OP_CSRRW
51	csrrw	\reg2, \csr, zero
52.endif
53	restore_xtvec \reg1
54	restore_xie \reg0
55.endm
56
57.macro detect_csr_by_csrr csr, reg0, reg1, reg2
58	detect_csr \csr, DETECT_OP_CSRR, \reg0, \reg1, \reg2
59.endm
60
61.macro detect_csr_by_csrrw csr, reg0, reg1, reg2
62	detect_csr \csr, DETECT_OP_CSRRW, \reg0, \reg1, \reg2
63.endm
64
65/**
66 * bool riscv_detect_csr_seed(void);
67 * @brief A helper function to detect if CSR seed is accessible. The value of a0
68 *        will be cleared by csr_detect_trap_vect() if exception occurs.
69 * @retval 1 if CSR seed is detected, otherwise 0
70 */
71FUNC riscv_detect_csr_seed , :
72	detect_csr_by_csrrw seed, a1, a2, a3
73	ret
74END_FUNC riscv_detect_csr_seed
75