1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2023 Andes Technology Corporation 4 * Copyright 2022-2023 NXP 5 */ 6 7 #include <assert.h> 8 #include <compiler.h> 9 #include <config.h> 10 #include <console.h> 11 #include <keep.h> 12 #include <kernel/boot.h> 13 #include <kernel/dt.h> 14 #include <kernel/linker.h> 15 #include <kernel/misc.h> 16 #include <kernel/panic.h> 17 #include <kernel/thread.h> 18 #include <mm/core_memprot.h> 19 #include <mm/core_mmu.h> 20 #include <mm/tee_mm.h> 21 #include <mm/tee_pager.h> 22 #include <platform_config.h> 23 #include <riscv.h> 24 #include <sbi.h> 25 #include <stdio.h> 26 #include <trace.h> 27 #include <util.h> 28 29 #define PADDR_INVALID ULONG_MAX 30 31 paddr_t start_addr; 32 unsigned long boot_args[4]; 33 34 uint32_t sem_cpu_sync[CFG_TEE_CORE_NB_CORE]; 35 36 #if defined(CFG_DT) 37 static int mark_tddram_as_reserved(struct dt_descriptor *dt) 38 { 39 return add_res_mem_dt_node(dt, "optee_core", CFG_TDDRAM_START, 40 CFG_TDDRAM_SIZE); 41 } 42 43 static void update_external_dt(void) 44 { 45 struct dt_descriptor *dt = get_external_dt_desc(); 46 47 if (!dt || !dt->blob) 48 return; 49 50 #ifdef CFG_CORE_RESERVED_SHM 51 if (mark_static_shm_as_reserved(dt)) 52 panic("Failed to config non-secure memory"); 53 #endif 54 55 if (mark_tddram_as_reserved(dt)) 56 panic("Failed to config secure memory"); 57 } 58 #else /*CFG_DT*/ 59 static void update_external_dt(void) 60 { 61 } 62 #endif /*!CFG_DT*/ 63 64 void init_sec_mon(unsigned long nsec_entry __maybe_unused) 65 { 66 assert(nsec_entry == PADDR_INVALID); 67 /* Do nothing as we don't have a secure monitor */ 68 } 69 70 #ifdef CFG_RISCV_S_MODE 71 static void start_secondary_cores(void) 72 { 73 size_t i = 0; 74 size_t pos = get_core_pos(); 75 76 for (i = 0; i < CFG_TEE_CORE_NB_CORE; i++) 77 if (i != pos && IS_ENABLED(CFG_RISCV_SBI) && 78 sbi_hsm_hart_start(i, start_addr, i)) 79 EMSG("Error starting secondary hart %zu", i); 80 } 81 #endif 82 83 static void init_runtime(void) 84 { 85 malloc_add_pool(__heap1_start, __heap1_end - __heap1_start); 86 87 IMSG_RAW("\n"); 88 } 89 90 void init_tee_runtime(void) 91 { 92 core_mmu_init_phys_mem(); 93 call_preinitcalls(); 94 call_initcalls(); 95 } 96 97 static void init_primary(unsigned long nsec_entry) 98 { 99 thread_init_core_local_stacks(); 100 101 /* 102 * Mask asynchronous exceptions before switch to the thread vector 103 * as the thread handler requires those to be masked while 104 * executing with the temporary stack. The thread subsystem also 105 * asserts that the foreign interrupts are blocked when using most of 106 * its functions. 107 */ 108 thread_set_exceptions(THREAD_EXCP_ALL); 109 110 init_runtime(); 111 thread_init_boot_thread(); 112 thread_init_primary(); 113 thread_init_per_cpu(); 114 init_sec_mon(nsec_entry); 115 } 116 117 /* May be overridden in plat-$(PLATFORM)/main.c */ 118 __weak void plat_primary_init_early(void) 119 { 120 } 121 122 /* May be overridden in plat-$(PLATFORM)/main.c */ 123 __weak void boot_primary_init_intc(void) 124 { 125 } 126 127 /* May be overridden in plat-$(PLATFORM)/main.c */ 128 __weak void boot_secondary_init_intc(void) 129 { 130 } 131 132 void boot_init_primary_early(void) 133 { 134 unsigned long e = PADDR_INVALID; 135 136 init_primary(e); 137 } 138 139 void boot_init_primary_late(unsigned long fdt, 140 unsigned long tos_fw_config __unused) 141 { 142 init_external_dt(fdt, CFG_DTB_MAX_SIZE); 143 discover_nsec_memory(); 144 update_external_dt(); 145 146 IMSG("OP-TEE version: %s", core_v_str); 147 if (IS_ENABLED(CFG_INSECURE)) { 148 IMSG("WARNING: This OP-TEE configuration might be insecure!"); 149 IMSG("WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html"); 150 } 151 IMSG("Primary CPU initializing"); 152 boot_primary_init_intc(); 153 init_tee_runtime(); 154 call_finalcalls(); 155 IMSG("Primary CPU initialized"); 156 157 #ifdef CFG_RISCV_S_MODE 158 start_secondary_cores(); 159 #endif 160 } 161 162 static void init_secondary_helper(unsigned long nsec_entry) 163 { 164 size_t pos = get_core_pos(); 165 166 IMSG("Secondary CPU %zu initializing", pos); 167 168 /* 169 * Mask asynchronous exceptions before switch to the thread vector 170 * as the thread handler requires those to be masked while 171 * executing with the temporary stack. The thread subsystem also 172 * asserts that the foreign interrupts are blocked when using most of 173 * its functions. 174 */ 175 thread_set_exceptions(THREAD_EXCP_ALL); 176 177 thread_init_per_cpu(); 178 init_sec_mon(nsec_entry); 179 boot_secondary_init_intc(); 180 181 IMSG("Secondary CPU %zu initialized", pos); 182 } 183 184 void boot_init_secondary(unsigned long nsec_entry __unused) 185 { 186 init_secondary_helper(PADDR_INVALID); 187 } 188